mipspy/README at master · breily/mipspy · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
MIPSpy - A MIPS Simulator
=========================

    * by:  brian reily
    * url: http://brianreily.com/project/mipspy

status
------
    * MIPSpy was written a while ago and just moved to github
      recently for safekeeping.  There may be a few bugs left
      but it is not being actively developed/maintained.

usage
-----
    * sample session:
        >>> import simulator
        >>> # Defaults are verbose=False, mem=1000, pc=0
        >>> s = simulator.Simulator()

        >>> s.run_line('line of code')
        >>> s.run_lines( ['line', 'line', 'line'] )

        >>> s.status()                  # show register, data, and pc status

        >>> s.get_register('$t0')       # manually retrieve a register value
        >>> s.get_register('$8')
        >>> s.get_register(9)

        >>> s.registers['$v0'] = 4      # manually set a register value
        >>> s.data[4] = 42              # manually set a data value

        >>> s.rerun()                   # reruns all previous instructions
        >>> s.instructions              # shows instructions in memory

        >>> s.reset()                   # reset all registers, data, pc

    * verbose mode will basically comment your code, as it shows you
      the starting values of operands, the operation, and then the ending
      values:
        >>> s.run_line('addi $t0, $0, 4')
        0: addi $t0, $0, 4      # $t0 = 0 + 4 = 4
        >>> s.run_line('addi $t0, $t0, 4')
        1: addi $t0, $t0, 4     # $t0 = 4 + 4 = 8

    * to read from a file:
        >>> s = simulator.Simulator()
        >>> s.run_lines( open(file, 'r').readlines() )

supported operations
--------------------
    syscall, j, b, jr, beq, bne, lw, sw, slt, slti, add, addi,
    sub, subi, and, andi, or, ori, sll, sllv, srl, srlv, div,
    mul, xor, xori, move

caveats
-------
    * div and mul are three register instructions like add and sub.

    * no memory addresses are assigned; memory is instead implemented
      as a list - this makes it very easy to test MIPS code but is bad
      if you need to use it for class.

    * there is no .data section - right now you have to manually input
      your .data section using 'Simulator.data[index] = value'

issues
------
    * verbose mode seems to be a bit buggy, trying to track it down.