quartus_project/stream_multdiv_hw.tcl at main · bccha/quartus_project · GitHub

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# TCL File Generated by Component Editor 20.1
# Sun Feb 08 01:30:30 EST 2026
# DO NOT MODIFY


#
# stream_multdiv "stream_multdiv" v1.0
#  2026.02.08.01:30:30
#
#

#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1


#
# module stream_multdiv
#
set_module_property DESCRIPTION ""
set_module_property NAME stream_multdiv
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME stream_multdiv
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL stream_processor
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file stream_processor.v VERILOG PATH RTL/stream_processor.v TOP_LEVEL_FILE


#
# parameters
#


#
# display items
#


#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset_n reset_n Input 1


#
# connection point avalon_streaming_source_0
#
add_interface avalon_streaming_source_0 avalon_streaming start
set_interface_property avalon_streaming_source_0 associatedClock clock
set_interface_property avalon_streaming_source_0 associatedReset reset
set_interface_property avalon_streaming_source_0 dataBitsPerSymbol 8
set_interface_property avalon_streaming_source_0 errorDescriptor ""
set_interface_property avalon_streaming_source_0 firstSymbolInHighOrderBits true
set_interface_property avalon_streaming_source_0 maxChannel 0
set_interface_property avalon_streaming_source_0 readyLatency 0
set_interface_property avalon_streaming_source_0 ENABLED true
set_interface_property avalon_streaming_source_0 EXPORT_OF ""
set_interface_property avalon_streaming_source_0 PORT_NAME_MAP ""
set_interface_property avalon_streaming_source_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_streaming_source_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_streaming_source_0 aso_valid valid Output 1
add_interface_port avalon_streaming_source_0 aso_data data Output 32
add_interface_port avalon_streaming_source_0 aso_ready ready Input 1


#
# connection point avalon_slave_0_1
#
add_interface avalon_slave_0_1 avalon end
set_interface_property avalon_slave_0_1 addressUnits WORDS
set_interface_property avalon_slave_0_1 associatedClock clock
set_interface_property avalon_slave_0_1 associatedReset reset
set_interface_property avalon_slave_0_1 bitsPerSymbol 8
set_interface_property avalon_slave_0_1 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0_1 burstcountUnits WORDS
set_interface_property avalon_slave_0_1 explicitAddressSpan 0
set_interface_property avalon_slave_0_1 holdTime 0
set_interface_property avalon_slave_0_1 linewrapBursts false
set_interface_property avalon_slave_0_1 maximumPendingReadTransactions 1
set_interface_property avalon_slave_0_1 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0_1 readLatency 0
set_interface_property avalon_slave_0_1 readWaitTime 1
set_interface_property avalon_slave_0_1 setupTime 0
set_interface_property avalon_slave_0_1 timingUnits Cycles
set_interface_property avalon_slave_0_1 writeWaitTime 0
set_interface_property avalon_slave_0_1 ENABLED true
set_interface_property avalon_slave_0_1 EXPORT_OF ""
set_interface_property avalon_slave_0_1 PORT_NAME_MAP ""
set_interface_property avalon_slave_0_1 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0_1 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0_1 avs_write write Input 1
add_interface_port avalon_slave_0_1 avs_writedata writedata Input 32
add_interface_port avalon_slave_0_1 avs_read read Input 1
add_interface_port avalon_slave_0_1 avs_readdata readdata Output 32
add_interface_port avalon_slave_0_1 avs_readdatavalid readdatavalid Output 1
add_interface_port avalon_slave_0_1 avs_address address Input 2
set_interface_assignment avalon_slave_0_1 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0_1 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0_1 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0_1 embeddedsw.configuration.isPrintableDevice 0


#
# connection point avalon_streaming_sink_0_1
#
add_interface avalon_streaming_sink_0_1 avalon_streaming end
set_interface_property avalon_streaming_sink_0_1 associatedClock clock
set_interface_property avalon_streaming_sink_0_1 associatedReset reset
set_interface_property avalon_streaming_sink_0_1 dataBitsPerSymbol 8
set_interface_property avalon_streaming_sink_0_1 errorDescriptor ""
set_interface_property avalon_streaming_sink_0_1 firstSymbolInHighOrderBits true
set_interface_property avalon_streaming_sink_0_1 maxChannel 0
set_interface_property avalon_streaming_sink_0_1 readyLatency 0
set_interface_property avalon_streaming_sink_0_1 ENABLED true
set_interface_property avalon_streaming_sink_0_1 EXPORT_OF ""
set_interface_property avalon_streaming_sink_0_1 PORT_NAME_MAP ""
set_interface_property avalon_streaming_sink_0_1 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_streaming_sink_0_1 SVD_ADDRESS_GROUP ""

add_interface_port avalon_streaming_sink_0_1 asi_valid valid Input 1
add_interface_port avalon_streaming_sink_0_1 asi_data data Input 32
add_interface_port avalon_streaming_sink_0_1 asi_ready ready Output 1