From 3fba80518db407bc01d1110d6a8d96c87a9294d0 Mon Sep 17 00:00:00 2001 From: Timor Knudsen Date: Sun, 22 Mar 2026 15:20:04 +0100 Subject: [PATCH] Fix README.md badge --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 1257005..4a1c9ea 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ ![banner](docs/img/mini-isp.png) --> -[![Synthesis](https://github.com/amd/mini-isp/actions/workflows/synthesis.yml/badge.svg?event=push)](https://github.com/amd/mini-isp/actions/workflows/synthesis.yml) [![Test](https://github.com/amd/mini-isp/actions/workflows/test.yml/badge.svg?event=push)](https://github.com/amd/mini-isp/actions/workflows/test.yml) [![Simulation](https://github.com/amd/mini-isp/actions/workflows/simulation.yml/badge.svg?event=push)](https://github.com/amd/mini-isp/actions/workflows/simulation.yml) +[![Lint, simulate, synthesize, test and docs](https://github.com/amd/mini-isp/actions/workflows/cicd.yml/badge.svg)](https://github.com/amd/mini-isp/actions/workflows/cicd.yml) A minimal, open-source Image Signal Processor (ISP) for AMD FPGA, implemented in Verilog.