xilpm: versal: server: Add XRAM AXI-lite workaround for ES1 devices

XRAM AXI-lite configuration is not supported in Vivado for VE2302 and VM1102
ES1 devices. Add a workaround to skip AXI-lite enablement on these devices.

Signed-off-by: Nicole Baze <amanda.baze@amd.com>

Acked-by:Trung Tran<trungt@amd.com>

Author: Baze, Amanda

lib/sw_services/xilpm/src/versal/server/xpm_common_plat.h

@@ -126,6 +126,12 @@ extern "C" {
 /* VP1902 */
 #define PMC_TAP_IDCODE_DEV_VP1902		((u32)0x0U << XPM_PMC_TAP_IDCODE_DEV_SHIFT)
 #define PMC_TAP_IDCODE_DEV_SBFMLY_VP1902	(XPM_PMC_TAP_IDCODE_SBFMLY_P_HS | PMC_TAP_IDCODE_DEV_VP1902)
+/* VE2302 */
+#define PMC_TAP_IDCODE_DEV_VE2302               ((u32)0x8U << XPM_PMC_TAP_IDCODE_DEV_SHIFT)
+#define PMC_TAP_IDCODE_DEV_SBFMLY_VE2302        (XPM_PMC_TAP_IDCODE_SBFMLY_SV | PMC_TAP_IDCODE_DEV_VE2302)
+/* VM1102 */
+#define PMC_TAP_IDCODE_DEV_VM1102               ((u32)0xAU << XPM_PMC_TAP_IDCODE_DEV_SHIFT)
+#define PMC_TAP_IDCODE_DEV_SBFMLY_VM1102        (XPM_PMC_TAP_IDCODE_SBFMLY_SV | PMC_TAP_IDCODE_DEV_VM1102)
 
 #define SLR_TYPE_MONOLITHIC_DEV			(0x7U)
 #define SLR_TYPE_SSIT_DEV_MASTER_SLR		(0x6U)

lib/sw_services/xilpm/src/versal/server/xpm_domain_iso.c

@@ -654,10 +654,20 @@ XStatus XPmDomainIso_Control(u32 IsoIdx, u32 Enable)
 			}
 
 			if ((u32)XPM_NODEIDX_ISO_XRAM_PL_AXILITE == IsoIdx) {
-				/* Select AXI lite clock from PL */
-				XPm_RMW32(XRAM_SLCR_BASEADDR + XRAM_SLCR_APB_CLK_OFFSET,
-					  XRAM_SLCR_APB_CLK_SRC_AXI_LITE_CLK_MASK,
-					  XRAM_SLCR_APB_CLK_SRC_AXI_LITE_CLK_MASK);
+				/*
+				 * Vivado does not support XRAM AXI-lite for VE2302/VM1102 ES1 devices.
+				 * Skip AXI-lite clock source selection for these devices.
+				 */
+				if (!((((u32)PLATFORM_VERSION_SILICON_ES1 == XPm_GetPlatformVersion()) &&
+				       (PMC_TAP_IDCODE_DEV_SBFMLY_VE2302 == (XPm_GetIdCode() & PMC_TAP_IDCODE_DEV_SBFMLY_MASK))) ||
+				      (((u32)PLATFORM_VERSION_SILICON_ES1 == XPm_GetPlatformVersion()) &&
+				       (PMC_TAP_IDCODE_DEV_SBFMLY_VM1102 == (XPm_GetIdCode() & PMC_TAP_IDCODE_DEV_SBFMLY_MASK))))) {
+
+					/* Select AXI lite clock from PL */
+					XPm_RMW32(XRAM_SLCR_BASEADDR + XRAM_SLCR_APB_CLK_OFFSET,
+						  XRAM_SLCR_APB_CLK_SRC_AXI_LITE_CLK_MASK,
+						  XRAM_SLCR_APB_CLK_SRC_AXI_LITE_CLK_MASK);
+				}
 			}
 		} else {
 			if (((u32)XPM_NODEIDX_ISO_XRAM_PL_AXI0 <= IsoIdx) &&