From 8e27436e88d6117c0318976077938079a243766a Mon Sep 17 00:00:00 2001
From: Saurav Singh <saurav.singh@fermions.co>
Date: Sat, 20 Jun 2026 08:30:47 +0000
Subject: [PATCH] drt: allow auto-taper to be disabled per net (#9995)

The detailed router auto-tapers NDR (wide) nets down to minimum width
near pin connections, gated globally by AUTO_TAPER_NDR_NETS. Previously
the only way to keep an NDR net (e.g. a wide analog trace) at full width
to the pin was to disable tapering globally by editing
src/drt/src/global.h and recompiling.

Add per-net control:

- odb: new dbNet flag disable_auto_taper (reuses a spare flag bit),
  exposed via dbNet::disableAutoTaper()/setDisableAutoTaper(), gated by
  new schema revision kSchemaNetDisableAutoTaper. Mirrors hasJumpers().
- Tcl: set_routing_disable_auto_taper (-net name | -all_clocks)
  [-disable] [-enable], modeled on assign_ndr.
- drt: frNet carries the flag (read in io::Parser::addNet); new
  drNet::autoTaperEnabled() helper gates the in-scope taper decisions in
  FlexDR_maze, FlexPA_acc_point and FlexPA_unique. The pin taper boxes
  are not created for disabled nets, so downstream tapering is skipped.

The global default (auto-taper on) is unchanged; existing ndr_vias
goldens are unaffected. Adds drt/test/ndr_no_auto_taper showing a
disabled net keeps full NDR width while other NDR nets still taper.

Signed-off-by: Saurav Singh <saurav.singh@fermions.co>
---
 src/OpenRoad.tcl                     |  34 ++
 src/drt/README.md                    |  29 +-
 src/drt/src/db/drObj/drNet.cpp       |   7 +-
 src/drt/src/db/drObj/drNet.h         |   4 +
 src/drt/src/db/obj/frNet.h           |   7 +
 src/drt/src/dr/FlexDR_maze.cpp       |   8 +-
 src/drt/src/io/io.cpp                |   1 +
 src/drt/src/pa/FlexPA_acc_point.cpp  |   9 +-
 src/drt/src/pa/FlexPA_unique.cpp     |  17 +-
 src/drt/src/pa/FlexPA_unique.h       |   1 +
 src/drt/test/BUILD                   |   2 +
 src/drt/test/CMakeLists.txt          |   2 +
 src/drt/test/ndr_no_auto_taper.defok | 516 +++++++++++++++++++++++++++
 src/drt/test/ndr_no_auto_taper.ok    |  56 +++
 src/drt/test/ndr_no_auto_taper.tcl   |  38 ++
 src/odb/include/odb/db.h             |  11 +
 src/odb/src/db/dbDatabase.h          |   4 +-
 src/odb/src/db/dbNet.cpp             |  26 +-
 src/odb/src/db/dbNet.h               |   2 +-
 19 files changed, 762 insertions(+), 12 deletions(-)
 create mode 100644 src/drt/test/ndr_no_auto_taper.defok
 create mode 100644 src/drt/test/ndr_no_auto_taper.ok
 create mode 100644 src/drt/test/ndr_no_auto_taper.tcl

diff --git a/src/OpenRoad.tcl b/src/OpenRoad.tcl
index 0395064e1a7..2a3c5e42804 100644
--- a/src/OpenRoad.tcl
+++ b/src/OpenRoad.tcl
@@ -295,6 +295,40 @@ proc assign_ndr { args } {
   }
 }
 
+sta::define_cmd_args "set_routing_disable_auto_taper" \
+  { (-net name | -all_clocks) [-disable] [-enable] }
+
+# Per-net control of the detailed router's auto-taper behavior.  By default
+# the detailed router tapers NDR (wide) nets down to minimum width near pin
+# connections.  Some nets (e.g. wide analog/NDR traces) must keep their full
+# width all the way to the pin; use -disable to suppress auto-taper for those
+# nets without recompiling.  Use -enable to restore the default behavior.
+proc set_routing_disable_auto_taper { args } {
+  sta::parse_key_args "set_routing_disable_auto_taper" args \
+    keys {-net} flags {-all_clocks -disable -enable}
+  if { !([info exists keys(-net)] ^ [info exists flags(-all_clocks)]) } {
+    utl::error ORD 1016 "Either -net or -all_clocks need to be defined."
+  }
+  if { [info exists flags(-disable)] && [info exists flags(-enable)] } {
+    utl::error ORD 1017 "Only one of -disable or -enable may be specified."
+  }
+  # Default action is to disable auto-taper.
+  set disable [expr { ![info exists flags(-enable)] }]
+  set block [[[ord::get_db] getChip] getBlock]
+  if { [info exists keys(-net)] } {
+    set netName $keys(-net)
+    set net [$block findNet $netName]
+    if { $net == "NULL" } {
+      utl::error ORD 1018 "No net named ${netName} found."
+    }
+    $net setDisableAutoTaper $disable
+  } else {
+    foreach net [sta::find_all_clk_nets] {
+      $net setDisableAutoTaper $disable
+    }
+  }
+}
+
 sta::define_cmd_args "set_debug_level" { tool group level }
 proc set_debug_level { args } {
   sta::check_argc_eq3 "set_debug_level" $args
diff --git a/src/drt/README.md b/src/drt/README.md
index 2fdeef94f6c..65c83f32118 100644
--- a/src/drt/README.md
+++ b/src/drt/README.md
@@ -98,13 +98,40 @@ detailed_route
 
 #### Developer arguments
 
-Some arguments that are helpful for developers are listed here. 
+Some arguments that are helpful for developers are listed here.  
 
 | Switch Name | Description |
 | ----- | ----- |
 | `-or_seed` | Random seed for the order of nets to reroute. The default value is `-1`, and the allowed values are integers `[0, MAX_INT]`. | 
 | `-or_k` | Number of swaps is given by $k * sizeof(rerouteNets)$. The default value is `0`, and the allowed values are integers `[0, MAX_INT]`. |
 
+### Disable Auto-Taper Per Net
+
+By default the detailed router tapers non-default-rule (NDR, i.e. wide)
+nets down to minimum width near pin connections so that they fit the pin
+access geometry. For some nets (for example wide analog/NDR traces) this
+tapering is undesirable and the net must keep its full NDR width all the
+way to the pin. The following command disables auto-taper on a per-net
+basis, without recompiling. The global default behavior (auto-taper
+enabled) is unchanged for all other nets.
+
+```tcl
+set_routing_disable_auto_taper
+    (-net name | -all_clocks)
+    [-disable]
+    [-enable]
+```
+
+#### Options
+
+| Switch Name | Description |
+| ----- | ----- |
+| `-net` | Name of the net to mark. Mutually exclusive with `-all_clocks`. |
+| `-all_clocks` | Apply to all clock nets. Mutually exclusive with `-net`. |
+| `-disable` | Disable auto-taper for the selected net(s). This is the default action if neither `-disable` nor `-enable` is given. |
+| `-enable` | Re-enable auto-taper for the selected net(s), restoring the default behavior. |
+
+
 ### Detailed Route Debugging
 
 The following command and arguments are useful when debugging error
diff --git a/src/drt/src/db/drObj/drNet.cpp b/src/drt/src/db/drObj/drNet.cpp
index 2ba0c4b7946..888b213bfb0 100644
--- a/src/drt/src/db/drObj/drNet.cpp
+++ b/src/drt/src/db/drObj/drNet.cpp
@@ -14,7 +14,7 @@
 #include "db/obj/frAccess.h"
 #include "db/obj/frBTerm.h"
 #include "db/obj/frBlockObject.h"
-#include "db/obj/frInstTerm.h"
+#include "db/obj/frNet.h" #include "db/obj/frInstTerm.h"
 #include "distributed/frArchive.h"
 #include "dr/FlexDR.h"
 #include "frBaseTypes.h"
@@ -106,6 +106,11 @@ bool drNet::hasNDR() const
   return getFrNet()->getNondefaultRule() != nullptr;
 }
 
+bool drNet::autoTaperEnabled(bool global_enabled) const
+{
+  return global_enabled && !fNet_->isAutoTaperDisabled();
+}
+
 bool drNet::isClockNet() const
 {
   return fNet_->isClock();
diff --git a/src/drt/src/db/drObj/drNet.h b/src/drt/src/db/drObj/drNet.h
index 0d44514ba86..aa706d95431 100644
--- a/src/drt/src/db/drObj/drNet.h
+++ b/src/drt/src/db/drObj/drNet.h
@@ -60,6 +60,10 @@ class drNet : public drBlockObject
   void clearRouteConnFigs() { routeConnFigs_.clear(); }
   frNet* getFrNet() const { return fNet_; }
   void setFrNet(frNet* net) { fNet_ = net; }
+  // True when this net should still be auto-tapered to min width near pins.
+  // Honors both the global AUTO_TAPER_NDR_NETS config and the per-net
+  // disable flag carried on the frNet.
+  bool autoTaperEnabled(bool global_enabled) const;
   const frOrderedIdSet<frBlockObject*>& getFrNetTerms() const
   {
     return fNetTerms_;
diff --git a/src/drt/src/db/obj/frNet.h b/src/drt/src/db/obj/frNet.h
index 7934ccd7b07..b52d50f3033 100644
--- a/src/drt/src/db/obj/frNet.h
+++ b/src/drt/src/db/obj/frNet.h
@@ -166,6 +166,10 @@ class frNet : public frBlockObject
   bool hasJumpers() { return has_jumpers_; }
   void setToBeDeleted(bool to_be_deleted) { to_be_deleted_ = to_be_deleted; }
   bool toBeDeleted() { return to_be_deleted_; }
+  // When true, DRT must not auto-taper this net to minimum width near pin
+  // connections (per-net override of router_cfg_->AUTO_TAPER_NDR_NETS).
+  void setDisableAutoTaper(bool in) { disable_auto_taper_ = in; }
+  bool isAutoTaperDisabled() const { return disable_auto_taper_; }
 
  protected:
   frString name_;
@@ -194,5 +198,8 @@ class frNet : public frBlockObject
   bool has_jumpers_{false};
   std::vector<frPinFig*> all_pinfigs_;
   bool to_be_deleted_{false};
+  // Per-net override: when true, auto-taper to min width near pins is
+  // suppressed for this net even if AUTO_TAPER_NDR_NETS is globally enabled.
+  bool disable_auto_taper_{false};
 };
 }  // namespace drt
diff --git a/src/drt/src/dr/FlexDR_maze.cpp b/src/drt/src/dr/FlexDR_maze.cpp
index 0027452e782..b02017da48d 100644
--- a/src/drt/src/dr/FlexDR_maze.cpp
+++ b/src/drt/src/dr/FlexDR_maze.cpp
@@ -2229,7 +2229,7 @@ void FlexDRWorker::routeNet_prep(
     }
     unConnPins.insert(pin.get());
     if (gridGraph_.getNDR()) {
-      if (router_cfg_->AUTO_TAPER_NDR_NETS
+      if (net->autoTaperEnabled(router_cfg_->AUTO_TAPER_NDR_NETS)
           && pin->isInstPin()) {  // create a taper box for each pin
         auto [l, h] = pin->getAPBbox();
         frCoord pitch
@@ -2648,7 +2648,8 @@ void FlexDRWorker::routeNet_postAstarWritePath(
           via = net_ndr->getPrefVia(startLayerNum / 2 - 1);
         }
         auto currVia = std::make_unique<drVia>(via);
-        if (net->hasNDR() && router_cfg_->AUTO_TAPER_NDR_NETS) {
+        if (net->hasNDR()
+            && net->autoTaperEnabled(router_cfg_->AUTO_TAPER_NDR_NETS)) {
           if (isInsideTaperBox(endX, endY, startZ, endZ, mazeIdx2TaperBox)) {
             currVia->setTapered(true);
           }
@@ -2818,7 +2819,8 @@ bool FlexDRWorker::splitPathSeg(frMIdx& midX,
                                 drNet* net)
 {
   taperFirstPiece = false;
-  if (!net->hasNDR() || !router_cfg_->AUTO_TAPER_NDR_NETS) {
+  if (!net->hasNDR()
+      || !net->autoTaperEnabled(router_cfg_->AUTO_TAPER_NDR_NETS)) {
     return false;
   }
   frBox3D* bx = nullptr;
diff --git a/src/drt/src/io/io.cpp b/src/drt/src/io/io.cpp
index a6683962ebb..7d6db388906 100644
--- a/src/drt/src/io/io.cpp
+++ b/src/drt/src/io/io.cpp
@@ -1053,6 +1053,7 @@ frNet* io::Parser::addNet(odb::dbNet* db_net)
   }
   net_in->setHasJumpers(has_jumpers);
   net_in->setIsConnectedByAbutment(is_abuted);
+  net_in->setDisableAutoTaper(db_net->disableAutoTaper());
   updateNetRouting(net_in.get(), db_net);
   net_in->setType(db_net->getSigType());
   frNet* raw_net_in = net_in.get();
diff --git a/src/drt/src/pa/FlexPA_acc_point.cpp b/src/drt/src/pa/FlexPA_acc_point.cpp
index d146df97e0e..244d7c79469 100644
--- a/src/drt/src/pa/FlexPA_acc_point.cpp
+++ b/src/drt/src/pa/FlexPA_acc_point.cpp
@@ -1059,13 +1059,16 @@ bool FlexPA::isViaViolationFree(frAccessPoint* ap,
   design_rule_checker.setExtBox(ext_box);
   design_rule_checker.setDrcBox(ext_box);
   if (inst_term) {
-    if (!inst_term->getNet() || !inst_term->getNet()->getNondefaultRule()
-        || router_cfg_->AUTO_TAPER_NDR_NETS) {
+    auto* it_net = inst_term->getNet();
+    if (!it_net || !it_net->getNondefaultRule()
+        || (router_cfg_->AUTO_TAPER_NDR_NETS
+            && !it_net->isAutoTaperDisabled())) {
       design_rule_checker.addTargetObj(inst_term->getInst());
     }
   } else {
     if (!pin_net || !pin_net->getNondefaultRule()
-        || router_cfg_->AUTO_TAPER_NDR_NETS) {
+        || (router_cfg_->AUTO_TAPER_NDR_NETS
+            && !pin_net->isAutoTaperDisabled())) {
       design_rule_checker.addTargetObj(pin_term);
     }
   }
diff --git a/src/drt/src/pa/FlexPA_unique.cpp b/src/drt/src/pa/FlexPA_unique.cpp
index b47651af35b..169e9dd4512 100644
--- a/src/drt/src/pa/FlexPA_unique.cpp
+++ b/src/drt/src/pa/FlexPA_unique.cpp
@@ -167,6 +167,21 @@ bool UniqueInsts::isNDRInst(frInst* inst) const
   return false;
 }
 
+bool UniqueInsts::isNoAutoTaperNDRInst(frInst* inst) const
+{
+  // An instance whose pin access must be computed without auto-taper:
+  // it touches an NDR net for which tapering is suppressed, either
+  // globally (!AUTO_TAPER_NDR_NETS) or per-net (disable_auto_taper).
+  for (const auto& a : inst->getInstTerms()) {
+    auto* net = a->getNet();
+    if (net && net->getNondefaultRule()
+        && (!router_cfg_->AUTO_TAPER_NDR_NETS || net->isAutoTaperDisabled())) {
+      return true;
+    }
+  }
+  return false;
+}
+
 UniqueClassKey UniqueInsts::computeUniqueClassKey(frInst* inst) const
 {
   const odb::Point origin = inst->getOrigin();
@@ -196,7 +211,7 @@ UniqueClassKey UniqueInsts::computeUniqueClassKey(frInst* inst) const
   }
   // Special case for NDR instances, create a separate unique class for them
   frInst* ndr_inst = nullptr;
-  if (!router_cfg_->AUTO_TAPER_NDR_NETS && isNDRInst(inst)) {
+  if (isNoAutoTaperNDRInst(inst)) {
     ndr_inst = inst;
   }
   std::set<frTerm*> stubborn_terms;
diff --git a/src/drt/src/pa/FlexPA_unique.h b/src/drt/src/pa/FlexPA_unique.h
index 989df7377ef..7990aac1eb1 100644
--- a/src/drt/src/pa/FlexPA_unique.h
+++ b/src/drt/src/pa/FlexPA_unique.h
@@ -193,6 +193,7 @@ class UniqueInsts
    * terminal.
    */
   bool isNDRInst(frInst* inst) const;
+  bool isNoAutoTaperNDRInst(frInst* inst) const;
   bool hasTrackPattern(frTrackPattern* tp, const odb::Rect& box) const;
 
   /**
diff --git a/src/drt/test/BUILD b/src/drt/test/BUILD
index d2b5d59062c..48ccd548f7d 100644
--- a/src/drt/test/BUILD
+++ b/src/drt/test/BUILD
@@ -18,6 +18,7 @@ COMPULSORY_TESTS = [
     "ndr_vias1",
     "ndr_vias2",
     "ndr_vias3",
+    "ndr_no_auto_taper",
     "obstruction",
     "single_step",
     "ta_ap_aligned",
@@ -36,6 +37,7 @@ ALL_TESTS = COMPULSORY_TESTS + PASSFAIL_TESTS
 BIG_TESTS = [
     "ndr_vias1",
     "ndr_vias2",
+    "ndr_no_auto_taper",
 ]
 
 PY_TESTS = [
diff --git a/src/drt/test/CMakeLists.txt b/src/drt/test/CMakeLists.txt
index f0df1b5c6ed..9957a9d3135 100644
--- a/src/drt/test/CMakeLists.txt
+++ b/src/drt/test/CMakeLists.txt
@@ -8,6 +8,7 @@ or_integration_tests(
     ndr_vias1
     ndr_vias2
     ndr_vias3
+    ndr_no_auto_taper
     obstruction
     single_step
     ta_ap_aligned
@@ -22,5 +23,6 @@ or_integration_tests(
 set_tests_properties(
   drt.ndr_vias1.tcl
   drt.ndr_vias2.tcl
+  drt.ndr_no_auto_taper.tcl
   PROPERTIES TIMEOUT 900
 )
diff --git a/src/drt/test/ndr_no_auto_taper.defok b/src/drt/test/ndr_no_auto_taper.defok
new file mode 100644
index 00000000000..4b705f5512a
--- /dev/null
+++ b/src/drt/test/ndr_no_auto_taper.defok
@@ -0,0 +1,516 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN gcd ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 299960 300130 ) ;
+ROW ROW_0 unithd 10120 10880 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_1 unithd 10120 13600 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_2 unithd 10120 16320 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_3 unithd 10120 19040 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_4 unithd 10120 21760 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_5 unithd 10120 24480 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_6 unithd 10120 27200 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_7 unithd 10120 29920 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_8 unithd 10120 32640 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_9 unithd 10120 35360 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_10 unithd 10120 38080 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_11 unithd 10120 40800 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_12 unithd 10120 43520 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_13 unithd 10120 46240 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_14 unithd 10120 48960 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_15 unithd 10120 51680 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_16 unithd 10120 54400 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_17 unithd 10120 57120 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_18 unithd 10120 59840 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_19 unithd 10120 62560 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_20 unithd 10120 65280 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_21 unithd 10120 68000 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_22 unithd 10120 70720 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_23 unithd 10120 73440 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_24 unithd 10120 76160 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_25 unithd 10120 78880 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_26 unithd 10120 81600 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_27 unithd 10120 84320 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_28 unithd 10120 87040 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_29 unithd 10120 89760 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_30 unithd 10120 92480 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_31 unithd 10120 95200 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_32 unithd 10120 97920 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_33 unithd 10120 100640 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_34 unithd 10120 103360 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_35 unithd 10120 106080 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_36 unithd 10120 108800 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_37 unithd 10120 111520 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_38 unithd 10120 114240 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_39 unithd 10120 116960 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_40 unithd 10120 119680 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_41 unithd 10120 122400 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_42 unithd 10120 125120 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_43 unithd 10120 127840 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_44 unithd 10120 130560 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_45 unithd 10120 133280 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_46 unithd 10120 136000 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_47 unithd 10120 138720 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_48 unithd 10120 141440 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_49 unithd 10120 144160 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_50 unithd 10120 146880 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_51 unithd 10120 149600 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_52 unithd 10120 152320 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_53 unithd 10120 155040 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_54 unithd 10120 157760 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_55 unithd 10120 160480 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_56 unithd 10120 163200 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_57 unithd 10120 165920 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_58 unithd 10120 168640 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_59 unithd 10120 171360 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_60 unithd 10120 174080 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_61 unithd 10120 176800 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_62 unithd 10120 179520 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_63 unithd 10120 182240 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_64 unithd 10120 184960 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_65 unithd 10120 187680 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_66 unithd 10120 190400 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_67 unithd 10120 193120 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_68 unithd 10120 195840 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_69 unithd 10120 198560 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_70 unithd 10120 201280 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_71 unithd 10120 204000 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_72 unithd 10120 206720 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_73 unithd 10120 209440 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_74 unithd 10120 212160 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_75 unithd 10120 214880 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_76 unithd 10120 217600 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_77 unithd 10120 220320 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_78 unithd 10120 223040 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_79 unithd 10120 225760 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_80 unithd 10120 228480 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_81 unithd 10120 231200 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_82 unithd 10120 233920 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_83 unithd 10120 236640 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_84 unithd 10120 239360 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_85 unithd 10120 242080 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_86 unithd 10120 244800 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_87 unithd 10120 247520 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_88 unithd 10120 250240 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_89 unithd 10120 252960 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_90 unithd 10120 255680 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_91 unithd 10120 258400 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_92 unithd 10120 261120 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_93 unithd 10120 263840 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_94 unithd 10120 266560 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_95 unithd 10120 269280 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_96 unithd 10120 272000 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_97 unithd 10120 274720 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_98 unithd 10120 277440 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_99 unithd 10120 280160 FS DO 608 BY 1 STEP 460 0 ;
+ROW ROW_100 unithd 10120 282880 N DO 608 BY 1 STEP 460 0 ;
+ROW ROW_101 unithd 10120 285600 FS DO 608 BY 1 STEP 460 0 ;
+TRACKS X 230 DO 652 STEP 460 LAYER li1 ;
+TRACKS Y 170 DO 882 STEP 340 LAYER li1 ;
+TRACKS X 170 DO 882 STEP 340 LAYER met1 ;
+TRACKS Y 170 DO 883 STEP 340 LAYER met1 ;
+TRACKS X 230 DO 652 STEP 460 LAYER met2 ;
+TRACKS Y 230 DO 652 STEP 460 LAYER met2 ;
+TRACKS X 340 DO 441 STEP 680 LAYER met3 ;
+TRACKS Y 340 DO 441 STEP 680 LAYER met3 ;
+TRACKS X 460 DO 326 STEP 920 LAYER met4 ;
+TRACKS Y 460 DO 326 STEP 920 LAYER met4 ;
+TRACKS X 1700 DO 88 STEP 3400 LAYER met5 ;
+TRACKS Y 1700 DO 88 STEP 3400 LAYER met5 ;
+GCELLGRID X 0 DO 43 STEP 6900 ;
+GCELLGRID Y 0 DO 43 STEP 6900 ;
+VIAS 4 ;
+    - via2_3_1600_480_1_5_320_320 + VIARULE M1M2_PR + CUTSIZE 150 150  + LAYERS met1 via met2  + CUTSPACING 170 170  + ENCLOSURE 85 165 55 85  + ROWCOL 1 5  ;
+    - via3_4_1600_480_1_4_400_400 + VIARULE M2M3_PR + CUTSIZE 200 200  + LAYERS met2 via2 met3  + CUTSPACING 200 200  + ENCLOSURE 40 85 65 65  + ROWCOL 1 4  ;
+    - via4_5_1600_480_1_4_400_400 + VIARULE M3M4_PR + CUTSIZE 200 200  + LAYERS met3 via3 met4  + CUTSPACING 200 200  + ENCLOSURE 90 60 100 65  + ROWCOL 1 4  ;
+    - via5_6_1600_1600_1_1_1600_1600 + VIARULE M4M5_PR + CUTSIZE 800 800  + LAYERS met4 via4 met5  + CUTSPACING 800 800  + ENCLOSURE 400 190 310 400  ;
+END VIAS
+NONDEFAULTRULES 1 ;
+    - NDR_3W_3S
+      + LAYER li1 WIDTH 510 SPACING 510
+      + LAYER met1 WIDTH 420 SPACING 420
+      + LAYER met2 WIDTH 420 SPACING 420
+      + LAYER met3 WIDTH 900 SPACING 900
+      + LAYER met4 WIDTH 900 SPACING 900
+      + LAYER met5 WIDTH 4800 SPACING 4800
+      + VIA L1M1_PR_R
+      + VIA M1M2_PR_R
+    ;
+END NONDEFAULTRULES
+COMPONENTS 66 ;
+    - _279_ sky130_fd_sc_hd__nand2_1 + PLACED ( 156860 212160 ) N ;
+    - _282_ sky130_fd_sc_hd__nand2_1 + PLACED ( 143520 212160 ) N ;
+    - _283_ sky130_fd_sc_hd__o22ai_1 + PLACED ( 154100 206720 ) N ;
+    - _284_ sky130_fd_sc_hd__nor2_8 + PLACED ( 156860 198560 ) FS ;
+    - _285_ sky130_fd_sc_hd__and2_1 + PLACED ( 170200 204000 ) FS ;
+    - _286_ sky130_fd_sc_hd__inv_8 + PLACED ( 109020 201280 ) N ;
+    - _288_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 164220 212160 ) N ;
+    - _289_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 140300 206720 ) N ;
+    - _290_ sky130_fd_sc_hd__a32o_1 + PLACED ( 164220 206720 ) N ;
+    - _291_ sky130_fd_sc_hd__nand2_2 + PLACED ( 117760 16320 ) N ;
+    - _292_ sky130_fd_sc_hd__o311a_2 + PLACED ( 127420 103360 ) N ;
+    - _293_ sky130_fd_sc_hd__or2_4 + PLACED ( 156860 190400 ) N ;
+    - _295_ sky130_fd_sc_hd__o31ai_4 + PLACED ( 116840 97920 ) N ;
+    - _297_ sky130_fd_sc_hd__nand2_8 + PLACED ( 162380 193120 ) FS ;
+    - _298_ sky130_fd_sc_hd__o21ba_4 + PLACED ( 112700 100640 ) FS ;
+    - _400_ sky130_fd_sc_hd__nor2_1 + PLACED ( 195960 95200 ) FS ;
+    - _401_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 199180 95200 ) FS ;
+    - _402_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 148120 125120 ) N ;
+    - _403_ sky130_fd_sc_hd__a22oi_1 + PLACED ( 143520 106080 ) FS ;
+    - _404_ sky130_fd_sc_hd__nor2_1 + PLACED ( 152720 114240 ) N ;
+    - _405_ sky130_fd_sc_hd__a21oi_1 + PLACED ( 150420 116960 ) FS ;
+    - _406_ sky130_fd_sc_hd__nand2_1 + PLACED ( 103500 103360 ) N ;
+    - _407_ sky130_fd_sc_hd__o21ai_0 + PLACED ( 96600 89760 ) FS ;
+    - _408_ sky130_fd_sc_hd__inv_1 + PLACED ( 96140 106080 ) FS ;
+    - _409_ sky130_fd_sc_hd__or4_1 + PLACED ( 97980 100640 ) FS ;
+    - _410_ sky130_fd_sc_hd__a32oi_1 + PLACED ( 98440 103360 ) N ;
+    - _411_ sky130_fd_sc_hd__dfxtp_4 + PLACED ( 137540 209440 ) FS ;
+    - _412_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 163760 209440 ) FS ;
+    - _413_ sky130_fd_sc_hd__dfxtp_4 + PLACED ( 150420 209440 ) FS ;
+    - _414_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 110860 133280 ) FS ;
+    - _415_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 96600 184960 ) N ;
+    - _416_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 143520 157760 ) N ;
+    - _417_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 140760 174080 ) N ;
+    - _418_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 110860 119680 ) N ;
+    - _419_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 207000 176800 ) FS ;
+    - _420_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 205620 193120 ) FS ;
+    - _421_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 111320 198560 ) FS ;
+    - _422_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 172960 174080 ) N ;
+    - _423_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 152720 146880 ) N ;
+    - _424_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 206080 127840 ) FS ;
+    - _425_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 164220 87040 ) N ;
+    - _426_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 157780 100640 ) FS ;
+    - _427_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 206080 111520 ) FS ;
+    - _428_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 146280 87040 ) N ;
+    - _429_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 92920 119680 ) N ;
+    - _430_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 99820 149600 ) FS ;
+    - _431_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 109020 182240 ) FS ;
+    - _432_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 136620 146880 ) N ;
+    - _433_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 125580 182240 ) FS ;
+    - _434_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 125120 119680 ) N ;
+    - _435_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 201020 163200 ) N ;
+    - _436_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 191820 190400 ) N ;
+    - _437_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 126040 198560 ) FS ;
+    - _438_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 154560 176800 ) FS ;
+    - _439_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 191820 152320 ) N ;
+    - _440_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 199180 136000 ) N ;
+    - _441_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 178480 89760 ) FS ;
+    - _442_ sky130_fd_sc_hd__dfxtp_2 + PLACED ( 155940 127840 ) FS ;
+    - _443_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 205620 95200 ) FS ;
+    - _444_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 143520 114240 ) N ;
+    - _445_ sky130_fd_sc_hd__dfxtp_1 + PLACED ( 89240 103360 ) N ;
+    - clkbuf_0_clk sky130_fd_sc_hd__clkbuf_4 + SOURCE TIMING + PLACED ( 150420 149600 ) FS ;
+    - clkbuf_2_0__f_clk sky130_fd_sc_hd__clkbuf_4 + SOURCE TIMING + PLACED ( 115920 116960 ) FS ;
+    - clkbuf_2_1__f_clk sky130_fd_sc_hd__clkbuf_4 + SOURCE TIMING + PLACED ( 168820 116960 ) FS ;
+    - clkbuf_2_2__f_clk sky130_fd_sc_hd__clkbuf_4 + SOURCE TIMING + PLACED ( 130180 171360 ) FS ;
+    - clkbuf_2_3__f_clk sky130_fd_sc_hd__clkbuf_4 + SOURCE TIMING + PLACED ( 168820 168640 ) N ;
+END COMPONENTS
+PINS 1 ;
+    - clk + NET clk + DIRECTION INPUT + USE SIGNAL
+      + PORT
+        + LAYER met2 ( -70 -242 ) ( 70 243 )
+        + PLACED ( 89470 242 ) N ;
+END PINS
+NETS 8 ;
+    - clk ( PIN clk ) ( clkbuf_0_clk A ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S
+      + ROUTED met1 ( 89470 148410 210 ) ( 107870 * 210 )
+      NEW met1 ( 107870 148410 210 ) ( * 150790 210 )
+      NEW met1 ( 107870 150790 210 ) ( 110400 * 210 )
+      NEW met1 ( 110400 150790 210 ) ( * 151130 210 )
+      NEW met1 ( 110400 151130 210 ) ( 149500 * 210 )
+      NEW met1 TAPER ( 149500 151130 ) ( 151110 * )
+      NEW met2 ( 89470 340 0 ) ( * 82800 210 )
+      NEW met2 ( 89470 131100 210 ) ( * 148410 210 )
+      NEW met2 ( 88550 82800 210 ) ( 89470 * 210 )
+      NEW met2 ( 88550 82800 210 ) ( * 131100 210 )
+      NEW met2 ( 88550 131100 210 ) ( 89470 * 210 )
+      NEW met1 ( 89470 148410 ) M1M2_PR_R
+      NEW li1 TAPER ( 151110 151130 ) L1M1_PR_R ;
+    - clknet_0_clk ( clkbuf_2_3__f_clk A ) ( clkbuf_2_2__f_clk A ) ( clkbuf_2_1__f_clk A ) ( clkbuf_2_0__f_clk A ) ( clkbuf_0_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S
+      + ROUTED met1 TAPER ( 167900 169830 ) ( 169510 * )
+      NEW met1 TAPER ( 167900 118490 ) ( 169510 * )
+      NEW met2 ( 146970 169830 210 ) ( * 172890 210 )
+      NEW met1 ( 146970 169830 210 ) ( 167900 * 210 )
+      NEW met1 TAPER ( 151570 150450 ) ( 152490 * )
+      NEW met2 ( 151570 150450 210 ) ( * 169830 210 )
+      NEW met1 TAPER ( 130870 172890 ) ( 131100 * )
+      NEW met2 ( 131100 172890 210 ) ( * 173060 210 )
+      NEW met2 ( 131100 173060 210 ) ( 131330 * 210 )
+      NEW met3 ( 131330 173060 450 ) ( 134550 * 450 )
+      NEW met2 ( 134550 172890 210 ) ( * 173060 210 )
+      NEW met1 ( 134550 172890 210 ) ( 146970 * 210 )
+      NEW met1 ( 158700 118490 210 ) ( 167900 * 210 )
+      NEW met1 ( 158700 118150 210 ) ( * 118490 210 )
+      NEW met1 ( 119370 118150 210 ) ( 158700 * 210 )
+      NEW met2 ( 119370 117980 210 ) ( * 118150 210 )
+      NEW met2 ( 117530 117980 210 ) ( 119370 * 210 )
+      NEW met2 ( 117530 117980 210 ) ( * 118830 210 )
+      NEW met1 TAPER ( 116520 118830 ) ( 117530 * )
+      NEW met2 ( 151570 118150 210 ) ( * 150450 210 )
+      NEW li1 TAPER ( 169510 169830 ) L1M1_PR_R
+      NEW li1 TAPER ( 169510 118490 ) L1M1_PR_R
+      NEW met1 ( 146970 169830 ) M1M2_PR_R
+      NEW met1 ( 146970 172890 ) M1M2_PR_R
+      NEW li1 TAPER ( 130870 172890 ) L1M1_PR_R
+      NEW met1 ( 151570 169830 ) M1M2_PR_R
+      NEW li1 TAPER ( 152490 150450 ) L1M1_PR_R
+      NEW met1 TAPER ( 151570 150450 ) M1M2_PR_R
+      NEW met1 ( 131100 172890 ) M1M2_PR_R
+      NEW met2 ( 131330 173060 ) M2M3_PR
+      NEW met2 ( 134550 173060 ) M2M3_PR
+      NEW met1 ( 134550 172890 ) M1M2_PR_R
+      NEW met1 ( 119370 118150 ) M1M2_PR_R
+      NEW met1 TAPER ( 117530 118830 ) M1M2_PR_R
+      NEW li1 TAPER ( 116520 118830 ) L1M1_PR_R
+      NEW met1 ( 151570 118150 ) M1M2_PR_R
+      NEW met1 TAPER ( 131100 172890 ) RECT ( 0 -70 365 70 )  ;
+    - clknet_2_0__leaf_clk ( _414_ CLK ) ( _418_ CLK ) ( _428_ CLK ) ( _429_ CLK ) ( _432_ CLK ) ( _434_ CLK ) ( _444_ CLK )
+      ( _445_ CLK ) ( clkbuf_2_0__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S
+      + ROUTED met2 ( 93150 118490 210 ) ( * 120870 210 )
+      NEW met1 ( 90390 118490 210 ) ( 93150 * 210 )
+      NEW met2 ( 90390 104380 210 ) ( * 118490 210 )
+      NEW met2 ( 89470 104380 210 ) ( 90390 * 210 )
+      NEW met2 ( 89470 104380 210 ) ( * 104550 210 )
+      NEW met2 ( 125350 120870 210 ) ( * 123590 210 )
+      NEW met1 ( 125350 123590 210 ) ( 136850 * 210 )
+      NEW met2 ( 136850 123590 210 ) ( * 148070 210 )
+      NEW met2 ( 118450 118830 210 ) ( * 123590 210 )
+      NEW met1 ( 118450 123590 210 ) ( 125350 * 210 )
+      NEW met2 ( 111090 120870 210 ) ( * 123590 210 )
+      NEW met1 ( 111090 123590 210 ) ( 118450 * 210 )
+      NEW met2 ( 111090 123590 210 ) ( * 134810 210 )
+      NEW met2 ( 111090 120700 210 ) ( * 120870 210 )
+      NEW met2 ( 143750 115430 210 ) ( * 123590 210 )
+      NEW met1 ( 136850 123590 210 ) ( 143750 * 210 )
+      NEW met3 ( 93150 120700 450 ) ( 111090 * 450 )
+      NEW met3 ( 143750 89420 450 ) ( 146510 * 450 )
+      NEW met2 ( 146510 88230 210 ) ( * 89420 210 )
+      NEW met2 ( 143750 89420 210 ) ( * 115430 210 )
+      NEW li1 ( 93150 120870 ) L1M1_PR_R
+      NEW met1 ( 93150 120870 ) M1M2_PR_R
+      NEW met1 ( 93150 118490 ) M1M2_PR_R
+      NEW met1 ( 90390 118490 ) M1M2_PR_R
+      NEW li1 ( 89470 104550 ) L1M1_PR_R
+      NEW met1 ( 89470 104550 ) M1M2_PR_R
+      NEW met2 ( 93150 120700 ) M2M3_PR
+      NEW li1 ( 125350 120870 ) L1M1_PR_R
+      NEW met1 ( 125350 120870 ) M1M2_PR_R
+      NEW met1 ( 125350 123590 ) M1M2_PR_R
+      NEW met1 ( 136850 123590 ) M1M2_PR_R
+      NEW li1 ( 136850 148070 ) L1M1_PR_R
+      NEW met1 ( 136850 148070 ) M1M2_PR_R
+      NEW li1 ( 118450 118830 ) L1M1_PR_R
+      NEW met1 ( 118450 118830 ) M1M2_PR_R
+      NEW met1 ( 118450 123590 ) M1M2_PR_R
+      NEW li1 ( 111090 120870 ) L1M1_PR_R
+      NEW met1 ( 111090 120870 ) M1M2_PR_R
+      NEW met1 ( 111090 123590 ) M1M2_PR_R
+      NEW li1 ( 111090 134810 ) L1M1_PR_R
+      NEW met1 ( 111090 134810 ) M1M2_PR_R
+      NEW met2 ( 111090 120700 ) M2M3_PR
+      NEW li1 ( 143750 115430 ) L1M1_PR_R
+      NEW met1 ( 143750 115430 ) M1M2_PR_R
+      NEW met1 ( 143750 123590 ) M1M2_PR_R
+      NEW met2 ( 143750 89420 ) M2M3_PR
+      NEW met2 ( 146510 89420 ) M2M3_PR
+      NEW li1 ( 146510 88230 ) L1M1_PR_R
+      NEW met1 ( 146510 88230 ) M1M2_PR_R ;
+    - clknet_2_1__leaf_clk ( _423_ CLK ) ( _424_ CLK ) ( _425_ CLK ) ( _426_ CLK ) ( _427_ CLK ) ( _440_ CLK ) ( _441_ CLK )
+      ( _442_ CLK ) ( _443_ CLK ) ( clkbuf_2_1__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S
+      + ROUTED met1 ( 172270 118490 210 ) ( * 120870 210 )
+      NEW met1 ( 171350 118490 210 ) ( 172270 * 210 )
+      NEW met2 ( 158010 91290 210 ) ( * 102170 210 )
+      NEW met2 ( 156170 129370 210 ) ( * 131750 210 )
+      NEW met1 ( 152950 131750 210 ) ( 156170 * 210 )
+      NEW met2 ( 152950 131750 210 ) ( * 148070 210 )
+      NEW met2 ( 156170 120870 210 ) ( * 129370 210 )
+      NEW met2 ( 158010 102170 210 ) ( * 120870 210 )
+      NEW met1 ( 156170 120870 210 ) ( 172270 * 210 )
+      NEW met1 ( 158010 91290 210 ) ( 164450 * 210 )
+      NEW met2 ( 164450 88230 210 ) ( * 91290 210 )
+      NEW met2 ( 177330 91290 210 ) ( 178710 * 210 )
+      NEW met2 ( 205850 94010 210 ) ( * 96730 210 )
+      NEW met1 ( 178710 94010 210 ) ( 205850 * 210 )
+      NEW met2 ( 178710 91290 210 ) ( * 94010 210 )
+      NEW met2 ( 206310 113050 210 ) ( * 113220 210 )
+      NEW met3 ( 199870 113220 450 ) ( 206310 * 450 )
+      NEW met1 ( 164450 91290 210 ) ( 177330 * 210 )
+      NEW met2 ( 206310 129370 210 ) ( * 131750 210 )
+      NEW met1 ( 199410 131750 210 ) ( 206310 * 210 )
+      NEW met2 ( 199410 131750 210 ) ( * 137190 210 )
+      NEW met2 ( 199410 131750 210 ) ( 199870 * 210 )
+      NEW met2 ( 199870 94010 210 ) ( * 131750 210 )
+      NEW li1 ( 164450 88230 ) L1M1_PR_R
+      NEW met1 ( 164450 88230 ) M1M2_PR_R
+      NEW li1 ( 171350 118490 ) L1M1_PR_R
+      NEW li1 ( 158010 102170 ) L1M1_PR_R
+      NEW met1 ( 158010 102170 ) M1M2_PR_R
+      NEW met1 ( 158010 91290 ) M1M2_PR_R
+      NEW li1 ( 156170 129370 ) L1M1_PR_R
+      NEW met1 ( 156170 129370 ) M1M2_PR_R
+      NEW met1 ( 156170 131750 ) M1M2_PR_R
+      NEW met1 ( 152950 131750 ) M1M2_PR_R
+      NEW li1 ( 152950 148070 ) L1M1_PR_R
+      NEW met1 ( 152950 148070 ) M1M2_PR_R
+      NEW met1 ( 156170 120870 ) M1M2_PR_R
+      NEW met1 ( 158010 120870 ) M1M2_PR_R
+      NEW met1 ( 164450 91290 ) M1M2_PR_R
+      NEW li1 ( 178710 91290 ) L1M1_PR_R
+      NEW met1 ( 178710 91290 ) M1M2_PR_R
+      NEW met1 ( 177330 91290 ) M1M2_PR_R
+      NEW li1 ( 205850 96730 ) L1M1_PR_R
+      NEW met1 ( 205850 96730 ) M1M2_PR_R
+      NEW met1 ( 205850 94010 ) M1M2_PR_R
+      NEW met1 ( 178710 94010 ) M1M2_PR_R
+      NEW met1 ( 199870 94010 ) M1M2_PR_R
+      NEW li1 ( 206310 113050 ) L1M1_PR_R
+      NEW met1 ( 206310 113050 ) M1M2_PR_R
+      NEW met2 ( 206310 113220 ) M2M3_PR
+      NEW met2 ( 199870 113220 ) M2M3_PR
+      NEW li1 ( 206310 129370 ) L1M1_PR_R
+      NEW met1 ( 206310 129370 ) M1M2_PR_R
+      NEW met1 ( 206310 131750 ) M1M2_PR_R
+      NEW met1 ( 199410 131750 ) M1M2_PR_R
+      NEW li1 ( 199410 137190 ) L1M1_PR_R
+      NEW met1 ( 199410 137190 ) M1M2_PR_R ;
+    - clknet_2_2__leaf_clk ( _411_ CLK ) ( _413_ CLK ) ( _415_ CLK ) ( _416_ CLK ) ( _417_ CLK ) ( _421_ CLK ) ( _430_ CLK )
+      ( _431_ CLK ) ( _433_ CLK ) ( _437_ CLK ) ( clkbuf_2_2__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S
+      + ROUTED met1 TAPER ( 108330 183770 ) ( 109250 * )
+      NEW met1 TAPER ( 108330 183770 ) ( * 185470 )
+      NEW met1 ( 108330 185470 210 ) ( * 186150 210 )
+      NEW met2 ( 96830 183770 210 ) ( * 186150 210 )
+      NEW met1 ( 96830 183770 210 ) ( 107410 * 210 )
+      NEW met1 TAPER ( 107410 183770 ) ( 108330 * )
+      NEW met1 TAPER ( 136850 210630 ) ( 137770 * )
+      NEW met1 ( 136850 208250 210 ) ( * 209100 210 )
+      NEW met1 TAPER ( 136850 209100 ) ( * 210630 )
+      NEW met1 ( 136850 208250 210 ) ( 146970 * 210 )
+      NEW met1 ( 146970 208250 210 ) ( * 209950 210 )
+      NEW met1 ( 146970 209950 210 ) ( 148810 * 210 )
+      NEW met1 TAPER ( 148810 209950 ) ( 150650 * )
+      NEW met1 TAPER ( 150650 209950 ) ( * 210630 )
+      NEW met1 ( 126270 208250 210 ) ( 136850 * 210 )
+      NEW met1 TAPER ( 98210 151130 ) ( 100050 * )
+      NEW met2 ( 98210 151130 210 ) ( * 183770 210 )
+      NEW met1 TAPER ( 139380 175270 ) ( 140990 * )
+      NEW met1 TAPER ( 142140 159290 ) ( 143750 * )
+      NEW met2 ( 125810 181050 210 ) ( * 183770 210 )
+      NEW met1 ( 125810 181050 210 ) ( 131790 * 210 )
+      NEW met2 ( 125810 206380 210 ) ( 126270 * 210 )
+      NEW met2 ( 125810 183770 210 ) ( * 206380 210 )
+      NEW met2 ( 111550 197370 210 ) ( * 200090 210 )
+      NEW met1 ( 111550 197370 210 ) ( 125810 * 210 )
+      NEW met1 TAPER ( 125810 199750 ) ( 126270 * )
+      NEW met1 ( 108330 186150 210 ) ( 125810 * 210 )
+      NEW met2 ( 126270 206380 210 ) ( * 208250 210 )
+      NEW met2 ( 137770 159290 210 ) ( * 175270 210 )
+      NEW met1 ( 131790 175270 210 ) ( 137770 * 210 )
+      NEW met1 TAPER ( 132710 173230 ) ( 133630 * )
+      NEW met1 TAPER ( 133630 173230 ) ( * 175270 )
+      NEW met2 ( 131790 175270 210 ) ( * 181050 210 )
+      NEW met1 ( 137770 159290 210 ) ( 142140 * 210 )
+      NEW met1 ( 137770 175270 210 ) ( 139380 * 210 )
+      NEW met1 ( 126270 208250 ) M1M2_PR_R
+      NEW li1 TAPER ( 109250 183770 ) L1M1_PR_R
+      NEW li1 TAPER ( 96830 186150 ) L1M1_PR_R
+      NEW met1 TAPER ( 96830 186150 ) M1M2_PR_R
+      NEW met1 ( 96830 183770 ) M1M2_PR_R
+      NEW met1 ( 98210 183770 ) M1M2_PR_R
+      NEW li1 TAPER ( 137770 210630 ) L1M1_PR_R
+      NEW li1 TAPER ( 150650 210630 ) L1M1_PR_R
+      NEW met1 ( 98210 151130 ) M1M2_PR_R
+      NEW li1 TAPER ( 100050 151130 ) L1M1_PR_R
+      NEW li1 TAPER ( 140990 175270 ) L1M1_PR_R
+      NEW li1 TAPER ( 143750 159290 ) L1M1_PR_R
+      NEW li1 TAPER ( 125810 183770 ) L1M1_PR_R
+      NEW met1 TAPER ( 125810 183770 ) M1M2_PR_R
+      NEW met1 ( 125810 181050 ) M1M2_PR_R
+      NEW met1 ( 131790 181050 ) M1M2_PR_R
+      NEW li1 TAPER ( 111550 200090 ) L1M1_PR_R
+      NEW met1 TAPER ( 111550 200090 ) M1M2_PR_R
+      NEW met1 ( 111550 197370 ) M1M2_PR_R
+      NEW met1 ( 125810 197370 ) M1M2_PR_R
+      NEW li1 TAPER ( 126270 199750 ) L1M1_PR_R
+      NEW met1 TAPER ( 125810 199750 ) M1M2_PR_R
+      NEW met1 ( 125810 186150 ) M1M2_PR_R
+      NEW met1 ( 137770 175270 ) M1M2_PR_R
+      NEW met1 ( 137770 159290 ) M1M2_PR_R
+      NEW met1 ( 131790 175270 ) M1M2_PR_R
+      NEW li1 TAPER ( 132710 173230 ) L1M1_PR_R ;
+    - clknet_2_3__leaf_clk ( _412_ CLK ) ( _419_ CLK ) ( _420_ CLK ) ( _422_ CLK ) ( _435_ CLK ) ( _436_ CLK ) ( _438_ CLK )
+      ( _439_ CLK ) ( clkbuf_2_3__f_clk X ) + USE CLOCK + NONDEFAULTRULE NDR_3W_3S
+      + ROUTED met2 ( 192050 191590 210 ) ( * 194310 210 )
+      NEW met1 ( 192050 194310 210 ) ( 204010 * 210 )
+      NEW met1 TAPER ( 204010 194310 ) ( 205850 * )
+      NEW met1 ( 192050 177990 210 ) ( 205620 * 210 )
+      NEW met1 TAPER ( 205620 177990 ) ( 207230 * )
+      NEW met1 ( 192050 164730 210 ) ( 199535 * 210 )
+      NEW met1 TAPER ( 199535 164730 ) ( 201250 * )
+      NEW met2 ( 192050 164730 210 ) ( * 177990 210 )
+      NEW met2 ( 192050 177990 210 ) ( * 191590 210 )
+      NEW met1 ( 165830 175610 210 ) ( 171580 * 210 )
+      NEW met1 TAPER ( 171580 175610 ) ( 173190 * )
+      NEW met2 ( 170430 170510 210 ) ( * 175610 210 )
+      NEW met2 ( 170430 175610 210 ) ( * 177990 210 )
+      NEW met1 ( 170430 177990 210 ) ( 192050 * 210 )
+      NEW met2 ( 192050 153850 210 ) ( * 164730 210 )
+      NEW met1 ( 153870 175610 210 ) ( * 176460 210 )
+      NEW met1 TAPER ( 153870 176460 ) ( * 177990 )
+      NEW met1 TAPER ( 153870 177990 ) ( 154790 * )
+      NEW met1 ( 153870 175610 210 ) ( 165830 * 210 )
+      NEW met2 ( 165830 175610 210 ) ( * 207000 210 )
+      NEW met2 ( 163990 207000 210 ) ( 165830 * 210 )
+      NEW met2 ( 163990 207000 210 ) ( * 210630 210 )
+      NEW li1 TAPER ( 192050 191590 ) L1M1_PR_R
+      NEW met1 TAPER ( 192050 191590 ) M1M2_PR_R
+      NEW met1 ( 192050 194310 ) M1M2_PR_R
+      NEW li1 TAPER ( 205850 194310 ) L1M1_PR_R
+      NEW met1 ( 192050 177990 ) M1M2_PR_R
+      NEW li1 TAPER ( 207230 177990 ) L1M1_PR_R
+      NEW li1 TAPER ( 201250 164730 ) L1M1_PR_R
+      NEW met1 ( 192050 164730 ) M1M2_PR_R
+      NEW met1 ( 165830 175610 ) M1M2_PR_R
+      NEW li1 TAPER ( 173190 175610 ) L1M1_PR_R
+      NEW li1 TAPER ( 170430 170510 ) L1M1_PR_R
+      NEW met1 TAPER ( 170430 170510 ) M1M2_PR_R
+      NEW met1 ( 170430 175610 ) M1M2_PR_R
+      NEW met1 ( 170430 177990 ) M1M2_PR_R
+      NEW li1 TAPER ( 192050 153850 ) L1M1_PR_R
+      NEW met1 TAPER ( 192050 153850 ) M1M2_PR_R
+      NEW li1 TAPER ( 154790 177990 ) L1M1_PR_R
+      NEW li1 TAPER ( 163990 210630 ) L1M1_PR_R
+      NEW met1 TAPER ( 163990 210630 ) M1M2_PR_R ;
+    - ctrl.state.out\[1\] ( _412_ Q ) ( _290_ B2 ) ( _285_ A ) + USE SIGNAL
+      + ROUTED met1 ( 167670 208250 ) ( 170890 * )
+      NEW met2 ( 170890 208250 ) ( * 209950 )
+      NEW met2 ( 170890 205530 ) ( * 208250 )
+      NEW li1 ( 170890 205530 ) L1M1_PR_MR
+      NEW met1 ( 170890 205530 ) M1M2_PR
+      NEW li1 ( 167670 208250 ) L1M1_PR_MR
+      NEW met1 ( 170890 208250 ) M1M2_PR
+      NEW li1 ( 170890 209950 ) L1M1_PR_MR
+      NEW met1 ( 170890 209950 ) M1M2_PR ;
+    - ctrl.state.out\[2\] ( _413_ Q ) ( _297_ A ) ( _293_ A ) ( _290_ A1 ) ( _284_ A ) ( _279_ A ) + USE SIGNAL
+      + ROUTED met1 ( 158010 209950 ) ( 158470 * )
+      NEW met2 ( 158010 207570 ) ( * 209950 )
+      NEW met2 ( 158010 209950 ) ( * 213350 )
+      NEW met1 ( 158010 207570 ) ( 166290 * )
+      NEW met2 ( 158010 194650 ) ( * 200090 )
+      NEW met2 ( 158010 191590 ) ( * 194650 )
+      NEW met2 ( 158010 200090 ) ( * 207570 )
+      NEW met1 ( 158010 194650 ) ( 167210 * )
+      NEW li1 ( 167210 194650 ) L1M1_PR_MR
+      NEW met1 ( 158010 207570 ) M1M2_PR
+      NEW li1 ( 158470 209950 ) L1M1_PR_MR
+      NEW met1 ( 158010 209950 ) M1M2_PR
+      NEW li1 ( 158010 213350 ) L1M1_PR_MR
+      NEW met1 ( 158010 213350 ) M1M2_PR
+      NEW li1 ( 166290 207570 ) L1M1_PR_MR
+      NEW li1 ( 158010 200090 ) L1M1_PR_MR
+      NEW met1 ( 158010 200090 ) M1M2_PR
+      NEW met1 ( 158010 194650 ) M1M2_PR
+      NEW li1 ( 158010 191590 ) L1M1_PR_MR
+      NEW met1 ( 158010 191590 ) M1M2_PR ;
+END NETS
+END DESIGN
diff --git a/src/drt/test/ndr_no_auto_taper.ok b/src/drt/test/ndr_no_auto_taper.ok
new file mode 100644
index 00000000000..6aa5ccc9e01
--- /dev/null
+++ b/src/drt/test/ndr_no_auto_taper.ok
@@ -0,0 +1,56 @@
+[INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias
+[INFO ODB-0227] LEF file: sky130hd/sky130hd_std_cell.lef, created 437 library cells
+[INFO ODB-0128] Design: gcd
+[INFO ODB-0130]     Created 1 pins.
+[INFO ODB-0131]     Created 66 components and 347 component-terminals.
+[INFO ODB-0133]     Created 8 nets and 54 connections.
+[WARNING GRT-0008] The read_guides command does not allow parasitics estimation from the guides file.
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
+[WARNING DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
+[INFO DRT-0167] List of default vias:
+  Layer via
+    default via: M1M2_PR
+  Layer via2
+    default via: M2M3_PR
+  Layer via3
+    default via: M3M4_PR
+  Layer via4
+    default via: M4M5_PR
+[INFO DRT-0168] Init region query.
+[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
+[INFO DRT-0033] FR_VIA shape region query size = 0.
+[INFO DRT-0033] li1 shape region query size = 2928.
+[INFO DRT-0033] mcon shape region query size = 210.
+[INFO DRT-0033] met1 shape region query size = 412.
+[INFO DRT-0033] via shape region query size = 0.
+[INFO DRT-0033] met2 shape region query size = 1.
+[INFO DRT-0033] via2 shape region query size = 0.
+[INFO DRT-0033] met3 shape region query size = 0.
+[INFO DRT-0033] via3 shape region query size = 0.
+[INFO DRT-0033] met4 shape region query size = 0.
+[INFO DRT-0033] via4 shape region query size = 0.
+[INFO DRT-0033] met5 shape region query size = 0.
+[INFO DRT-0178] Init guide query.
+[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
+[INFO DRT-0036] FR_VIA guide region query size = 0.
+[INFO DRT-0036] li1 guide region query size = 51.
+[INFO DRT-0036] mcon guide region query size = 0.
+[INFO DRT-0036] met1 guide region query size = 56.
+[INFO DRT-0036] via guide region query size = 0.
+[INFO DRT-0036] met2 guide region query size = 32.
+[INFO DRT-0036] via2 guide region query size = 0.
+[INFO DRT-0036] met3 guide region query size = 0.
+[INFO DRT-0036] via3 guide region query size = 0.
+[INFO DRT-0036] met4 guide region query size = 0.
+[INFO DRT-0036] via4 guide region query size = 0.
+[INFO DRT-0036] met5 guide region query size = 0.
+[INFO DRT-0179] Init gr pin query.
+No differences found.
diff --git a/src/drt/test/ndr_no_auto_taper.tcl b/src/drt/test/ndr_no_auto_taper.tcl
new file mode 100644
index 00000000000..49deb950783
--- /dev/null
+++ b/src/drt/test/ndr_no_auto_taper.tcl
@@ -0,0 +1,38 @@
+# Per-net disable of DRT auto-taper (issue #9995).
+#
+# Clock nets are given a wide NDR.  By default DRT auto-tapers NDR nets
+# down to minimum width near pin connections.  Here we disable auto-taper
+# on a subset of the NDR nets via set_routing_disable_auto_taper so those
+# nets keep their full NDR width all the way to the pin, while the other
+# NDR nets continue to taper as before.  The DEF golden captures the
+# resulting routing.
+source "helpers.tcl"
+read_lef "sky130hd/sky130hd.tlef"
+read_lef "sky130hd/sky130hd_std_cell.lef"
+read_def "gcd_sky130hd.def"
+read_guides "gcd_sky130hd.guide"
+
+set def_file [make_result_file ndr_no_auto_taper.def]
+
+create_ndr -name NDR_3W_3S \
+  -spacing { li1 0.51 met1 0.42 met2 0.42 met3 0.9 met4 0.9 met5 4.8 } \
+  -width { li1 0.51 met1 0.42 met2 0.42 met3 0.9 met4 0.9 met5 4.8 } \
+  -via { L1M1_PR_R M1M2_PR_R }
+
+assign_ndr -ndr NDR_3W_3S -net clk
+assign_ndr -ndr NDR_3W_3S -net clknet_0_clk
+assign_ndr -ndr NDR_3W_3S -net clknet_2_0__leaf_clk
+assign_ndr -ndr NDR_3W_3S -net clknet_2_1__leaf_clk
+assign_ndr -ndr NDR_3W_3S -net clknet_2_2__leaf_clk
+assign_ndr -ndr NDR_3W_3S -net clknet_2_3__leaf_clk
+
+# Keep full NDR width to the pins on these nets (no auto-taper); the
+# remaining NDR nets still taper by default.
+set_routing_disable_auto_taper -net clknet_2_0__leaf_clk
+set_routing_disable_auto_taper -net clknet_2_1__leaf_clk
+
+set_routing_layers -signal met1-met5
+detailed_route -verbose 0
+
+write_def $def_file
+diff_files ndr_no_auto_taper.defok $def_file
diff --git a/src/odb/include/odb/db.h b/src/odb/include/odb/db.h
index 5b85cacd791..0a81cb7d0d9 100644
--- a/src/odb/include/odb/db.h
+++ b/src/odb/include/odb/db.h
@@ -2535,6 +2535,17 @@ class dbNet : public dbObject
 
   void setJumpers(bool has_jumpers);
 
+  ///
+  /// When set, the detailed router will not auto-taper this net down to
+  /// minimum width near pin connections.  This is useful for wide/NDR
+  /// (e.g. analog) nets that must keep their full width all the way to
+  /// the pin.  Default is false (auto-taper enabled), matching the
+  /// historical global behavior.
+  ///
+  bool disableAutoTaper();
+
+  void setDisableAutoTaper(bool disable_auto_taper);
+
   ///
   /// Return true if the input net is in higher hierarchy than this net
   /// e.g., If this net name = "a/b/c" and input `net` name = "a/d",
diff --git a/src/odb/src/db/dbDatabase.h b/src/odb/src/db/dbDatabase.h
index 0509274a3a0..d9973bec936 100644
--- a/src/odb/src/db/dbDatabase.h
+++ b/src/odb/src/db/dbDatabase.h
@@ -50,8 +50,10 @@ namespace odb {
 inline constexpr uint32_t kSchemaMajor = 0;  // Not used...
 inline constexpr uint32_t kSchemaInitial = 57;
 
-inline constexpr uint32_t kSchemaMinor = 132;  // Current revision number
+inline constexpr uint32_t kSchemaMinor = 133;  // Current revision number
 
+// Revision where dbNet::disable_auto_taper flag was added
+inline constexpr uint32_t kSchemaNetDisableAutoTaper = 133;
 // Revision where dbInst::bump_ was added
 inline constexpr uint32_t kSchemaInstBump = 132;
 // Revision where all areas in the are switched to be stored as int64_t
diff --git a/src/odb/src/db/dbNet.cpp b/src/odb/src/db/dbNet.cpp
index d0dc8205f57..98e11bec3c0 100644
--- a/src/odb/src/db/dbNet.cpp
+++ b/src/odb/src/db/dbNet.cpp
@@ -100,7 +100,7 @@ _dbNet::_dbNet(_dbDatabase* db)
   flags_.special = 0;
   flags_.wild_connect = 0;
   flags_.wire_ordered = 0;
-  flags_.unused2 = 0;
+  flags_.disable_auto_taper = 0;
   flags_.disconnected = 0;
   flags_.spef = 0;
   flags_.select = 0;
@@ -218,6 +218,10 @@ bool _dbNet::operator==(const _dbNet& rhs) const
     return false;
   }
 
+  if (flags_.disable_auto_taper != rhs.flags_.disable_auto_taper) {
+    return false;
+  }
+
   if (flags_.disconnected != rhs.flags_.disconnected) {
     return false;
   }
@@ -2440,6 +2444,26 @@ void dbNet::setJumpers(bool has_jumpers)
   }
 }
 
+bool dbNet::disableAutoTaper()
+{
+  bool disable_auto_taper = false;
+  _dbNet* net = (_dbNet*) this;
+  _dbDatabase* db = net->getImpl()->getDatabase();
+  if (db->isSchema(kSchemaNetDisableAutoTaper)) {
+    disable_auto_taper = net->flags_.disable_auto_taper == 1;
+  }
+  return disable_auto_taper;
+}
+
+void dbNet::setDisableAutoTaper(bool disable_auto_taper)
+{
+  _dbNet* net = (_dbNet*) this;
+  _dbDatabase* db = net->getImpl()->getDatabase();
+  if (db->isSchema(kSchemaNetDisableAutoTaper)) {
+    net->flags_.disable_auto_taper = disable_auto_taper ? 1 : 0;
+  }
+}
+
 void dbNet::checkSanity() const
 {
   // Check net itself
diff --git a/src/odb/src/db/dbNet.h b/src/odb/src/db/dbNet.h
index 69ff5bbc11a..14f738837f5 100644
--- a/src/odb/src/db/dbNet.h
+++ b/src/odb/src/db/dbNet.h
@@ -38,7 +38,7 @@ struct _dbNetFlags
   uint32_t special : 1;
   uint32_t wild_connect : 1;
   uint32_t wire_ordered : 1;
-  uint32_t unused2 : 1;       // free to reuse
+  uint32_t disable_auto_taper : 1;  // was unused2; free bit reused
   uint32_t disconnected : 1;  // this flag is only valid if wire_ordered == true
   uint32_t spef : 1;
   uint32_t select : 1;