gate level module power estimate

[y20n20]

Dear Mat, experienced OR users
How do i use OR for gate level module power estimate ?
that is both dynamic and leakage per sub module in the design.
obviously i would like to stimulate the module with specific stimulus.
do i need to create the GDS by preserving hierarchical structure with SYNTH_HIERARCHY ?
thanks
Y

[maliberty]

You need to simulate with another tool and provide the toggle counts in VCD or SAIF format, both of which OpenSTA can read (read_saif or read_vcd). report_power will then give you power estimates. If you don't provide those files sta will attempt to estimate activity though the result will be less accurate.

[y20n20]

Matt, thank you for the prompt response.
several questions raised:

1. do the design needs beforehand be hierarchical ?
2. this VCD/SAIF can help estimate dynamic power, how is is done for leakage power ?
3. usually for leakage power, the estimate is over cell of your designated module - meaning hierarchical..
   It would be really helpful if you can clear this.
   Best,
   Y

[maliberty]

1. Not required
2. Leakage is usually not dependent on activity if you only care about that
3. By default the estimate is for the whole design. If the design is hierarchical I suppose you could report for one instance of a module though I've never tried it.

[y20n20]

Hello Matt,
True, leakage is independent from the dynamic activity. But leakage do depends on the collections of cells belonging to certain module. therefore hierarchical is essential for this kind of estimate.
In addition, it is essential for coloring region in the design that constitute sub modules.
So my question:

1. would you know if hierarchical flag exists in OR? is it supported? (i think it was in the past)
2. would the power estimate (dynamic/leakage) will be give per hard macros, in case of using a hard macro around a Module ??
   Thanks,
   Y

[maliberty]

How does leakage depend on modules? Transistors don't know anything about modules.

OR does support hierarchy. See OPENROAD_HIERARCHICAL in ORFS.
Hard macros are nothing special, their leakage is whatever the Liberty says.

[y20n20]

if transistor T(j) serves functionality of Module1, then leakage(T(j)) is counted in the leakage-budget of Module1.. no ?
if transistor T(j) serves functionality of Module1 and Module2, then leakage(T(j)) is counted in the leakage-budget of both Module1 and Module2 with some proportions.. no ?

in that sense in dose depends to Module/Hierarchy..

[maliberty]

You seem to have some methodology assumptions that are unclear. There is no notion of leakage-budget in OR.