drivers: mtd: s25h: automatically enter 4 byte address mode

To be able to address the full flash memory it's required to enter the 4
byte address mode. This is now done automatically during startup

Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>

Author: m-braunschweig

drivers/flash/flash_mspi_infineon_s25h.c

@@ -597,7 +597,8 @@ static int flash_mspi_infineon_s25h_switch_to_quad_transfer(const struct device
 
 	ret = flash_mspi_infineon_s25h_verify_jedec_id(dev);
 	if (ret < 0) {
-		LOG_ERR("JEDEC ID mismatch after switching to 4 lane MSPI. Communication is broken");
+		LOG_ERR("JEDEC ID mismatch after switching to 4 lane MSPI. Communication is "
+			"broken");
 		return ret;
 	}
 
@@ -629,7 +630,8 @@ static int flash_mspi_infineon_s25h_switch_to_quad_transfer(const struct device
 
 	ret = flash_mspi_infineon_s25h_verify_jedec_id(dev);
 	if (ret < 0) {
-		LOG_ERR("JEDEC ID mismatch after switching to full quad MSPI mode. Communication is broken");
+		LOG_ERR("JEDEC ID mismatch after switching to full quad MSPI mode. Communication "
+			"is broken");
 		return ret;
 	}
 
@@ -700,6 +702,49 @@ static int flash_mspi_infineon_s25h_disable_hybrid_sector_mode(const struct devi
 	return 0;
 }
 
+static int flash_mspi_infineon_s25h_enter_4_byte_address_mode(const struct device *dev)
+{
+	int ret = 0;
+	const struct flash_mspi_infineon_s25h_cfg *config = dev->config;
+	struct flash_mspi_infineon_s25h_data *data = dev->data;
+
+	const struct mspi_xfer_packet enter_4_byte_cmd = {
+		.dir = MSPI_TX,
+		.cmd = INF_MSPI_S25H_OPCODE_ENABLE_4_BYTE_ADDR_MODE,
+		.num_bytes = 0,
+	};
+
+	struct mspi_xfer xfer = {
+		INF_MSPI_S25H_DEFAULT_XFER_DATA,
+		.rx_dummy = 0,
+		.addr_length = 0,
+		.num_packet = 1,
+		.packets = &enter_4_byte_cmd,
+		.timeout = INF_MSPI_S25H_DEFAULT_MSPI_TIMEOUT,
+	};
+
+	ret = mspi_transceive(config->bus, &config->dev_id, &xfer);
+	if (ret < 0) {
+		LOG_ERR("Error sending command to enter 4 byte address mode");
+		return ret;
+	}
+
+	data->mspi_dev_cfg.addr_length = 4;
+
+	if (ret < 0) {
+		LOG_ERR("Error setting up MSPI bus after changing address length");
+		return ret;
+	}
+
+	ret = flash_mspi_infineon_s25h_verify_jedec_id(dev);
+	if (ret < 0) {
+		LOG_ERR("Error verifying JEDEC id after entering 4 byte address mode");
+		return ret;
+	}
+
+	return 0;
+}
+
 static int flash_mspi_infineon_s25h_init(const struct device *dev)
 {
 	int ret = 0;
@@ -735,6 +780,11 @@ static int flash_mspi_infineon_s25h_init(const struct device *dev)
 		return ret;
 	}
 
+	ret = flash_mspi_infineon_s25h_enter_4_byte_address_mode(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
 	ret = flash_mspi_infineon_s25h_switch_to_quad_transfer(dev);
 	if (ret < 0) {
 		return ret;

drivers/flash/flash_mspi_infineon_s25h.h

@@ -14,8 +14,9 @@
 #define INF_MSPI_S25H_DEFAULT_MSPI_TIMEOUT 100
 
 /* opcodes 1-1-1 mode */
-#define INF_MSPI_S25H_OPCODE_WRITE_ENABLE  0x06
-#define INF_MSPI_S25H_OPCODE_WRITE_DISABLE 0x04
+#define INF_MSPI_S25H_OPCODE_WRITE_ENABLE            0x06
+#define INF_MSPI_S25H_OPCODE_WRITE_DISABLE           0x04
+#define INF_MSPI_S25H_OPCODE_ENABLE_4_BYTE_ADDR_MODE 0xB7
 
 #define INF_MSPI_S25H_OPCODE_READ_ANY_REGISTER  0x65
 #define INF_MSPI_S25H_OPCODE_WRITE_ANY_REGISTER 0x71