Mid-Side-Transform-Module-FPGA/.gitignore at main · Nandhagopal200/Mid-Side-Transform-Module-FPGA · GitHub

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# ============================================================================
# FPGA / Vivado
# ============================================================================

# Vivado projects & runs
*.xpr
*.jou
*.log
*.str
*.cache/
*.runs/
*.hw/
*.sim/
*.ip_user_files/
*.gen/
*.srcs/

# Block Design outputs
*.bd
*.hwh
*.xsa
*.bit

# Reports
*.rpt
*.dcp
*.pb
*.xml

# ============================================================================
# Simulation
# ============================================================================

# XSIM / ModelSim / Questa
xsim.dir/
*.wdb
*.vcd
*.fst
*.lxt
*.log

# ============================================================================
# OS / Editor
# ============================================================================

.DS_Store
Thumbs.db
*.swp
*.swo
*.bak

# ============================================================================
# Python / Plotting (results only, scripts allowed)
# ============================================================================

__pycache__/
*.pyc
*.pyo
.venv/

# ============================================================================
# Temporary / Local
# ============================================================================

tmp/
temp/
local/