fixes PMP and memory access handling

Author: eyck

src/iss/arch/riscv_hart_msu_vp.h

@@ -267,13 +267,14 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const addr_t& a, const unsigned
                     return iss::Err;
                 }
                 auto res = this->memory.rd_mem({address_type::VIRTUAL, a.access, a.space, a.val}, length, data);
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
+                if(unlikely(res != iss::Ok &&  !is_debug(a.access))) {
+                    auto trap_id = is_fetch(a.access)?traits<BASE>::RV_CAUSE_FETCH_ACCESS:traits<BASE>::RV_CAUSE_LOAD_ACCESS;
+                    this->reg.trap_state = (1UL << 31) | trap_id << 16;
                     this->fault_data = addr;
                 }
                 return res;
             } catch(trap_access& ta) {
-                if((access & access_type::DEBUG) == 0) {
+                if(!is_debug(access)) {
                     this->reg.trap_state = (1UL << 31) | ta.id;
                     this->fault_data = ta.addr;
                 }
@@ -283,7 +284,7 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::read(const addr_t& a, const unsigned
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        if((access & access_type::DEBUG) == 0) {
+        if(!is_debug(access)) {
             this->reg.trap_state = (1UL << 31) | ta.id;
             this->fault_data = ta.addr;
         }
@@ -386,7 +387,7 @@ iss::status riscv_hart_msu_vp<BASE, FEAT>::write(const addr_t& a, const unsigned
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        if((access & access_type::DEBUG) == 0) {
+        if(!is_debug(access)) {
             this->reg.trap_state = (1UL << 31) | ta.id;
             this->fault_data = ta.addr;
         }

src/iss/arch/riscv_hart_mu_p.h

@@ -229,13 +229,14 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const addr_t& a, const unsigned le
                     return iss::Err;
                 }
                 auto res = this->memory.rd_mem({address_type::PHYSICAL, a.access, a.space, a.val}, length, data);
-                if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
-                    this->reg.trap_state = (1UL << 31) | traits<BASE>::RV_CAUSE_LOAD_ACCESS << 16;
+                if(unlikely(res != iss::Ok && !is_debug(access))) {
+                    auto trap_id = is_fetch(a.access)?traits<BASE>::RV_CAUSE_FETCH_ACCESS:traits<BASE>::RV_CAUSE_LOAD_ACCESS;
+                    this->reg.trap_state = (1UL << 31) | trap_id << 16;
                     this->fault_data = addr;
                 }
                 return res;
             } catch(trap_access& ta) {
-                if((access & access_type::DEBUG) == 0) {
+                if(!is_debug(access)) {
                     this->reg.trap_state = (1UL << 31) | ta.id;
                     this->fault_data = ta.addr;
                 }
@@ -245,7 +246,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const addr_t& a, const unsigned le
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        if((access & access_type::DEBUG) == 0) {
+        if(!is_debug(access)) {
             this->reg.trap_state = (1UL << 31) | ta.id;
             this->fault_data = ta.addr;
         }
@@ -334,7 +335,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const addr_t& a, const unsigned l
         }
         return iss::Ok;
     } catch(trap_access& ta) {
-        if((access & access_type::DEBUG) == 0) {
+        if(!is_debug(access)) {
             this->reg.trap_state = (1UL << 31) | ta.id;
             this->fault_data = ta.addr;
         }

src/iss/mem/pmp.h

@@ -94,7 +94,7 @@ template <typename PLAT, size_t NUM_ENTRIES = 16> struct pmp : public memory_ele
            !pmp_check(addr.access, addr.val, length) && !is_debug(addr.access)) {
             if(is_debug(addr.access))
                 throw trap_access(0, addr.val);
-            hart_if.raise_trap(/*trap_id*/ 0, /*cause*/ (addr.access == access_type::FETCH) ? 1 : 5, /*fault_data*/ addr.val);
+            // trap is raised in privilege wrapper
             return iss::Err;
         }
         return down_stream_mem.rd_mem(addr, length, data);
@@ -105,7 +105,7 @@ template <typename PLAT, size_t NUM_ENTRIES = 16> struct pmp : public memory_ele
         if(likely(addr.space == arch::traits<PLAT>::MEM) && !pmp_check(addr.access, addr.val, length) && !is_debug(addr.access)) {
             if(is_debug(addr.access))
                 throw trap_access(0, addr.val);
-            hart_if.raise_trap(/*trap_id*/ 0, /*cause*/ 7, /*fault_data*/ addr.val);
+            // trap is raised in privilege wrapper, so we just return error
             return iss::Err;
         }
         return down_stream_mem.wr_mem(addr, length, data);