diff --git a/MCL86/Core/MCL86_Microcode_Xilinx_Version_5.coe b/MCL86/Core/MCL86_Microcode_Xilinx_Version_5.coe
new file mode 100644
index 0000000..d5e3183
--- /dev/null
+++ b/MCL86/Core/MCL86_Microcode_Xilinx_Version_5.coe
@@ -0,0 +1,2 @@
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diff --git a/MCL86/Core/MCL86_Microcode_Xilinx_Version_6.coe b/MCL86/Core/MCL86_Microcode_Xilinx_Version_6.coe
new file mode 100644
index 0000000..8b755ff
--- /dev/null
+++ b/MCL86/Core/MCL86_Microcode_Xilinx_Version_6.coe
@@ -0,0 +1,2 @@
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diff --git a/MCL86/Core/MCL86_Microcode_Xilinx_Version_7.coe b/MCL86/Core/MCL86_Microcode_Xilinx_Version_7.coe
new file mode 100644
index 0000000..9b4bc02
--- /dev/null
+++ b/MCL86/Core/MCL86_Microcode_Xilinx_Version_7.coe
@@ -0,0 +1,2 @@
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diff --git a/MCL86/Core/MCL86_Microcode_Xilinx_Version_8.coe b/MCL86/Core/MCL86_Microcode_Xilinx_Version_8.coe
new file mode 100644
index 0000000..54965a9
--- /dev/null
+++ b/MCL86/Core/MCL86_Microcode_Xilinx_Version_8.coe
@@ -0,0 +1,2 @@
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588f0040 10000041 00000000 00000000 00000000 00000000 00000000 2ccc0000 2bbb0000 4eef0001 10020f35 5ccf0001 5e3f0000 233d0000 4eef0001 10020f3a 5bbf0001 5e0f0000 200d0000 4eef0001 10020f3f 533f0001 10300000 00000000 00000000 00000000 00000000 00000000 00000000 488ff7fe 5aff0000 4b9f8000 4e9f0001 10020f4d 588f0001 5aff8000 79990000 599a0000 6eab0200 10020f52 588f0800 10300000 00000000 00000000 00000000 2bbb0000 5e0f0000 200d0000 4eef0001 10020f5c 5bbf0001 10300000 00000000 00000000 00000000 700f0000 4e3f0001 10020f64 500f8000 733f0000 4ebf0001 10020f68 533f8000 7bbf0000 10300000 700f0000 4ebf0001 10020f6e 500f8000 7bbf0000 10300000 4e0fff00 10020f73 588f0801 4ecf0001 10020f77 600fffff 200f0001 4eef1000 10020f77 100000c6 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 5fffc02b 110003f2 5ddf1004 4ddf0000 4eef0080 10020fcb 488f0fd5 4ddf0000 10000006 4ddf0000 10000474 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000;
diff --git a/MCL86/Core/Microcode_MCL86.txt b/MCL86/Core/Microcode_MCL86.txt
index 45c7aab..63c9ca8 100644
--- a/MCL86/Core/Microcode_MCL86.txt
+++ b/MCL86/Core/Microcode_MCL86.txt
@@ -29,6 +29,53 @@
 // Revision 4.0 12/2/2022
 // Assigned values to unused flags[1,3,5] for opcode LAHF
 //
+// Revision 5.0 5/5/2026
+// STORE/RESTORE_SEG_PREFIX use r2 scratch instead of stashing the
+// segment-override prefix bit in eu_flags bit 4 (AF). The original
+// procedure corrupted architectural AF on every string-op call site
+// (8086 spec says string ops preserve flags). r2 is dead during string
+// ops since the INC16/DEC16 flag-processing path that uses r2 isn't
+// called between STORE and RESTORE.
+//
+// Revision 6.0 5/6/2026
+// Segment-load interrupt-poll fix. Real 8086 only delays interrupts by
+// one instruction after MOV/POP to SS (atomic stack reload), not after
+// other segment-register loads. Previously, all POP_SEGREG (POP ES/CS/
+// SS/DS at 0x07/0x0F/0x17/0x1F) and all MOV Sreg (the 0x8E group)
+// converged on the legacy 0x0470-0x0478 ending whose final jump skips
+// the interrupt-poll section of the main fetch loop (jumps to 0x0011
+// instead of 0x0006). That caused the worker to miss hardware
+// interrupts taken by MartyPC after POP DS / POP ES / MOV ES / MOV DS,
+// because the worker's microcode bypassed the 0x0008 intr_asserted
+// test in the fetch loop following these instructions.
+//
+// Fix: split the common ending into two:
+//   * 0x0470-0x0478 (legacy): final jump to 0x0011, used by POP SS and
+//     MOV SS to preserve the architecturally-mandated 1-instruction
+//     interrupt delay for atomic stack reload.
+//   * 0x0FC7-0x0FCF (new): mirror of 0x0470-0x0478 with final jump to
+//     0x0006 (with INT poll), used by POP ES/CS/DS and MOV ES/CS/DS.
+// MOV ES/CS/DS reach the new tail via 0x0D63 redirected from 0x0474 to
+// 0x0FCB (the PFQ-wait entry of the new tail). MOV SS bypasses 0x0D62
+// /0x0D63 entirely by jumping from 0x0D6B to a new SS-specific
+// debounce + skip-INT path at 0x0FD0-0x0FD1.
+//
+// Revision 7.0 5/11/2026
+// IRET (0xCF) interrupt-recognition fix. Real 8086 only delays
+// interrupt recognition after STI / MOV SS / POP SS; IRET does not.
+// MCL86jr's microcode and EU both deferred INT after IRET for two
+// reasons, both fixed here:
+//   1. IRET's ending jumped to the legacy 0x0470-0x0478 skip-INT
+//      path. Switched to the V6 with-INT-poll path (0x0FCB).
+//   2. Even with the with-INT-poll path, the EU's intr_enable_delayed
+//      register only updates on new_instruction edges, so the IRET
+//      microcode's post-FLAGS-load intr poll would still see IF=0.
+//      eu.v now also bypasses that delay when the microcode is at
+//      IRET's "OR r0 into FLAGS" step (eu_rom_address == 0x0532),
+//      syncing intr_enable_delayed from the ALU output's bit 9 in
+//      the same cycle.
+// Caught running King's Quest I on PCjr: BIOS timer ISR's IRET to
+// user code races the next 18.2Hz tick.
 //
 //------------------------------------------------------------------------
 //
@@ -2451,15 +2498,21 @@ p 00 00000 00001 02BE
 p 01 00000 00001 5FFF
 p 01 00000 00001 C492
 #
-# Dummy = AX OR 0x0000 to populate last_alu for flags processing
+# Dummy = AL only (AX AND 0x00FF) to populate last_alu for flags
+# processing. AAD's flags (SF, ZF, PF) are defined on AL per Intel
+# spec, not on the full AX word. AAD always zeroes AH in the body
+# (0x02BB/0x02BD), so for AAD specifically AX AND 0xFF == AX, but
+# calling CALCULATE_FLAGS_BYTE makes the byte-domain explicit and
+# keeps the SF check on AL bit 7 (not AX bit 15).
 p 00 00000 00001 02BF
-p 01 00000 00001 5E0F
-p 01 00000 00001 0000
+p 01 00000 00001 4E0F
+p 01 00000 00001 00FF
 #
-# Call All_Flags_WORD
+# Call CALCULATE_FLAGS_BYTE (byte-domain SF/ZF/PF for AL result).
+# Was: CALL All_Flags_WORD (0x03D3) — wrong domain for AAM/AAD.
 p 00 00000 00001 02C0
 p 01 00000 00001 1100
-p 01 00000 00001 03D3
+p 01 00000 00001 0990
 #
 # Jump unconditional to Multibyte ending
 p 00 00000 00001 02C1
@@ -2554,15 +2607,23 @@ p 00 00000 00001 02D6
 p 01 00000 00001 5FFF
 p 01 00000 00001 C675
 #
-# Dummy = AX OR 0x0000 to populate last_alu for flags processing
+# Dummy = AL only (AX AND 0x00FF) to populate last_alu for flags
+# processing. AAM's flags (SF, ZF, PF) are defined on AL per Intel
+# spec, NOT on the full AX word. Original code populated alu_last
+# with AX, then All_Flags_WORD's bit-15 SF check and 16-bit ZF check
+# tripped on the AH=quotient byte — e.g. AL_pre=0x50, AAM 10 →
+# AX=0x0800, AL=0 (so ZF should be 1), but All_Flags_WORD saw
+# alu_last=0x0800 ≠ 0 and left ZF=0. Caught by Lotus 1-2-3 cosim
+# at op 4901806 in CS:IP F000:19CB-area.
 p 00 00000 00001 02D7
-p 01 00000 00001 5E0F
-p 01 00000 00001 0000
+p 01 00000 00001 4E0F
+p 01 00000 00001 00FF
 #
-# Call All_Flags_WORD
+# Call CALCULATE_FLAGS_BYTE (byte-domain SF/ZF/PF for AL result).
+# Was: CALL All_Flags_WORD (0x03D3) — wrong domain; checked AX.
 p 00 00000 00001 02D8
 p 01 00000 00001 1100
-p 01 00000 00001 03D3
+p 01 00000 00001 0990
 #
 # Jump unconditional to Multibyte ending
 p 00 00000 00001 02D9
@@ -4646,10 +4707,13 @@ p 00 00000 00001 045A
 p 01 00000 00001 4DDF
 p 01 00000 00001 CFF3
 #
-# Jump unconditional to POP_SEGREG ending
+# Jump unconditional to POP_SEGREG_WITH_INT ending (0xFC7) — POP ES
+# polls INT on completion, real-8086 behavior. POP SS keeps the legacy
+# skip-INT ending at 0x0470 (1-instruction interrupt delay for atomic
+# stack reload).
 p 00 00000 00001 045B
 p 01 00000 00001 1000
-p 01 00000 00001 0470
+p 01 00000 00001 0FC7
 #
 #
 # -----------------------------------------------------
@@ -4678,10 +4742,12 @@ p 00 00000 00001 045F
 p 01 00000 00001 4DDF
 p 01 00000 00001 CFD3
 #
-# Jump unconditional to POP_SEGREG ending
+# Jump unconditional to POP_SEGREG_WITH_INT ending (0xFC7) — POP CS
+# polls INT on completion (POP CS isn't a real 8086 opcode in modern
+# decode, but the handler exists; same fix as POP ES/DS).
 p 00 00000 00001 0460
 p 01 00000 00001 1000
-p 01 00000 00001 0470
+p 01 00000 00001 0FC7
 #
 #
 # -----------------------------------------------------
@@ -4742,10 +4808,11 @@ p 00 00000 00001 0469
 p 01 00000 00001 4DDF
 p 01 00000 00001 CFC3
 #
-# Jump unconditional to POP_SEGREG ending
+# Jump unconditional to POP_SEGREG_WITH_INT ending (0xFC7) — POP DS
+# polls INT on completion, real-8086 behavior.
 p 00 00000 00001 046A
 p 01 00000 00001 1000
-p 01 00000 00001 0470
+p 01 00000 00001 0FC7
 #
 # -----------------------------------------------------
 #
@@ -5640,7 +5707,13 @@ p 00 00000 00001 0531
 p 01 00000 00001 488F
 p 01 00000 00001 0000
 #
-# OR r0 into Flags register
+# OR r0 into Flags register. eu.v detects this microcode step (when
+# eu_rom_data delivers this word, which is when eu_rom_address has
+# already advanced to 0x0533 due to the 1-cycle synchronous BRAM
+# read) and immediately syncs intr_enable_delayed from bit 9 of the
+# ALU output, so the post-load intr poll sees IF=1 without waiting
+# for the next new_instruction edge. Real 8086 takes pending
+# interrupts right after IRET.
 p 00 00000 00001 0532
 p 01 00000 00001 5889
 p 01 00000 00001 0000
@@ -5675,10 +5748,14 @@ p 00 00000 00001 0538
 p 01 00000 00001 4DDF
 p 01 00000 00001 0000
 #
-# Jump unconditional to common code that waits for prefetch queue, then returns to main loop skipping all interrupts.
+# Jump to PFQ-wait entry of the with-INT-poll ending (0xFCB). Real
+# 8086 only delays interrupt recognition after STI / MOV SS / POP SS;
+# IRET should NOT defer — the BIOS timer ISR returns via IRET and
+# expects the NEXT 18.2Hz tick to be taken immediately if it lands
+# during IRET. Was 0x0474 (legacy skip-INT path used by POP/MOV SS).
 p 00 00000 00001 0539
 p 01 00000 00001 1000
-p 01 00000 00001 0474
+p 01 00000 00001 0FCB
 #
 # -----------------------------------------------------
 #
@@ -8234,7 +8311,16 @@ p 01 00000 00001 0011
 #
 # PROCEDURE - STORE_SEG_PREFIX
 #
-# Store the Segment Override Prefix bit in the AF Flag temporarily
+# Stash the Segment Override Prefix bit in scratch register r2 across a
+# BIU operation that needs the override cleared (e.g. MOVS dest write
+# after a DS-overridden source read). Originally this used eu_flags
+# bit 4 (AF) as the stash, but that corrupts the architectural AF flag
+# on every string-op call site (8086 says string ops preserve flags).
+# Cannot use r0/r1 as scratch — CMPSB/CMPSW load r0 with the source
+# byte at 0x0645 and r1 with the dest byte at 0x064B, with the
+# STORE_SEG_PREFIX call sandwiched at 0x0646. r3 is the BIU address
+# register (set to SI then DI between calls), also unsafe. r2 is dead
+# across all string-op STORE/RESTORE windows.
 #
 # --------------------------------------------------------------------
 #
@@ -8248,10 +8334,10 @@ p 00 00000 00001 0751
 p 01 00000 00001 1002
 p 01 00000 00001 0755
 #
-# Set eu_alu_a flag to 1
+# r2 = 1 (scratch: segment override was set)
 p 00 00000 00001 0752
-p 01 00000 00001 588F
-p 01 00000 00001 0010
+p 01 00000 00001 5BFF
+p 01 00000 00001 0001
 #
 # Set segment_override prefix bit to 0
 p 00 00000 00001 0753
@@ -8263,10 +8349,10 @@ p 00 00000 00001 0754
 p 01 00000 00001 1030
 p 01 00000 00001 4000
 #
-# B: Set eu_alu_a flag to 0
+# B: r2 = 0 (scratch: segment override was clear)
 p 00 00000 00001 0755
-p 01 00000 00001 488F
-p 01 00000 00001 FFEF
+p 01 00000 00001 5BFF
+p 01 00000 00001 0000
 #
 # Set segment_override prefix bit to 0
 p 00 00000 00001 0756
@@ -8282,15 +8368,16 @@ p 01 00000 00001 4000
 #
 # PROCEDURE - RESTORE_SEG_PREFIX
 #
-# Retore the Segment Override Prefix bit from the AF Flag
-# The override prefix is assumed to be 0 before entering this procedure.
+# Restore the Segment Override Prefix bit from scratch register r2
+# (saved by STORE_SEG_PREFIX). The override prefix is assumed to be 0
+# before entering this procedure.
 #
 # --------------------------------------------------------------------
 #
-# Isolate eu_alu_a flag into Dummy
+# Isolate r2 bit 0 (saved segment-override bit) into Dummy
 p 00 00000 00001 075A
-p 01 00000 00001 4E8F
-p 01 00000 00001 0010
+p 01 00000 00001 4EBF
+p 01 00000 00001 0001
 #
 # Return to calling code if last ALU=0
 p 00 00000 00001 075B
@@ -16047,10 +16134,13 @@ p 00 00000 00001 0D62
 p 01 00000 00001 4DDF
 p 01 00000 00001 0000
 #
-# Jump unconditional to common code that waits for prefetch queue, then returns to main loop skipping polling all interrupts
+# Jump unconditional to PFQ-wait entry of POP_SEGREG_WITH_INT ending
+# (0xFCB). MOV ES/CS/DS now poll INT on completion, real-8086 behavior.
+# MOV SS bypasses this by going through 0xFD0 (SS-specific debounce
+# that jumps to legacy skip-INT 0x0474).
 p 00 00000 00001 0D63
 p 01 00000 00001 1000
-p 01 00000 00001 0474
+p 01 00000 00001 0FCB
 #
 # Update the CS Segment Register
 # ------------------------------
@@ -16085,10 +16175,12 @@ p 00 00000 00001 0D6A
 p 01 00000 00001 5DFF
 p 01 00000 00001 3010
 #
-# Jump unconditional to common code
+# Jump unconditional to SS-specific debounce + skip-INT (0xFD0) so MOV
+# SS keeps the 1-instruction interrupt delay for atomic stack reload.
+# MOV ES/CS/DS continue through 0x0D62 → 0x0D63 → 0xFCB (with INT).
 p 00 00000 00001 0D6B
 p 01 00000 00001 1000
-p 01 00000 00001 0D62
+p 01 00000 00001 0FD0
 #
 # Update the DS Segment Register
 # ------------------------------
@@ -18689,6 +18781,84 @@ p 01 00000 00001 1000
 p 01 00000 00001 00C6
 #
 #
+#
+# -----------------------------------------------------
+# POP/MOV ES/CS/DS "with INT poll" common ending. Mirror of legacy
+# 0x0470-0x0478 ending, but final jump returns to 0x0006 (with INT)
+# instead of 0x0011 (skip INT). Real 8086 only delays interrupts after
+# segment-register loads to SS (POP SS / MOV SS / LSS); ES/CS/DS loads
+# do not delay. POP/MOV SS keep their existing 0x0470-based path.
+#
+# POP ES/CS/DS handlers jump to 0xFC7 (start). MOV ES/CS/DS reach
+# 0xFCB (PFQ-wait entry) via 0x0D63's redirected jump.
+# -----------------------------------------------------
+#
+# Write 12 clocks to clock counter (== 0x0470)
+p 00 00000 00001 0FC7
+p 01 00000 00001 5FFF
+p 01 00000 00001 C02B
+#
+# CALL WAIT_CLOCKS (== 0x0471)
+p 00 00000 00001 0FC8
+p 01 00000 00001 1100
+p 01 00000 00001 03F2
+#
+# Strobe BIU - Fetch Opcode (== 0x0472)
+p 00 00000 00001 0FC9
+p 01 00000 00001 5DDF
+p 01 00000 00001 1004
+#
+# Debounce BIU Strobe (== 0x0473)
+p 00 00000 00001 0FCA
+p 01 00000 00001 4DDF
+p 01 00000 00001 0000
+#
+# AND with PFQ_EMPTY mask (== 0x0474; MOV ES/CS/DS enter here)
+p 00 00000 00001 0FCB
+p 01 00000 00001 4EEF
+p 01 00000 00001 0080
+#
+# Jump back to 0xFCB if PFQ empty (== 0x0475)
+p 00 00000 00001 0FCC
+p 01 00000 00001 1002
+p 01 00000 00001 0FCB
+#
+# Clear prefix flags (== 0x0476)
+p 00 00000 00001 0FCD
+p 01 00000 00001 488F
+p 01 00000 00001 0FD5
+#
+# Clear BIU command (== 0x0477)
+p 00 00000 00001 0FCE
+p 01 00000 00001 4DDF
+p 01 00000 00001 0000
+#
+# Jump to main loop start at 0x0006 (with INT poll). This is the only
+# difference from 0x0478, which jumps to 0x0011 (skip INT).
+p 00 00000 00001 0FCF
+p 01 00000 00001 1000
+p 01 00000 00001 0006
+#
+
+#
+# -----------------------------------------------------
+# MOV SS-specific debounce + skip-INT jump. MOV SS at 0x0D6B redirects
+# here so it bypasses the 0x0D63 path (which now points at the with-INT
+# tail) and lands on the legacy skip-INT 0x0474 ending.
+# -----------------------------------------------------
+#
+# Debounce BIU Strobe (mirror of 0x0D62)
+p 00 00000 00001 0FD0
+p 01 00000 00001 4DDF
+p 01 00000 00001 0000
+#
+# Jump to legacy skip-INT PFQ-wait (== old 0x0D63 → 0x0474)
+p 00 00000 00001 0FD1
+p 01 00000 00001 1000
+p 01 00000 00001 0474
+#
+
+
 
 # DONE 
 
diff --git a/MCL86/Core/biu_min.v b/MCL86/Core/biu_min.v
index 36418d2..ff2542a 100644
--- a/MCL86/Core/biu_min.v
+++ b/MCL86/Core/biu_min.v
@@ -108,6 +108,14 @@ reg   clk_d3;
 reg   clk_d4;
 reg   eu_biu_req_caught;
 reg   eu_biu_req_d1;
+// Stage a pending CS-register update so the visible biu_register_cs only
+// changes when the matching JMP/CALL/RET request (eu_biu_req_code 5'h19)
+// lands -- atomic with pfq_addr_in. Real 8088 microcode treats CS+IP as a
+// single update from the BIU's point of view; without staging the BIU
+// briefly sees new CS + old pfq_addr_in, and any prefetch dispatched in
+// that window forms a phantom (new_CS << 4) + old_pfq_addr_in address.
+reg [15:0] biu_register_cs_staged;
+reg        cs_update_staged;
 reg   eu_prefix_lock_d1;
 reg   eu_prefix_lock_d2;
 reg   intr_d1;
@@ -127,6 +135,12 @@ wire  eu_prefix_seg;
 wire  pfq_empty;
 reg  [7:0]  ad_in_int;
 reg  [19:0] addr_out_temp;
+// Latched byte-1 offset for word reads, used to compute byte 2 with
+// proper 8086-style offset wrap (byte_2_offset = (byte_1_offset+1)&0xFFFF).
+// Avoids both a 16-bit-only linear increment (which gives wrong addresses
+// at 0x?FFFF for non-paragraph-aligned segments) and a naive 20-bit
+// linear increment (which is wrong for offset=0xFFFF wrap).
+reg  [15:0] biu_byte1_offset;
 reg  [7:0]  biu_state;
 reg  [15:0] biu_register_cs;
 reg  [15:0] biu_register_es;
@@ -259,6 +273,8 @@ begin : BIU_STATE_MACHINE
       eu_register_r3_d <= 'h0;
       eu_biu_req_caught <= 'h0;
       biu_register_cs <= 16'hFFFF;
+      biu_register_cs_staged <= 16'hFFFF;
+      cs_update_staged <= 1'b0;
       biu_register_es <= 'h0;
       biu_register_ss <= 'h0;
       biu_register_ds <= 'h0;
@@ -281,6 +297,7 @@ begin : BIU_STATE_MACHINE
       eu_biu_req_d1 <= 'h0;
       latched_data_in <= 'h0;
       addr_out_temp <= 'h0;
+      biu_byte1_offset <= 'h0;
       s_bits <= 3'b111;
       AD_OUT <= 'h0;
       word_cycle <= 1'b0;
@@ -400,7 +417,10 @@ else
         case (eu_biu_req_code[2:0])  // synthesis parallel_case
           3'h0 : biu_register_es      <= EU_BIU_DATAOUT[15:0];
           3'h1 : biu_register_ss      <= EU_BIU_DATAOUT[15:0];
-          3'h2 : biu_register_cs      <= EU_BIU_DATAOUT[15:0];
+          3'h2 : begin
+                   biu_register_cs_staged <= EU_BIU_DATAOUT[15:0];
+                   cs_update_staged       <= 1'b1;
+                 end
           3'h3 : biu_register_ds      <= EU_BIU_DATAOUT[15:0];
           3'h4 : biu_register_rm      <= EU_BIU_DATAOUT[15:0];
           3'h5 : biu_register_reg     <= EU_BIU_DATAOUT[15:0];
@@ -437,10 +457,17 @@ else
       end                         
         
         
-    if (eu_biu_req_caught==1'b1 && eu_biu_req_code==5'h19) 
+    if (eu_biu_req_caught==1'b1 && eu_biu_req_code==5'h19)
       begin
         pfq_addr_in <= eu_register_r3_d; // Update the prefetch queue to the new address.
-      end    
+        // Atomically commit the staged CS (if any) at the same edge so
+        // prefetches from this point onward see (new CS, new pfq_addr_in).
+        if (cs_update_staged)
+          begin
+            biu_register_cs    <= biu_register_cs_staged;
+            cs_update_staged   <= 1'b0;
+          end
+      end
     else if (pfq_write==1'b1)
       begin  
         pfq_addr_in <= pfq_addr_in + 1;
@@ -485,6 +512,7 @@ else
                       // Interrupt ACK Cycle 
                       8'h16 : begin                   
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 //AD_OE <= 'h0;                   
                                 word_cycle <= 1'b1;
                                 s_bits <= 3'b000;
@@ -494,6 +522,7 @@ else
                       // IO Byte Read 
                       8'h08 : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 s_bits <= 3'b001;
                                 biu_state <= 8'h01;
                               end
@@ -501,6 +530,7 @@ else
                       // IO Word Read 
                       8'h1A : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 word_cycle <= 1'b1; 
                                 s_bits <= 3'b001;
                                 biu_state <= 8'h01;
@@ -509,6 +539,7 @@ else
                       // IO Byte Write 
                       8'h0A : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 s_bits <= 3'b010;
                                 biu_state <= 8'h01;
                               end
@@ -516,21 +547,31 @@ else
                       // IO Word Write 
                       8'h1C : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 word_cycle <= 1'b1; 
                                 s_bits <= 3'b010;
                                 biu_state <= 8'h01;
                               end
                                                 
-                      // Halt Request 
+                      // Halt Request: acknowledge immediately without
+                      // running a real bus cycle. A real 8088 HALT is just
+                      // T1 (ALE pulse + S2:S0=011 status) and does NOT wait
+                      // for READY. There's no architectural reason for a
+                      // host platform to drive READY in response to a HALT
+                      // cycle, so running through states 0x02..0x0A risks
+                      // stalling at the READY-wait in state 0x07
+                      // indefinitely on any board that doesn't happen to
+                      // assert READY anyway.
                       8'h18 : begin
-                                addr_out_temp <= { biu_register_cs[15:0] , 4'h0 } + pfq_addr_out[15:0] ;
                                 s_bits <= 3'b011;
-                                biu_state <= 8'h01;
+                                biu_done_int <= 1'b1;
+                                biu_state <= 8'h0B;
                               end
                                             
                       // Memory Byte Read 
                       8'h0C : begin
                                 addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 s_bits <= 3'b101;
                                 biu_state <= 8'h01;
                               end
@@ -538,6 +579,7 @@ else
                       // Memory Word Read 
                       8'h10 : begin
                                 addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 word_cycle <= 1'b1; 
                                 s_bits <= 3'b101;
                                 biu_state <= 8'h01;
@@ -546,6 +588,7 @@ else
                       // Memory Word Read from Stack Segment
                       8'h11 : begin
                                 addr_out_temp <= { biu_register_ss[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 word_cycle <= 1'b1; 
                                 s_bits <= 3'b101;
                                 biu_state <= 8'h01;
@@ -554,6 +597,7 @@ else
                       // Memory Word Read from Segment 0x0000 - Used for interrupt vector fetches
                       8'h12 : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 word_cycle <= 1'b1; 
                                 s_bits <= 3'b101;
                                 biu_state <= 8'h01;
@@ -562,6 +606,7 @@ else
                       // Memory Byte Write 
                       8'h0E : begin
                                 addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 s_bits <= 3'b110;
                                 biu_state <= 8'h01;
                               end
@@ -569,6 +614,7 @@ else
                       // Memory Word Write 
                       8'h13 : begin
                                 addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 word_cycle <= 1'b1; 
                                 s_bits <= 3'b110;
                                 biu_state <= 8'h01;
@@ -577,6 +623,7 @@ else
                       // Memory Word Write to Stack Segment
                       8'h14 : begin
                                 addr_out_temp <= { biu_register_ss[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 word_cycle <= 1'b1; 
                                 s_bits <= 3'b110;
                                 biu_state <= 8'h01;
@@ -732,7 +779,19 @@ else
                 INTA_n <= 1'b1;
 
                 
-                 addr_out_temp[15:0] <=  addr_out_temp[15:0] + 1;
+                 // Byte-2 of word access: 8086 wraps the OFFSET within
+                 // the segment (byte_2_offset = (byte_1_offset+1)&0xFFFF).
+                 // For offset != 0xFFFF this is just linear+1 (full
+                 // 20-bit so the carry past bit 15 propagates, fixing
+                 // word reads that cross 64KB linear boundaries with
+                 // non-paragraph-aligned segments).
+                 // For offset == 0xFFFF the offset wraps to 0 and
+                 // byte_2_linear = seg*16 = byte_1_linear - 0xFFFF.
+                 if (biu_byte1_offset == 16'hFFFF)
+                   addr_out_temp[19:0] <= addr_out_temp[19:0] - 20'h0FFFF;
+                 else
+                   addr_out_temp[19:0] <= addr_out_temp[19:0] + 1;
+
                  if (word_cycle==1'b1 && byte_num==1'b0)
                    begin        
                      byte_num <= 1'b1;                   
diff --git a/MCL86/Core/ucode_assembler.py b/MCL86/Core/ucode_assembler.py
new file mode 100644
index 0000000..12323c8
--- /dev/null
+++ b/MCL86/Core/ucode_assembler.py
@@ -0,0 +1,172 @@
+#!/usr/bin/env python3
+"""
+Microcode assembler for MCL86 / MCL86jr.
+
+Source format (Microcode_MCL86.txt):
+  Each microcode word is a triplet of `p` lines:
+    p 00 00000 00001 AAAA   # 12-bit ROM address (in hex)
+    p 01 00000 00001 HHHH   # upper 16 bits of 32-bit word
+    p 01 00000 00001 LLLL   # lower 16 bits of 32-bit word
+  The full word at ROM[AAAA] = HHHH:LLLL.
+
+  `d AAAA` lines fill subsequent un-targeted entries (current pointer).
+  `#` lines are comments. Anything else is ignored.
+
+Output formats:
+  - .coe  Xilinx COE format (memory_initialization_vector hex words)
+  - .mem  Verilog $readmemh (one hex word per line)
+"""
+import sys, re, argparse
+
+ROM_SIZE = 4096
+
+def parse_text(path):
+    rom = [0] * ROM_SIZE
+    pending_addr = None
+    pending_high = None
+    cur_addr = 0
+    with open(path) as f:
+        for lineno, raw in enumerate(f, 1):
+            s = raw.strip()
+            if not s or s.startswith('#') or s.startswith('//') or s.startswith('--'):
+                continue
+            tok = s.split()
+            if tok[0] == 'd' and len(tok) >= 2:
+                # default address pointer
+                cur_addr = int(tok[1], 16)
+                continue
+            if tok[0] == 'p' and len(tok) >= 5:
+                tag = tok[1]
+                # tok[3] is the channel/target. 00001 = microcode ROM; 00010 =
+                # simulator control register (Stop CPU / Set trigger / Start CPU).
+                # We only assemble the 00001 microcode stream.
+                channel = tok[3]
+                value = int(tok[-1], 16)
+                if channel != '00001':
+                    # Reset any pending p-record state and skip.
+                    pending_addr = None
+                    pending_high = None
+                    continue
+                if tag == '00':
+                    pending_addr = value & 0xFFF
+                    pending_high = None
+                elif tag == '01':
+                    if pending_high is None:
+                        pending_high = value & 0xFFFF
+                    else:
+                        word = (pending_high << 16) | (value & 0xFFFF)
+                        addr = pending_addr if pending_addr is not None else cur_addr
+                        rom[addr] = word
+                        cur_addr = addr + 1
+                        pending_addr = None
+                        pending_high = None
+                continue
+    return rom
+
+def write_coe(rom, path):
+    with open(path, 'w') as f:
+        f.write('memory_initialization_radix=16;\n')
+        f.write('memory_initialization_vector=')
+        words = ['{:08x}'.format(w) for w in rom]
+        f.write(' '.join(words))
+        f.write(';\n')
+
+def write_mem(rom, path):
+    with open(path, 'w') as f:
+        for w in rom:
+            f.write('{:08x}\n'.format(w))
+
+def parse_coe(path):
+    """Parse a .coe file into a 4096-word list."""
+    with open(path) as f:
+        content = f.read()
+    # Find the memory_initialization_vector= section if present, else treat the
+    # whole file as a sequence of hex words.
+    m = re.search(r'memory_initialization_vector\s*=', content)
+    if m:
+        j = content.rfind(';')
+        if j < m.end(): j = len(content)
+        vec = content[m.end():j]
+    else:
+        # Strip COE header lines like "memory_initialization_radix=16;" and
+        # comment lines, keep the rest as the hex stream.
+        vec = re.sub(r'memory_initialization_radix\s*=\s*\d+\s*;', '', content)
+        vec = re.sub(r';\s*$', '', vec.strip())
+    parts = re.split(r'[\s,]+', vec.strip())
+    rom = [0] * ROM_SIZE
+    for k, p in enumerate(parts):
+        if not p: continue
+        if k >= ROM_SIZE: break
+        rom[k] = int(p, 16)
+    return rom
+
+def cmd_assemble(args):
+    rom = parse_text(args.text)
+    if args.coe:
+        write_coe(rom, args.coe)
+    if args.mem:
+        write_mem(rom, args.mem)
+    if args.print:
+        for k, w in enumerate(rom):
+            if w: print(f'{k:03X} {w:08X}')
+
+def cmd_match(args):
+    """Try to identify which binary .coe the text source produces."""
+    rom_text = parse_text(args.text)
+    candidates = args.coes
+    print(f'Source: {args.text}')
+    print(f'  non-zero words: {sum(1 for w in rom_text if w)}')
+    print()
+    for c in candidates:
+        try:
+            rom_bin = parse_coe(c)
+        except Exception as e:
+            print(f'{c}: parse error: {e}')
+            continue
+        diffs = sum(1 for a, b in zip(rom_text, rom_bin) if a != b)
+        first = next(((k, a, b) for k, (a, b) in enumerate(zip(rom_text, rom_bin)) if a != b), None)
+        print(f'{c}:')
+        print(f'  match: {ROM_SIZE - diffs}/{ROM_SIZE} ({100*(ROM_SIZE-diffs)/ROM_SIZE:.2f}%)')
+        if first is not None:
+            k, a, b = first
+            print(f'  first diff at 0x{k:03X}: text={a:08X} bin={b:08X}')
+
+def cmd_diff(args):
+    """Show all words where text != binary."""
+    rom_text = parse_text(args.text)
+    rom_bin = parse_coe(args.coe)
+    n = 0
+    for k in range(ROM_SIZE):
+        if rom_text[k] != rom_bin[k]:
+            n += 1
+            if n <= args.limit:
+                print(f'{k:03X} text={rom_text[k]:08X} bin={rom_bin[k]:08X}')
+    print(f'... {n} differences total' if n > args.limit else f'{n} differences total')
+
+if __name__ == '__main__':
+    p = argparse.ArgumentParser()
+    sub = p.add_subparsers(dest='cmd')
+
+    pa = sub.add_parser('assemble', help='text -> coe/mem')
+    pa.add_argument('text')
+    pa.add_argument('--coe', help='output .coe file')
+    pa.add_argument('--mem', help='output .mem file (verilog $readmemh)')
+    pa.add_argument('--print', action='store_true')
+    pa.set_defaults(func=cmd_assemble)
+
+    pm = sub.add_parser('match', help='which .coe matches the text source?')
+    pm.add_argument('text')
+    pm.add_argument('coes', nargs='+')
+    pm.set_defaults(func=cmd_match)
+
+    pd = sub.add_parser('diff', help='show differences between text and a .coe')
+    pd.add_argument('text')
+    pd.add_argument('coe')
+    pd.add_argument('--limit', type=int, default=200)
+    pd.set_defaults(func=cmd_diff)
+
+    args = p.parse_args()
+    if not args.cmd:
+        p.print_help()
+        sys.exit(1)
+    args.func(args)
diff --git a/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_5.coe b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_5.coe
new file mode 100644
index 0000000..d5e3183
--- /dev/null
+++ b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_5.coe
@@ -0,0 +1,2 @@
+memory_initialization_radix=16;
+memory_initialization_vector=00000000 00000000 00000000 00000000 488f0fdf 4ddf0000 4cef0008 1001053a 4cef0002 10010562 4cef0100 10010545 00000000 00000000 00000000 00000000 00000000 4eef0080 10110001 10000006 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 4ddf0000 48ff0000 4fff0000 5dff3000 5dff3010 5dff3030 5dff3020 5fffffff 4dff0000 4cff0000 5dff0b98 4eef0040 1001002e 1000002b 4dff0000 10000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 5fffc025 5ddf2000 4ddfcfff 4cef1000 10020043 5ddf1004 4ddfcff3 10000004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 488ffffe 1000005c 688f0001 1000005c 588f0001 1000005c 488ffbff 1000005c 588f0400 1000005c 488ffdff 1000005c 5fffc00c 10000041 590f0000 5a2f0000 50fa0000 52f90000 5fffc01e 10000041 590f0000 5a3f0000 50fa0000 53f90000 5fffc01d 10000041 590f0000 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diff --git a/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_6.coe b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_6.coe
new file mode 100644
index 0000000..8b755ff
--- /dev/null
+++ b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_6.coe
@@ -0,0 +1,2 @@
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diff --git a/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_7.coe b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_7.coe
new file mode 100644
index 0000000..9b4bc02
--- /dev/null
+++ b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_7.coe
@@ -0,0 +1,2 @@
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diff --git a/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_8.coe b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_8.coe
new file mode 100644
index 0000000..54965a9
--- /dev/null
+++ b/MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_8.coe
@@ -0,0 +1,2 @@
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diff --git a/MCL86jr/FPGA/src4synth/biu_min.v b/MCL86jr/FPGA/src4synth/biu_min.v
index 03c8a01..83fe593 100644
--- a/MCL86jr/FPGA/src4synth/biu_min.v
+++ b/MCL86jr/FPGA/src4synth/biu_min.v
@@ -115,6 +115,19 @@ reg   clk_d3;
 reg   clk_d4;
 reg   eu_biu_req_caught;
 reg   eu_biu_req_d1;
+// Stage a pending CS-register update so the visible biu_register_cs only
+// changes when the matching JMP/CALL/RET request (eu_biu_req_code 5'h19)
+// lands -- atomic with pfq_addr_in. Real 8088 microcode treats CS+IP as a
+// single update from the BIU's point of view; MCL86jr's microcode strobes
+// them separately, and without staging the BIU briefly sees new CS + old
+// pfq_addr_in. Two visible bus-level symptoms get fixed by staging:
+//   * No phantom fetch at (new_CS << 4) + old_pfq_addr_in (e.g. F000:0005
+//     out of the reset vector instead of FFFF:0005).
+//   * The prefetch in the gap between CS strobe and JMP request still uses
+//     the OLD CS, producing the real-8088 prefetch overshoot
+//     (e.g. FFFF:0005) that's discarded after the queue flush.
+reg [15:0] biu_register_cs_staged;
+reg        cs_update_staged;
 reg   eu_prefix_lock_d1;
 reg   eu_prefix_lock_d2;
 reg   intr_d1;
@@ -149,6 +162,13 @@ wire clk_falling_edge;
 
 reg  [7:0]  ad_in_int;
 reg  [19:0] addr_out_temp;
+// Latched byte-1 offset for word reads, used to compute byte 2 with
+// proper 8086-style offset wrap (byte_2_offset = (byte_1_offset+1)&0xFFFF).
+// Avoids both the previous 16-bit-only linear increment (which gave wrong
+// addresses at 0x?FFFF for non-paragraph-aligned segments) and a naive
+// 20-bit linear increment (which was wrong for offset=0xFFFF wrap that
+// the BIOS hits at end-of-segment reads).
+reg  [15:0] biu_byte1_offset;
 reg  [7:0]  biu_state;
 reg  [15:0] biu_register_cs;
 reg  [15:0] biu_register_es;
@@ -305,6 +325,8 @@ begin : BIU_STATE_MACHINE
       biu_state <= 8'hD0;
       pfq_write <= 'h0;
       pfq_addr_in <= 'h0;
+      biu_register_cs_staged <= 16'hFFFF;
+      cs_update_staged <= 1'b0;
       biu_return_data_int <= 'h0;
       biu_done_int <= 'h0;
       ready_d1 <= 'h0;
@@ -313,6 +335,7 @@ begin : BIU_STATE_MACHINE
       eu_biu_req_d1 <= 'h0;
       latched_data_in <= 'h0;
       addr_out_temp <= 'h0;
+      biu_byte1_offset <= 'h0;
       s_bits <= 3'b111;
       AD_OUT <= 'h0;
       word_cycle <= 1'b0;
@@ -453,19 +476,24 @@ else
       end
                     
     
-    // Strobe from EU to update the segment and addressing registers
+    // Strobe from EU to update the segment and addressing registers.
+    // CS is staged rather than committed so the BIU keeps prefetching
+    // from the OLD CS until the matching JMP request lands.
     if (eu_biu_strobe==2'b11)
       begin
         case (eu_biu_req_code[2:0])  // synthesis parallel_case
           3'h0 : biu_register_es      <= EU_BIU_DATAOUT[15:0];
           3'h1 : biu_register_ss      <= EU_BIU_DATAOUT[15:0];
-          3'h2 : biu_register_cs      <= EU_BIU_DATAOUT[15:0];
+          3'h2 : begin
+                   biu_register_cs_staged <= EU_BIU_DATAOUT[15:0];
+                   cs_update_staged       <= 1'b1;
+                 end
           3'h3 : biu_register_ds      <= EU_BIU_DATAOUT[15:0];
           3'h4 : biu_register_rm      <= EU_BIU_DATAOUT[15:0];
           3'h5 : biu_register_reg     <= EU_BIU_DATAOUT[15:0];
           default :  ;
         endcase
-      end   
+      end
 
     // Strobe from EU to set the 8088 clock cycle counter
     if (eu_biu_strobe==2'b10)
@@ -494,14 +522,21 @@ else
       end                         
         
         
-    if (eu_biu_req_caught==1'b1 && eu_biu_req_code==5'h19) 
+    if (eu_biu_req_caught==1'b1 && eu_biu_req_code==5'h19)
       begin
         pfq_addr_in <= eu_register_r3_d; // Update the prefetch queue to the new address.
-      end    
+        // Atomically commit the staged CS (if any) at the same edge so
+        // prefetches from this point onward see (new CS, new pfq_addr_in).
+        if (cs_update_staged)
+          begin
+            biu_register_cs    <= biu_register_cs_staged;
+            cs_update_staged   <= 1'b0;
+          end
+      end
     else if (pfq_write==1'b1)
-      begin  
+      begin
         pfq_addr_in <= pfq_addr_in + 1;
-      end                         
+      end
         
       
     // Write to the selected prefetch queue entry.
@@ -536,101 +571,121 @@ else
                         
                     case (eu_biu_req_code)  // synthesis parallel_case
                                         
-                      // Interrupt ACK Cycle 
-                      8'h16 : begin                   
+                      // Interrupt ACK Cycle
+                      8'h16 : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 word_cycle <= 1'b1;
                                 s_bits <= 3'b000;
                                 biu_state <= 8'h01;
                               end
-                                  
-                      // IO Byte Read 
+
+                      // IO Byte Read
                       8'h08 : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 s_bits <= 3'b001;
                                 biu_state <= 8'h01;
                               end
-                                 
-                      // IO Word Read 
+
+                      // IO Word Read
                       8'h1A : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
-                                word_cycle <= 1'b1; 
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
+                                word_cycle <= 1'b1;
                                 s_bits <= 3'b001;
                                 biu_state <= 8'h01;
                               end
-                                                
-                      // IO Byte Write 
+
+                      // IO Byte Write
                       8'h0A : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 s_bits <= 3'b010;
                                 biu_state <= 8'h01;
                               end
-                                                
-                      // IO Word Write 
+
+                      // IO Word Write
                       8'h1C : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
-                                word_cycle <= 1'b1; 
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
+                                word_cycle <= 1'b1;
                                 s_bits <= 3'b010;
                                 biu_state <= 8'h01;
                               end
                                                 
-                      // Halt Request 
+                      // Halt Request: acknowledge immediately without
+                      // running a real bus cycle. A real 8088 HALT is just
+                      // T1 (ALE pulse + S2:S0=011 status) and does NOT wait
+                      // for READY. There's no architectural reason for a
+                      // host platform to drive READY in response to a HALT
+                      // cycle, so running through states 0x02..0x0A risks
+                      // stalling at the READY-wait in state 0x07
+                      // indefinitely on any board that doesn't happen to
+                      // assert READY anyway.
                       8'h18 : begin
-                                addr_out_temp <= { biu_register_cs[15:0] , 4'h0 } + pfq_addr_out[15:0] ;
                                 s_bits <= 3'b011;
-                                biu_state <= 8'h01;
+                                biu_done_int <= 1'b1;
+                                biu_state <= 8'h0B;
                               end
                                             
-                      // Memory Byte Read 
+                      // Memory Byte Read
                       8'h0C : begin
                                 addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 s_bits <= 3'b101;
                                 biu_state <= 8'h01;
                               end
-                                                
-                      // Memory Word Read 
+
+                      // Memory Word Read
                       8'h10 : begin
                                 addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
-                                word_cycle <= 1'b1; 
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
+                                word_cycle <= 1'b1;
                                 s_bits <= 3'b101;
                                 biu_state <= 8'h01;
                               end
-                                                
+
                       // Memory Word Read from Stack Segment
                       8'h11 : begin
                                 addr_out_temp <= { biu_register_ss[15:0] , 4'h0 } + eu_register_r3_d[15:0];
-                                word_cycle <= 1'b1; 
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
+                                word_cycle <= 1'b1;
                                 s_bits <= 3'b101;
                                 biu_state <= 8'h01;
                               end
-                                                
+
                       // Memory Word Read from Segment 0x0000 - Used for interrupt vector fetches
                       8'h12 : begin
                                 addr_out_temp <= { 4'h0 , eu_register_r3_d[15:0] };
-                                word_cycle <= 1'b1; 
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
+                                word_cycle <= 1'b1;
                                 s_bits <= 3'b101;
                                 biu_state <= 8'h01;
                               end
-                                                
-                      // Memory Byte Write 
+
+                      // Memory Byte Write
                       8'h0E : begin
                                 addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
                                 s_bits <= 3'b110;
                                 biu_state <= 8'h01;
                               end
-                                                
-                      // Memory Word Write 
+
+                      // Memory Word Write
                       8'h13 : begin
                                 addr_out_temp <= { biu_muxed_segment[15:0] , 4'h0 } + eu_register_r3_d[15:0];
-                                word_cycle <= 1'b1; 
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
+                                word_cycle <= 1'b1;
                                 s_bits <= 3'b110;
                                 biu_state <= 8'h01;
                               end
-                                                
+
                       // Memory Word Write to Stack Segment
                       8'h14 : begin
                                 addr_out_temp <= { biu_register_ss[15:0] , 4'h0 } + eu_register_r3_d[15:0];
-                                word_cycle <= 1'b1; 
+                                biu_byte1_offset <= eu_register_r3_d[15:0];
+                                word_cycle <= 1'b1;
                                 s_bits <= 3'b110;
                                 biu_state <= 8'h01;
                               end
@@ -832,8 +887,19 @@ else
                   begin
                     den_int <= 1'b1;
                     dtr_int <= 1'b1;
-                    addr_out_temp[15:0] <=  addr_out_temp[15:0] + 1;
-                    
+                    // Byte-2 of word access: 8086 wraps the OFFSET within
+                    // the segment (byte_2_offset = (byte_1_offset+1)&0xFFFF).
+                    // For offset != 0xFFFF this is just linear+1 (full
+                    // 20-bit so the carry past bit 15 propagates, fixing
+                    // word reads that cross 64KB linear boundaries with
+                    // non-paragraph-aligned segments).
+                    // For offset == 0xFFFF the offset wraps to 0 and
+                    // byte_2_linear = seg*16 = byte_1_linear - 0xFFFF.
+                    if (biu_byte1_offset == 16'hFFFF)
+                      addr_out_temp[19:0] <= addr_out_temp[19:0] - 20'h0FFFF;
+                    else
+                      addr_out_temp[19:0] <= addr_out_temp[19:0] + 1;
+
                     if (word_cycle==1'b1 && byte_num==1'b0)
                       begin     
                         byte_num <= 1'b1;                    
@@ -871,8 +937,14 @@ else
                 if (s_bits[2:1]==2'b11) SRAM_D_OE <= 1'b1;
               end
 
-      8'h16 : begin         
-                SRAM_A[15:0] <= addr_out_temp[15:0] + 1'b1;
+      8'h16 : begin
+                // Same byte-2 offset-wrap rule as state 0x0A — full 19-bit
+                // SRAM_A increment for the common case, segment-relative
+                // wrap when byte-1 offset was 0xFFFF.
+                if (biu_byte1_offset == 16'hFFFF)
+                  SRAM_A[18:0] <= addr_out_temp[18:0] - 19'h0FFFF;
+                else
+                  SRAM_A[18:0] <= addr_out_temp[18:0] + 1'b1;
                 SRAM_OE_n <= 1'b1;
                 SRAM_WE_n <= 1'b1;
                 biu_return_data_int[15:0] <= { 8'h00 , SRAM_D_IN[7:0] };
diff --git a/MCL86jr/FPGA/src4synth/eu.v b/MCL86jr/FPGA/src4synth/eu.v
index a1a4022..3412e96 100644
--- a/MCL86jr/FPGA/src4synth/eu.v
+++ b/MCL86jr/FPGA/src4synth/eu.v
@@ -405,7 +405,22 @@ else
   
     // Delay the INTR enable flag until after the next instruction begins.
     // No delay when it is disabled.
-    if (eu_flag_i==1'b0)
+    // Exception: when the microcode is executing IRET's "OR r0 into
+    // FLAGS" step, update intr_enable_delayed in the same cycle
+    // directly from bit 9 of the ALU output (= the new popped IF).
+    // The microcode word is at ROM address 0x0532; ROM has 1-cycle
+    // synchronous read, so eu_rom_data shows that word when
+    // eu_rom_address has advanced to 0x0533. Must come BEFORE the
+    // eu_flag_i==0 short-circuit because eu_flag_i is still the OLD
+    // value at this point (typically 0 — we're returning from an ISR
+    // that ran with CLI). Real 8086 only delays interrupt recognition
+    // after STI / MOV SS / POP SS — not after IRET.
+    if (eu_stall_pipeline==1'b0 && eu_opcode_type!=3'h0 && eu_opcode_type!=3'h1
+        && eu_rom_address==13'h0533)
+      begin
+        intr_enable_delayed <= eu_alu_out[9];
+      end
+    else if (eu_flag_i==1'b0)
       begin
         intr_enable_delayed <= 1'b0;
       end
@@ -623,7 +638,7 @@ else
           4'hB : eu_register_r2   <= eu_alu_out[15:0];
           4'hC : eu_register_r3   <= eu_alu_out[15:0];
           4'hD : eu_biu_command   <= eu_alu_out[15:0];
-          //4'hE : ;             
+          //4'hE : ;
           4'hF : eu_biu_dataout   <= eu_alu_out[15:0];
           default :  ;
         endcase