Add XLEN parameter.

ahmedcharles · ahmedcharles · commit e8eedbee37b9 · 2025-01-06T08:37:54.000Z
diff --git a/cpu/alu.v b/cpu/alu.v
@@ -92,7 +92,7 @@ module tinyqv_shifter (
 
 endmodule
 
-module tinyqv_mul #(parameter B_BITS=16) (
+module tinyqv_mul #(parameter B_BITS) (
     input clk,
 
     input [3:0] a,
diff --git a/cpu/core.v b/cpu/core.v
@@ -3,7 +3,7 @@
    This core module takes decoded instructions and produces output data
  */
 
-module tinyqv_core #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
+module tinyqv_core #(parameter XLEN, parameter NUM_REGS, parameter REG_ADDR_BITS) (
     input clk,
     input rstn,
 
@@ -86,7 +86,7 @@ module tinyqv_core #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
 
     reg [31:0] tmp_data;
 
-    tinyqv_registers #(.REG_ADDR_BITS(REG_ADDR_BITS), .NUM_REGS(NUM_REGS)) 
+    tinyqv_registers #(.XLEN(XLEN), .NUM_REGS(NUM_REGS), .REG_ADDR_BITS(REG_ADDR_BITS))
         i_registers(clk, rstn, wr_en, counter, rs1, rs2, rd, data_rs1, data_rs2, data_rd, return_addr);
 
 
@@ -298,7 +298,7 @@ module tinyqv_core #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
         instr_retired <= instr_complete && !is_stall;
     end
     /* verilator lint_off PINMISSING */  // No carry
-    tinyqv_counter i_instrret (
+    tinyqv_counter #(.OUTPUT_WIDTH(4)) i_instrret (
         .clk(clk),
         .rstn(rstn),
         .add(instr_retired),
diff --git a/cpu/counter.v b/cpu/counter.v
@@ -1,6 +1,6 @@
 /* Counter register for TinyQV */
 
-module tinyqv_counter #(parameter OUTPUT_WIDTH=4) (
+module tinyqv_counter #(parameter OUTPUT_WIDTH) (
     input clk,
     input rstn,
 
diff --git a/cpu/cpu.v b/cpu/cpu.v
@@ -3,7 +3,7 @@
    This CPU module interfaces with memory, the instruction decoder and the core.
  */
 
-module tinyqv_cpu #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
+module tinyqv_cpu #(parameter XLEN, parameter NUM_REGS, parameter REG_ADDR_BITS) (
     input clk,
     input rstn,
 
@@ -68,7 +68,7 @@ module tinyqv_cpu #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
     wire [2:0] additional_mem_ops_de;
     wire mem_op_increment_reg_de;
 
-    tinyqv_decoder i_decoder(
+    tinyqv_decoder #(.XLEN(XLEN), .REG_ADDR_BITS(REG_ADDR_BITS)) i_decoder(
         .instr(instr),
         .imm(imm_de),
 
@@ -294,7 +294,7 @@ module tinyqv_cpu #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
             was_early_branch <= early_branch && !branch;
     end
 
-    tinyqv_core #(.REG_ADDR_BITS(REG_ADDR_BITS), .NUM_REGS(NUM_REGS))  i_core(
+    tinyqv_core #(.XLEN(XLEN), .NUM_REGS(NUM_REGS), .REG_ADDR_BITS(REG_ADDR_BITS)) i_core(
         .clk(clk),
         .rstn(rstn),
         
diff --git a/cpu/decode.v b/cpu/decode.v
@@ -3,10 +3,10 @@
     Note parts of this are from the excellent FemtoRV by Bruno Levy et al.
 */
 
-module tinyqv_decoder #(parameter REG_ADDR_BITS=4) (
+module tinyqv_decoder #(parameter XLEN, parameter REG_ADDR_BITS) (
     input [31:0] instr,
 
-    output reg [31:0] imm,
+    output reg [XLEN-1:0] imm,
 
     output reg is_load,
     output reg is_alu_imm,
@@ -34,25 +34,25 @@ module tinyqv_decoder #(parameter REG_ADDR_BITS=4) (
     output reg       mem_op_increment_reg
 );
 
-    wire [31:0] Uimm = {    instr[31],   instr[30:12], {12{1'b0}}};
-    wire [31:0] Iimm = {{21{instr[31]}}, instr[30:20]};
-    wire [31:0] Simm = {{21{instr[31]}}, instr[30:25],instr[11:7]};
-    wire [31:0] Bimm = {{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
-    wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
+    wire [XLEN-1:0] Uimm = {{XLEN-31{instr[31]}}, instr[30:12], {12{1'b0}}};
+    wire [XLEN-1:0] Iimm = {{XLEN-11{instr[31]}}, instr[30:20]};
+    wire [XLEN-1:0] Simm = {{XLEN-11{instr[31]}}, instr[30:25],instr[11:7]};
+    wire [XLEN-1:0] Bimm = {{XLEN-12{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
+    wire [XLEN-1:0] Jimm = {{XLEN-20{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
 
     // Compressed immediates
-    wire [31:0] CLWSPimm     = {24'b0, instr[3:2], instr[12], instr[6:4], 2'b00};
-    wire [31:0] CSWSPimm     = {24'b0, instr[8:7], instr[12:9], 2'b00};
-    wire [31:0] CLSWimm      = {25'b0, instr[5], instr[12:10], instr[6], 2'b00};  // LW and SW
-    wire [31:0] CLSHimm      = {30'b0, instr[5], 1'b0};  // LH(U) and SH
-    wire [31:0] CLSBimm      = {30'b0, instr[5], instr[6]};  // LBU and SB
-    wire [31:0] CJimm        = {{21{instr[12]}}, instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
-    wire [31:0] CBimm        = {{24{instr[12]}}, instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
-    wire [31:0] CALUimm      = {{27{instr[12]}}, instr[6:2]};          // ADDI, LI, shifts, ANDI
-    wire [31:0] CLUIimm      = {{15{instr[12]}}, instr[6:2], 12'b0};
-    wire [31:0] CADDI16SPimm = {{23{instr[12]}}, instr[4:3], instr[5], instr[2], instr[6], 4'b0};
-    wire [31:0] CADDI4SPimm  = {22'b0, instr[10:7], instr[12:11], instr[5], instr[6], 2'b0};
-    wire [31:0] CSCXTimm     = {{23{instr[12]}}, instr[9:7], instr[10], instr[11], 4'b0};
+    wire [XLEN-1:0] CLWSPimm     = {{XLEN-8{1'b0}}, instr[3:2], instr[12], instr[6:4], 2'b00};
+    wire [XLEN-1:0] CSWSPimm     = {{XLEN-8{1'b0}}, instr[8:7], instr[12:9], 2'b00};
+    wire [XLEN-1:0] CLSWimm      = {{XLEN-7{1'b0}}, instr[5], instr[12:10], instr[6], 2'b00};  // LW and SW
+    wire [XLEN-1:0] CLSHimm      = {{XLEN-2{1'b0}}, instr[5], 1'b0};  // LH(U) and SH
+    wire [XLEN-1:0] CLSBimm      = {{XLEN-2{1'b0}}, instr[5], instr[6]};  // LBU and SB
+    wire [XLEN-1:0] CJimm        = {{XLEN-11{instr[12]}}, instr[8], instr[10:9], instr[6], instr[7], instr[2], instr[11], instr[5:3], 1'b0};
+    wire [XLEN-1:0] CBimm        = {{XLEN-8{instr[12]}}, instr[6:5], instr[2], instr[11:10], instr[4:3], 1'b0};
+    wire [XLEN-1:0] CALUimm      = {{XLEN-5{instr[12]}}, instr[6:2]};          // ADDI, LI, shifts, ANDI
+    wire [XLEN-1:0] CLUIimm      = {{XLEN-17{instr[12]}}, instr[6:2], 12'b0};
+    wire [XLEN-1:0] CADDI16SPimm = {{XLEN-9{instr[12]}}, instr[4:3], instr[5], instr[2], instr[6], 4'b0};
+    wire [XLEN-1:0] CADDI4SPimm  = {{XLEN-10{1'b0}}, instr[10:7], instr[12:11], instr[5], instr[6], 2'b0};
+    wire [XLEN-1:0] CSCXTimm     = {{XLEN-9{instr[12]}}, instr[9:7], instr[10], instr[11], 4'b0};
 
     always @(*) begin
         additional_mem_ops = 3'b000;
diff --git a/cpu/register.v b/cpu/register.v
@@ -7,7 +7,7 @@
     The read bit address is one ahead of write bit address, and both increment every clock.
  */
 
-module tinyqv_registers #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
+module tinyqv_registers #(parameter XLEN, parameter NUM_REGS, parameter REG_ADDR_BITS) (
     input clk,
     input rstn,
 
@@ -26,7 +26,7 @@ module tinyqv_registers #(parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
     output [23:1] return_addr
 );
 
-    reg [31:0] registers [1:NUM_REGS-1];
+    reg [XLEN-1:0] registers [1:NUM_REGS-1];
     wire [3:0] reg_access [0:2**REG_ADDR_BITS-1];
 
     genvar i;
diff --git a/cpu/tinyqv.v b/cpu/tinyqv.v
@@ -6,7 +6,7 @@
 `define default_netname none
 
 // TinyQV CPU and QSPI memory controller wrapper
-module tinyQV (
+module tinyQV #(parameter XLEN=32, parameter NUM_REGS=16, parameter REG_ADDR_BITS=4) (
     input clk,
     input rstn,
 
@@ -89,7 +89,7 @@ module tinyQV (
   reg rst_reg_n;
   always @(posedge clk) rst_reg_n <= rstn;
 
-  tinyqv_cpu cpu(
+  tinyqv_cpu #(.XLEN(XLEN), .NUM_REGS(NUM_REGS), .REG_ADDR_BITS(REG_ADDR_BITS)) cpu(
         .clk(clk),
         .rstn(rst_reg_n),
 
diff --git a/iceFUN/iceFUN.v b/iceFUN/iceFUN.v
@@ -87,7 +87,7 @@ module tinyQV_top (
     wire        data_ready;
     reg [31:0] data_from_read;
 
-    tinyQV i_tinyqv(
+    tinyQV #(.XLEN(32), .NUM_REGS(16), .REG_ADDR_BITS(4)) i_tinyqv(
         .clk(clk),
         .rstn(rst_reg_n),
 
diff --git a/pico_ice/pico_ice.v b/pico_ice/pico_ice.v
@@ -86,7 +86,7 @@ module tinyQV_top (
     wire       debug_stop_txn;
     wire [3:0] debug_rd;
 
-    tinyQV i_tinyqv(
+    tinyQV #(.XLEN(32), .NUM_REGS(16), .REG_ADDR_BITS(4)) i_tinyqv(
         .clk(clk),
         .rstn(rst_reg_n),
 
diff --git a/test/tb_core.v b/test/tb_core.v
@@ -57,7 +57,7 @@ end
     wire [2:0] additional_mem_ops;
     wire mem_op_increment_reg;
 
-    tinyqv_decoder decoder(instr, 
+    tinyqv_decoder #(.XLEN(32), .REG_ADDR_BITS(4)) decoder(instr,
         imm,
 
         is_load,
@@ -107,7 +107,7 @@ end
     wire debug_reg_wen;
     wire [3:0] debug_rd;
 
-    tinyqv_core core(clk,
+    tinyqv_core #(.XLEN(32), .NUM_REGS(16), .REG_ADDR_BITS(4)) core(clk,
         rstn,
         
         imm[counter+:4],
@@ -153,4 +153,4 @@ end
         debug_rd
         );
 
-endmodule
+endmodule
diff --git a/test/tb_counter.v b/test/tb_counter.v
@@ -31,11 +31,11 @@ end
         end
 
     wire [3:0] data;
-    tinyqv_counter i_mcount(clk, rstn, add, last_counter[4:2], data, cy_out);
+    tinyqv_counter #(.OUTPUT_WIDTH(4)) i_mcount(clk, rstn, add, last_counter[4:2], data, cy_out);
 
     always @(posedge clk) begin
         val[last_counter+:4] <= data;
         if (last_counter[4:2] == 3'b111) cy <= cy_out;
     end
 
-endmodule
+endmodule
diff --git a/test/tb_cpu.v b/test/tb_cpu.v
@@ -48,7 +48,7 @@ end
     wire        debug_counter_0;
     wire [3:0] debug_rd;
 
-    tinyqv_cpu cpu(
+    tinyqv_cpu #(.XLEN(32), .NUM_REGS(16), .REG_ADDR_BITS(4)) cpu(
         clk,
         rstn,
 
diff --git a/test/tb_decode.v b/test/tb_decode.v
@@ -44,7 +44,7 @@ initial begin
 end
 `endif
 
-    tinyqv_decoder decoder(instr, 
+    tinyqv_decoder #(.XLEN(32), .REG_ADDR_BITS(4)) decoder(instr,
         imm,
 
         is_load,
@@ -74,4 +74,4 @@ end
 
     assign instr_len[0] = 1'b0;
 
-endmodule
+endmodule
diff --git a/test/tb_decode64.v b/test/tb_decode64.v
@@ -0,0 +1,77 @@
+/* A RISC-V core designed to use minimal area.
+  
+   Aim is to support RV32E 
+ */
+
+module tb_decode64 (
+    input clk,
+    input rstn,
+
+    input [31:0] instr,
+
+    output [63:0] imm,
+
+    output is_load,
+    output is_alu_imm,
+    output is_auipc,
+    output is_store,
+    output is_alu_reg,
+    output is_lui,
+    output is_branch,
+    output is_jalr,
+    output is_jal,
+    output is_ret,
+    output is_system,
+
+    output [2:0] instr_len,
+
+    output [3:0] alu_op,  // See tinyqv_alu for format
+    output [2:0] mem_op,
+
+    output [3:0] rs1,
+    output [3:0] rs2,
+    output [3:0] rd,
+
+    output [2:0] additional_mem_ops,
+    output       mem_op_increment_reg
+);
+
+`ifdef COCOTB_SIM
+initial begin
+  $dumpfile ("decode64.vcd");
+  $dumpvars (0, tb_decode64);
+  #1;
+end
+`endif
+
+    tinyqv_decoder #(.XLEN(64), .REG_ADDR_BITS(4)) decoder(instr,
+        imm,
+
+        is_load,
+        is_alu_imm,
+        is_auipc,
+        is_store,
+        is_alu_reg,
+        is_lui,
+        is_branch,
+        is_jalr,
+        is_jal,
+        is_ret,
+        is_system,
+
+        instr_len[2:1],
+
+        alu_op,  // See tinyqv_alu for format
+        mem_op,
+
+        rs1,
+        rs2,
+        rd,
+
+        additional_mem_ops,
+        mem_op_increment_reg
+             );
+
+    assign instr_len[0] = 1'b0;
+
+endmodule
diff --git a/test/tb_qspi_flash.v b/test/tb_qspi_flash.v
@@ -33,7 +33,7 @@ initial begin
 end
 `endif
 
-    qspi_flash_controller i_flash(
+    qspi_flash_controller #(.DATA_WIDTH_BYTES(2), .ADDR_BITS(24)) i_flash(
         clk,
         rstn,
 
@@ -53,4 +53,4 @@ end
         busy
     );
 
-endmodule
+endmodule
diff --git a/test/tb_register.v b/test/tb_register.v
@@ -38,11 +38,12 @@ end
     wire [3:0] data_rs1;
     wire [3:0] data_rs2;
     wire [23:1] return_addr;
-    tinyqv_registers registers(clk, rstn, wr_en, last_counter[4:2], rs1, rs2, rd, data_rs1, data_rs2, rd_in[last_counter+:4], return_addr);
+    tinyqv_registers #(.XLEN(32), .NUM_REGS(16), .REG_ADDR_BITS(4))
+        registers(clk, rstn, wr_en, last_counter[4:2], rs1, rs2, rd, data_rs1, data_rs2, rd_in[last_counter+:4], return_addr);
 
     always @(posedge clk) begin
         rs1_out[last_counter+:4] <= data_rs1;
         rs2_out[last_counter+:4] <= data_rs2;
     end
 
-endmodule
+endmodule
diff --git a/test/test_decode64.mk b/test/test_decode64.mk
@@ -0,0 +1,19 @@
+# Makefile
+# See https://docs.cocotb.org/en/stable/quickstart.html for more info
+
+# defaults
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+
+CPUD = $(PWD)/../cpu
+VERILOG_SOURCES += $(CPUD)/decode.v $(PWD)/tb_decode64.v
+COMPILE_ARGS    += -DSIM
+
+# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
+TOPLEVEL = tb_decode64
+
+# MODULE is the basename of the Python test file
+MODULE = test_decode64
+
+# include cocotb's make rules to take care of the simulator setup
+include $(shell cocotb-config --makefiles)/Makefile.sim
diff --git a/test/test_decode64.py b/test/test_decode64.py
