Signal_Generator/vivado.log at master · Maxwelltoo/Signal_Generator · GitHub

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#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2708876 on Wed Nov  6 21:40:23 MST 2019
# IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
# Start of session at: Thu Sep  3 08:30:56 2020
# Process ID: 8060
# Current directory: D:/FPGA/Project/Vivado/Signal_Generator
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1964 D:\FPGA\Project\Vivado\Signal_Generator\Signal_Generator.xpr
# Log file: D:/FPGA/Project/Vivado/Signal_Generator/vivado.log
# Journal file: D:/FPGA/Project/Vivado/Signal_Generator\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/FPGA/Project/Vivado/Signal_Generator/Signal_Generator.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/FPGA/Xilinx/vivado/2019.2/data/ip'.
open_project: Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 851.508 ; gain = 222.160
update_compile_order -fileset sources_1
close [ open D:/FPGA/Project/Vivado/Signal_Generator/Signal_Generator.srcs/sources_1/new/Encoder.v w ]
add_files D:/FPGA/Project/Vivado/Signal_Generator/Signal_Generator.srcs/sources_1/new/Encoder.v
update_compile_order -fileset sources_1
exit
INFO: [Common 17-206] Exiting Vivado at Thu Sep  3 09:46:52 2020...