From 2cd720ef0557a5e9237b4fedfd29b52e45c030f8 Mon Sep 17 00:00:00 2001 From: Kaustubh Harapanahalli Date: Sat, 21 Feb 2026 07:32:14 -0700 Subject: [PATCH 01/37] feat: establish initial MPS Lab website infrastructure including Astro components, React features, and content collections. --- .gitignore | 52 + MPS Lab Astro Pipeline Design.md | 156 + README.md | 74 +- astro.config.mjs | 23 + docker-compose.yml | 10 + package-lock.json | 15338 ++++++++++++++++ package.json | 31 + page.html | 254 + server.pid | 1 + src/components/astro/Footer.astro | 63 + src/components/astro/MemberGrid.astro | 77 + src/components/astro/Navbar.astro | 91 + src/components/react/PublicationSearch.tsx | 360 + src/components/react/ThemeToggle.tsx | 27 + src/content/config.ts | 38 + src/content/members/aviral-shrivastava.md | 11 + src/content/members/hwisoo-so.md | 9 + src/content/members/shail-dave.md | 9 + src/content/news/dac-2024-award.md | 8 + src/content/news/tcps-2024.md | 8 + src/content/research/ai-compilers.md | 17 + .../research/intelligent-transportation.md | 17 + src/content/research/ml-acceleration.md | 17 + src/content/research/quantum-ml.md | 17 + .../research/reliability-robustness-ml.md | 17 + src/data/publications.bib | 3103 ++++ src/env.d.ts | 2 + src/layouts/Layout.astro | 37 + src/pages/contact.astro | 84 + src/pages/index.astro | 125 + src/pages/people.astro | 50 + src/pages/publications.astro | 52 + src/pages/research/[...slug].astro | 60 + src/pages/research/index.astro | 86 + src/styles/_theme-dark.scss | 19 + src/styles/_theme-light.scss | 19 + src/styles/main.scss | 46 + tailwind.config.mjs | 45 + tsconfig.json | 7 + 39 files changed, 20457 insertions(+), 3 deletions(-) create mode 100644 .gitignore create mode 100644 MPS Lab Astro Pipeline Design.md create mode 100644 astro.config.mjs create mode 100644 docker-compose.yml create mode 100644 package-lock.json create mode 100644 package.json create mode 100644 page.html create mode 100644 server.pid create mode 100644 src/components/astro/Footer.astro create mode 100644 src/components/astro/MemberGrid.astro create mode 100644 src/components/astro/Navbar.astro create mode 100644 src/components/react/PublicationSearch.tsx create mode 100644 src/components/react/ThemeToggle.tsx create mode 100644 src/content/config.ts create mode 100644 src/content/members/aviral-shrivastava.md create mode 100644 src/content/members/hwisoo-so.md create mode 100644 src/content/members/shail-dave.md create mode 100644 src/content/news/dac-2024-award.md create mode 100644 src/content/news/tcps-2024.md create mode 100644 src/content/research/ai-compilers.md create mode 100644 src/content/research/intelligent-transportation.md create mode 100644 src/content/research/ml-acceleration.md create mode 100644 src/content/research/quantum-ml.md create mode 100644 src/content/research/reliability-robustness-ml.md create mode 100644 src/data/publications.bib create mode 100644 src/env.d.ts create mode 100644 src/layouts/Layout.astro create mode 100644 src/pages/contact.astro create mode 100644 src/pages/index.astro create mode 100644 src/pages/people.astro create mode 100644 src/pages/publications.astro create mode 100644 src/pages/research/[...slug].astro create mode 100644 src/pages/research/index.astro create mode 100644 src/styles/_theme-dark.scss create mode 100644 src/styles/_theme-light.scss create mode 100644 src/styles/main.scss create mode 100644 tailwind.config.mjs create mode 100644 tsconfig.json diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..798e239 --- /dev/null +++ b/.gitignore @@ -0,0 +1,52 @@ +# Local node_modules +node_modules/ +.npm/ + +# Build outputs +dist/ +.output/ +.vercel/ +.netlify/ +.worker/ +public/build/ + +# Astro dev/build outputs +.astro/ +server.log +server_new.pid + +# Logs +logs +*.log +npm-debug.log* +yarn-debug.log* +yarn-error.log* +pnpm-debug.log* +lerna-debug.log* + +# OS/Editor +.DS_Store +.AppleDouble +.LSOverride +Icon +._* +.DocumentRevisions-V100 +.fseventsd +.Spotlight-V100 +.TemporaryItems +.Trashes +.VolumeIcon.icns +.com.apple.timemachine.donotpresent + +# IDEs +.idea/ +.vscode/ + +# Environment variables +.env +.env.* +!.env.example + +# Temporary files +tmp/ +temp/ diff --git a/MPS Lab Astro Pipeline Design.md b/MPS Lab Astro Pipeline Design.md new file mode 100644 index 0000000..73ecdba --- /dev/null +++ b/MPS Lab Astro Pipeline Design.md @@ -0,0 +1,156 @@ +# **MPS Lab Website Overhaul: System Architecture & Implementation Guide** + +## **1\. System Overview** + +This document serves as the implementation blueprint for the MPS Lab website overhaul. The system is designed as a highly performant, fully static website that utilizes the Island **Architecture**. + +**Core Tech Stack:** + +* **Framework:** Astro (Static Site Generation mode) +* **UI Libraries:** React (for complex interactive components only), Tailwind CSS (styling), SCSS/Sass (Theme management), Lucide React (icons). +* **Data Parsing:** bibtex-parse-js (Publications), fuse.js (Client-side search). +* **Hosting:** GitHub Pages via GitHub Actions. +* **Development Environment:** Docker & Docker Compose (Isolated runtime). + +## **2\. UI Design Concepts** + +Below is the targeted visual design for the new MPS Lab website. The design emphasizes a clean, highly readable "Modern Academic" layout with subtle ASU branding (Maroon and Gold accents), ample whitespace, and an accessible grid system for research areas. + +![][image1] + +* **Visual Identity:** Heavy Navy Blue and Green headers (derived from the lab logo) balanced against clean white backgrounds, with ASU Maroon serving as the primary call-to-action color. +* **Component Library:** Tailwind CSS is used to enforce consistent padding, rounded corners, and mobile-first responsive grids across all devices, mapping directly to SCSS-managed theme variables. + +### **Reference Websites (Style Inspiration)** + +To guide the visual development and component styling, the following websites should be used as benchmarks for the aesthetic direction: + +**Modern Academic Focus (Clean, Accessible, Institutional):** + +* [**Stanford AI Lab (SAIL)**](https://ai.stanford.edu/)**:** Excellent use of whitespace, clear typography, and a highly functional layout that feels both academic and modern. +* [**MIT CSAIL**](https://www.csail.mit.edu/)**:** Great example of managing large amounts of news, research groups, and publications without feeling cluttered. +* [**Berkeley AI Research (BAIR)**](https://bair.berkeley.edu/)**:** Minimalist approach that prioritizes content (papers and blog posts) over heavy graphics. + +## **3\. Requirement Fulfillment Mapping** + +* **Req 1: No Backend Needed:** Astro compiles the entire application into pure HTML/CSS/JS during the build step. The site is hosted on GitHub Pages, requiring zero active server management. +* **Req 2: Markdown-Driven Updates:** Lab members, news, and project updates are managed via Astro **Content Collections**. Adding a new Ph.D. student with a pop-up card simply requires dropping a student-name.md file with YAML frontmatter into the src/content/members/ directory. No HTML editing is required. +* **Req 3: Single-File Publication Updates:** Publications are stored in a single src/data/publications.bib file. At build time, Astro parses this file into JSON and passes it to an interactive React Search component. + +## **4\. Agent Implementation Blueprint** + +*Instructions for the Agentic System:* Execute the implementation in the following sequential phases. + +### **Phase 1: Containerized Development Environment Setup** + +**Objective:** Isolate the build tools and runtime environment using Docker *first* to ensure consistency and provide the npm runtime required for the subsequent scaffolding phases. + +1. **Create docker-compose.yml:** In the empty root directory, create a Docker Compose file that maps the local source code into a Node.js container. +2. **Isolate Dependencies:** Use an anonymous volume for node\_modules to prevent host OS conflicts with the container's compiled modules. +3. **Implementation Configuration:** + version: '3.8' + services: + astro: + image: node:20-alpine + working\_dir: /app + volumes: + \- .:/app + \- /app/node\_modules \# Isolates container node\_modules from the host + ports: + \- "4321:4321" \# Astro's default dev port + command: sh \-c "npm install && npm run dev \-- \--host 0.0.0.0" + +### **Phase 2: Initialization & Configuration** + +**Objective:** Scaffold the project and install dependencies using the containerized Node environment established in Phase 1\. + +1. **Initialize Astro:** Run the scaffolding command through the container into the current directory (.): + docker-compose run \--rm astro npm create astro@latest . \-- \--template minimal +2. **Install integrations:** docker-compose run \--rm astro npx astro add react tailwind +3. **Install specific libraries:** docker-compose run \--rm astro npm install lucide-react fuse.js bibtex-parse-js sass +4. **Configure:** Update astro.config.mjs to ensure output: 'static' and that React/Tailwind integrations are active. +5. **Execution:** Once configured, developers/agents will strictly use docker-compose up to start the live-reloading dev server. No source code resides inside the image itself; it is fully mounted from the host. + +### **Phase 3: Directory Structure Setup** + +**Objective:** Establish the routing and data layer skeleton. + +/ +├── public/ \# Static assets (logos, CVs, PDFs) +├── src/ +│ ├── components/ \# Reusable UI parts +│ │ ├── astro/ \# Static UI (Nav, Footer, Static Cards) +│ │ └── react/ \# Interactive UI (Search, ThemeToggle, Modals) +│ ├── content/ \# Markdown Collections +│ │ ├── config.ts \# Zod Schemas for Type Safety +│ │ ├── news/ \# .md files for updates +│ │ └── members/ \# .md files for students/faculty +│ ├── data/ +│ │ └── publications.bib \# The single source of truth for papers +│ ├── layouts/ +│ │ └── Layout.astro \# Global HTML wrapper (Dark mode logic here) +│ ├── pages/ \# Route mapping (index.astro, publications.astro) +│ └── styles/ \# SCSS Theme configuration +│ ├── main.scss \# Main stylesheet importing themes and tailwind +│ ├── \_theme-light.scss \# Light/Academic theme color variables +│ └── \_theme-dark.scss \# Dark/Alternate theme color variables +├── docker-compose.yml \# Containerized dev environment configuration + +### **Phase 4: The Content Collection Layer (Markdown)** + +**Objective:** Enable non-developers to update the site without touching HTML. + +1. **Define Schemas (src/content/config.ts):** \* Create a schema for members requiring name, role (Faculty, Ph.D., Alumni), photoUrl, joinDate, and bio. + * Create a schema for news requiring title, date, and type. +2. **Implementation:** Build an Astro component (MemberGrid.astro) that uses getCollection('members') to loop through the markdown files and render the UI cards. Use a React component (\) if the "pop-up card" requires complex state (like a click-to-expand overlay). + +### **Phase 5: The Publication Pipeline (Single-File)** + +**Objective:** Implement the searchable, filterable publication list. + +1. **Build-Time Parsing:** In src/pages/publications.astro, use Node's fs module to read src/data/publications.bib. +2. Pass the string to bibtex-parse-js to convert it into a structured JavaScript array. +3. **The Interactive Island:** Pass that parsed JSON array as a prop to a React component: \. +4. **Search Logic:** Inside PublicationSearch.jsx, initialize fuse.js on the papers array. Bind an \ to a React state to filter the rendered list in real-time. Render tags (e.g., Year, Topic) that modify a filter state. + +### **Phase 6: UI, SCSS Theme Management, and Responsiveness** + +**Objective:** Apply the MPS Lab styling requirements using dedicated SCSS files connected to Tailwind. + +1. **SCSS Theme Setup:** \* In src/styles/\_theme-light.scss, define the light mode CSS variables (e.g., \--color-primary: \#8C1D40; \--color-bg: \#ffffff;). + * In src/styles/\_theme-dark.scss, define the exact same variables with dark mode values (e.g., \--color-primary: \#FFC627; \--color-bg: \#0f172a;). + * In src/styles/main.scss, import Tailwind directives (@tailwind base; etc.) and import both theme files, nesting the dark theme variables under a .dark class. + * Import main.scss globally inside src/layouts/Layout.astro. +2. **Tailwind Configuration:** In tailwind.config.mjs, map Tailwind's color palette to your SCSS CSS variables (e.g., theme: { extend: { colors: { primary: 'var(--color-primary)' } } }). This ensures bg-primary automatically respects the active SCSS theme file. +3. **Responsiveness:** Ensure all grids use mobile-first breakpoints (e.g., grid-cols-1 md:grid-cols-2 lg:grid-cols-4). Hide desktop navs and show hamburger menus on screens smaller than md. +4. **Dark Mode Engine:** \* Ensure darkMode: 'class' is set in tailwind.config.mjs. + * Create a React component \ that toggles the dark class on the \ element and saves the user's preference to localStorage. + * Add a tiny inline \ in the \ of Layout.astro to read localStorage before the page paints to prevent theme flickering. + +ThemeToggle client:only="react" /\> that toggles the dark class on the \ element and saves the user's preference to localStorage. + +Add a tiny inline \ in the \ of Layout.astro to read localStorage before the page paints to prevent theme flickering. + +### **Phase 7: Google Forms & External Integrations** + +**Objective:** Integrate lead capture/contact forms seamlessly. + +1. Create src/pages/contact.astro. +2. Extract the \ embed code from the desired Google Form. +3. Wrap the iframe in a responsive Tailwind container (aspect-video w-full max-w-2xl mx-auto) to ensure it scales correctly on mobile devices without breaking the layout. + +### **Phase 8: Deployment Configuration** + +**Objective:** Automate GitHub Pages hosting. + +1. Create .github/workflows/deploy.yml. +2. Use the official Astro GitHub Pages action (actions/configure-pages, actions/upload-pages-artifact, actions/deploy-pages). +3. Ensure site and base (if deploying to a subpath) are configured in astro.config.mjs. + +## **5\. Security & Maintenance Notes** + +* **Zero-JS by Default:** Only components explicitly marked with client:load, client:visible, or client:only (like the Search bar or Theme Toggle) will ship JavaScript to the user. Everything else is pure, lightning-fast HTML. +* **Data Integrity:** The Zod schemas in src/content/config.ts will intentionally fail the GitHub Actions build if a lab member accidentally forgets to add a required field (like a Date or Title) to their Markdown file, preventing broken UI from reaching production. +* **Docker Portability:** Because the entire runtime is containerized, any lab member (regardless of OS) can build and test the site locally using docker-compose up without dealing with npm version conflicts or missing global dependencies. + +[image1]: \ No newline at end of file diff --git a/README.md b/README.md index bfc25cf..85d435d 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,72 @@ -Making Programming Simple Lab: -https://labs.engineering.asu.edu/mps-lab/ +# MPS Lab @ ASU - Website -MPS Lab Publications: https://labs.engineering.asu.edu/mps-lab/publications/ +This repository contains the source code for the Make Programming Simple (MPS) Lab website at Arizona State University. The site is built using [Astro](https://astro.build/), [React](https://react.dev/), and [Tailwind CSS](https://tailwindcss.com/). + +**Live Website:** [https://labs.engineering.asu.edu/mps-lab/](https://labs.engineering.asu.edu/mps-lab/) +**Publications list:** [https://labs.engineering.asu.edu/mps-lab/publications/](https://labs.engineering.asu.edu/mps-lab/publications/) + +--- + +## Prerequisites +To run this project locally, you will need either: +- **Node.js**: v20 or higher +- **Docker & Docker Compose** (Optional, recommended for isolated environments) + +--- + +## Local Development (Node.js) + +1. **Install dependencies:** + ```bash + npm install + ``` +2. **Start the development server:** + ```bash + npm run dev + ``` +3. Open `http://localhost:4321` in your browser. + +--- + +## Local Development (Docker) +If you prefer not to install Node locally, you can use the provided Docker Compose configuration. + +1. **Start the environment:** + ```bash + docker compose up + ``` + *(This maps port 4321 to your local machine and automatically runs `npm install` and `npm run dev -- --host 0.0.0.0`)* + +2. Open `http://localhost:4321` in your browser. + +To stop the container: +```bash +docker compose down +``` + +--- + +## Deployment (GitHub Pages) + +This project is configured to be deployed as a static site to GitHub pages. + +1. **Build the project:** + ```bash + npm run build + ``` + This generates the static HTML files into the `dist/` directory. + +2. **GitHub Actions Overview:** + The site uses a continuous integration pipeline (via `.github/workflows/deploy.yml` if configured) to build and publish the Astro site automatically on pushes to the `main` branch. + *(Note: Ensure Astro's `site` and `base` config in `astro.config.mjs` match your GitHub Pages repository settings).* + +--- + +## Content Management + +The website content is powered by **Astro Content Collections** located in `src/content/`. + +- **Members:** Add new markdown files to `src/content/members/`. The schema requires `name`, `role`, and `joinDate`. +- **News:** Add new markdown files to `src/content/news/`. The schema requires `title`, `date`, and `type`. +- **Research:** Add new markdown files to `src/content/research/`. The schema requires `title`, `status` ("Active" or "Extended"), and `description`. +- **Publications:** Managed via a single BibTeX file located at `src/data/publications.bib`. The site uses a React island to parse and search publications flawlessly. diff --git a/astro.config.mjs b/astro.config.mjs new file mode 100644 index 0000000..519dbf7 --- /dev/null +++ b/astro.config.mjs @@ -0,0 +1,23 @@ +import react from '@astrojs/react'; +import tailwind from '@astrojs/tailwind'; +import { defineConfig } from 'astro/config'; + +export default defineConfig({ + output: 'static', + site: 'https://MPSLab-ASU.github.io', + integrations: [ + react(), + tailwind({ + applyBaseStyles: false, + }), + ], + vite: { + css: { + preprocessorOptions: { + scss: { + api: 'modern-compiler', + }, + }, + }, + }, +}); diff --git a/docker-compose.yml b/docker-compose.yml new file mode 100644 index 0000000..d81a4f1 --- /dev/null +++ b/docker-compose.yml @@ -0,0 +1,10 @@ +services: + astro: + image: node:20-alpine + working_dir: /app + volumes: + - .:/app + - /app/node_modules + ports: + - "4321:4321" + command: sh -c "npm install && npm run dev -- --host 0.0.0.0" diff --git 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"integrity": "sha512-gzUt/qt81nXsFGKIFcC3YnfEAx5NkunCfnDlvuBSSFS02bcXu4Lmea0AFIUwbLWxWPx3d9p8S5QoaujKcNQxcQ==", + "license": "MIT", + "funding": { + "url": "https://github.com/sponsors/colinhacks" + } + }, + "node_modules/zod-to-json-schema": { + "version": "3.25.1", + "resolved": "https://registry.npmjs.org/zod-to-json-schema/-/zod-to-json-schema-3.25.1.tgz", + "integrity": "sha512-pM/SU9d3YAggzi6MtR4h7ruuQlqKtad8e9S0fmxcMi+ueAK5Korys/aWcV9LIIHTVbj01NdzxcnXSN+O74ZIVA==", + "license": "ISC", + "peerDependencies": { + "zod": "^3.25 || ^4" + } + }, + "node_modules/zod-to-ts": { + "version": "1.2.0", + "resolved": "https://registry.npmjs.org/zod-to-ts/-/zod-to-ts-1.2.0.tgz", + "integrity": "sha512-x30XE43V+InwGpvTySRNz9kB7qFU8DlyEy7BsSTCHPH1R0QasMmHWZDCzYm6bVXtj/9NNJAZF3jW8rzFvH5OFA==", + "peerDependencies": { + "typescript": "^4.9.4 || ^5.0.2", + "zod": "^3" + } + }, + "node_modules/zwitch": { + "version": "2.0.4", + "resolved": "https://registry.npmjs.org/zwitch/-/zwitch-2.0.4.tgz", + "integrity": "sha512-bXE4cR/kVZhKZX/RjPEflHaKVhUVl85noU3v6b8apfQEc1x4A+zBxjZ4lN8LqGd6WZ3dl98pY4o717VFmoPp+A==", + "license": "MIT", + "funding": { + "type": "github", + "url": "https://github.com/sponsors/wooorm" + } + } + } +} diff --git a/package.json b/package.json new file mode 100644 index 0000000..e7757cb --- /dev/null +++ b/package.json @@ -0,0 +1,31 @@ +{ + "name": "mpslab-asu", + "type": "module", + "version": "1.0.0", + "scripts": { + "dev": "astro dev", + "start": "astro dev", + "build": "astro check && astro build", + "preview": "astro preview", + "astro": "astro" + }, + "dependencies": { + "@astrojs/check": "^0.9.6", + "@astrojs/react": "^4.4.2", + "@astrojs/tailwind": "^6.0.2", + "@types/react": "^19.2.14", + "@types/react-dom": "^19.2.3", + "astro": "^5.17.3", + "bibtex-parse-js": "^0.0.24", + "fuse.js": "^7.1.0", + "lucide-react": "^0.575.0", + "react": "^19.2.4", + "react-dom": "^19.2.4", + "sass": "^1.97.3", + "typescript": "^5.9.3" + }, + "devDependencies": { + "@types/node": "^25.3.0", + "cheerio": "^1.2.0" + } +} diff --git a/page.html b/page.html new file mode 100644 index 0000000..3ad289a --- /dev/null +++ b/page.html @@ -0,0 +1,254 @@ + + + + + + + + Publications – MPS-Lab + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + +
+
+ + + + + + +
+
+ +
+
+

MPS-Lab

+
+
+ + +
+
+ Close + + +
+

MPS-Lab

+

Make Programming Simple

+
+ + +
+ + + +
+ +
+ +
+
+ + +
+
+ + +

Publications

+
+
+ +
+ +
+

Sorry, no publications matched your criteria.

+
+ +
+ +
+
+ + +
+ + + + +
+ + + + + + + + + + + diff --git a/server.pid b/server.pid new file mode 100644 index 0000000..796974c --- /dev/null +++ b/server.pid @@ -0,0 +1 @@ +61467 diff --git a/src/components/astro/Footer.astro b/src/components/astro/Footer.astro new file mode 100644 index 0000000..ea68123 --- /dev/null +++ b/src/components/astro/Footer.astro @@ -0,0 +1,63 @@ +--- +const currentYear = new Date().getFullYear(); +--- + +
+
+
+ +
+
+
+ M +
+
+

MPS Lab

+

Making Programming Simple

+
+
+

+ School of Computing & Augmented Intelligence
+ Arizona State University
+ Tempe, AZ 85281 +

+
+ + +
+

Quick Links

+ +
+ + +
+

Connect

+ +
+
+ +
+

+ © {currentYear} MPS Lab, Arizona State University. All rights reserved. +

+
+
+
diff --git a/src/components/astro/MemberGrid.astro b/src/components/astro/MemberGrid.astro new file mode 100644 index 0000000..a515834 --- /dev/null +++ b/src/components/astro/MemberGrid.astro @@ -0,0 +1,77 @@ +--- +import { getCollection } from 'astro:content'; + +interface Props { + roleFilter?: string; +} + +const { roleFilter } = Astro.props; + +let allMembers = await getCollection('members'); +if (roleFilter) { + allMembers = allMembers.filter(m => m.data.role === roleFilter); +} +allMembers.sort((a, b) => (a.data.order ?? 99) - (b.data.order ?? 99)); + +const roleColors: Record = { + 'Faculty': 'bg-primary/10 text-primary', + 'Ph.D.': 'bg-blue-100 text-blue-700 dark:bg-blue-900/30 dark:text-blue-300', + 'Masters': 'bg-green-100 text-green-700 dark:bg-green-900/30 dark:text-green-300', + 'Postdoc': 'bg-purple-100 text-purple-700 dark:bg-purple-900/30 dark:text-purple-300', + 'Alumni': 'bg-gray-100 text-gray-600 dark:bg-gray-800 dark:text-gray-400', +}; +--- + +
+ {allMembers.map(async (member) => { + const { Content } = await member.render(); + return ( +
+ +
+ {member.data.name.split(' ').map(n => n[0]).join('')} +
+ + +

{member.data.name}

+
+ + {member.data.role} + +
+ + {member.data.researchInterests && ( +
+ {member.data.researchInterests.slice(0, 3).map(tag => ( + {tag} + ))} +
+ )} + + {member.data.email && ( +

{member.data.email}

+ )} + + + +
+ ); + })} +
+ + diff --git a/src/components/astro/Navbar.astro b/src/components/astro/Navbar.astro new file mode 100644 index 0000000..1a557d6 --- /dev/null +++ b/src/components/astro/Navbar.astro @@ -0,0 +1,91 @@ +--- +import ThemeToggle from '../react/ThemeToggle'; + +const navLinks = [ + { href: '/', label: 'Home' }, + { href: '/research', label: 'Research' }, + { href: '/people', label: 'People' }, + { href: '/publications', label: 'Publications' }, + { href: '/contact', label: 'Contact' }, +]; + +const currentPath = Astro.url.pathname; +--- + + + + diff --git a/src/components/react/PublicationSearch.tsx b/src/components/react/PublicationSearch.tsx new file mode 100644 index 0000000..d508f57 --- /dev/null +++ b/src/components/react/PublicationSearch.tsx @@ -0,0 +1,360 @@ +import Fuse from 'fuse.js'; +import { Check, Clipboard, FileText, Filter, Image as ImageIcon, Link, PlaySquare, Presentation, Quote, Search } from 'lucide-react'; +import { useEffect, useMemo, useState } from 'react'; + +interface Publication { + citationKey: string; + entryType: string; + entryTags: { + author?: string; + title?: string; + booktitle?: string; + journal?: string; + year?: string; + keywords?: string; + url?: string; + tppubtype?: string; + }; +} + +interface Props { + papers: Publication[]; + validAuthors?: string[]; + validTags?: string[]; +} + +export default function PublicationSearch({ papers, validAuthors = [], validTags = [] }: Props) { + const [query, setQuery] = useState(''); + const [yearFilter, setYearFilter] = useState(''); + const [authorFilter, setAuthorFilter] = useState(''); + const [typeFilter, setTypeFilter] = useState(''); + const [tagFilter, setTagFilter] = useState(''); + const [currentPage, setCurrentPage] = useState(1); + const [expandedBibtex, setExpandedBibtex] = useState(null); + const [copiedKey, setCopiedKey] = useState(null); + + const ITEMS_PER_PAGE = 20; + + // Reset to page 1 when any filter changes + useEffect(() => { + setCurrentPage(1); + }, [query, yearFilter, authorFilter, typeFilter, tagFilter]); + + const years = useMemo(() => { + const y = [...new Set(papers.map(p => p.entryTags.year).filter(Boolean))].sort().reverse(); + return y as string[]; + }, [papers]); + + const authors = useMemo(() => { + return [...validAuthors].sort(); + }, [validAuthors]); + + const types = useMemo(() => { + return [...new Set(papers.map(p => p.entryTags.tppubtype).filter(Boolean))].sort() as string[]; + }, [papers]); + + const tags = useMemo(() => { + return [...validTags].sort(); + }, [validTags]); + + const fuse = useMemo(() => new Fuse(papers, { + keys: [ + { name: 'entryTags.title', weight: 0.4 }, + { name: 'entryTags.author', weight: 0.3 }, + { name: 'entryTags.keywords', weight: 0.2 }, + { name: 'entryTags.year', weight: 0.1 }, + { name: 'entryTags.booktitle', weight: 0.1 }, + { name: 'entryTags.journal', weight: 0.1 }, + ], + threshold: 0.4, + includeScore: true, + }), [papers]); + + const filtered = useMemo(() => { + let results = query ? fuse.search(query).map(r => r.item) : papers; + if (yearFilter) { + results = results.filter(p => p.entryTags.year === yearFilter); + } + if (authorFilter) { + results = results.filter(p => p.entryTags.author?.includes(authorFilter)); + } + if (typeFilter) { + results = results.filter(p => p.entryTags.tppubtype === typeFilter); + } + if (tagFilter) { + results = results.filter(p => p.entryTags.keywords?.includes(tagFilter)); + } + return results; + }, [query, yearFilter, authorFilter, typeFilter, tagFilter, papers, fuse]); + + const totalPages = Math.ceil(filtered.length / ITEMS_PER_PAGE); + const startIndex = (currentPage - 1) * ITEMS_PER_PAGE; + const paginatedResults = useMemo(() => { + return filtered.slice(startIndex, startIndex + ITEMS_PER_PAGE); + }, [filtered, startIndex]); + + const getVenue = (p: Publication) => p.entryTags.booktitle || p.entryTags.journal || ''; + + // Parse the space/comma-separated URL field: e.g. "https://url1, pdf https://url2, slides" + const parseUrls = (urlString?: string) => { + if (!urlString) return []; + const parts = urlString.split(/(?=https?:\/\/)/); + return parts.map(p => { + const raw = p.trim(); + if (!raw) return null; + const commaIdx = raw.indexOf(','); + if (commaIdx !== -1) { + const url = raw.substring(0, commaIdx).trim(); + let label = raw.substring(commaIdx + 1).trim() || 'Link'; + + // Normalize labels according to user request + const lowerLabel = label.toLowerCase(); + if (lowerLabel.includes('pdf')) label = 'Paper'; + else if (lowerLabel.includes('ppt') || lowerLabel.includes('slide')) label = 'Slides'; + + return { url, label }; + } + return { url: raw, label: 'Link' }; + }).filter(Boolean) as { url: string, label: string }[]; + }; + + const getIconForLabel = (label: string) => { + const l = label.toLowerCase(); + if (l.includes('pdf')) return ; + if (l.includes('slide') || l.includes('ppt')) return ; + if (l.includes('poster')) return ; + if (l.includes('teaser') || l.includes('video')) return ; + return ; + }; + + const generateBibtex = (pub: Publication) => { + let result = `@${pub.entryType}{${pub.citationKey},\n`; + for (const [key, value] of Object.entries(pub.entryTags)) { + // Omit custom/injected 'url' handling for the raw bibtex output + if (value !== undefined && value !== null && key !== 'url') { + result += ` ${key} = {${value}},\n`; + } + } + result += `}`; + return result; + }; + + const handleCopyBibtex = async (pub: Publication) => { + const bibtex = generateBibtex(pub); + try { + await navigator.clipboard.writeText(bibtex); + setCopiedKey(pub.citationKey); + setTimeout(() => setCopiedKey(null), 2000); + } catch (err) { + console.error('Failed to copy bibtex: ', err); + } + }; + + return ( +
+ {/* Search */} +
+ + setQuery(e.target.value)} + className="w-full pl-10 pr-4 py-3 rounded-xl border bg-[var(--color-bg-card)] text-[var(--color-text)] border-[var(--color-border)] focus:ring-2 focus:ring-[var(--color-primary)] focus:border-transparent outline-none transition-all" + /> +
+ + {/* Filters */} +
+
+ + +
+
+ + +
+
+ + +
+ +
+ + +
+
+ + {/* Results Count */} +

+ Showing {filtered.length > 0 ? startIndex + 1 : 0}-{Math.min(startIndex + ITEMS_PER_PAGE, filtered.length)} of {filtered.length} publications +

+ + {/* Publication List */} +
+ {paginatedResults.map(pub => ( +
+
+
+

+ {pub.entryTags.title || pub.citationKey} +

+

+ {pub.entryTags.author?.replace(/ and /ig, '; ')} +

+
+ + {pub.entryTags.year} + + {pub.entryTags.tppubtype && ( + + )} + + {getVenue(pub)} + +
+ {pub.entryTags.keywords && ( +
+ {pub.entryTags.keywords.split(',').map(t => t.trim()).filter(t => validTags.some(v => v.toLowerCase() === t.toLowerCase())).map(kw => ( + + ))} +
+ )} +
+
+
+ {parseUrls(pub.entryTags.url).map((resource, i) => ( + + {getIconForLabel(resource.label)} + {resource.label} + + ))} + +
+
+
+ + {/* Expandable BibTeX Output */} + {expandedBibtex === pub.citationKey && ( +
+
+ BibTeX + +
+ 
+                                    {generateBibtex(pub)}
+
+
+ )} +
+ ))} +
+ + {totalPages > 1 && ( +
+ + + Page {currentPage} of {totalPages} + + +
+ )} + + { + filtered.length === 0 && ( +
+ +

No publications match your search.

+
+ ) + } +
+ ); +} diff --git a/src/components/react/ThemeToggle.tsx b/src/components/react/ThemeToggle.tsx new file mode 100644 index 0000000..cd4312c --- /dev/null +++ b/src/components/react/ThemeToggle.tsx @@ -0,0 +1,27 @@ +import { Moon, Sun } from 'lucide-react'; +import { useEffect, useState } from 'react'; + +export default function ThemeToggle() { + const [isDark, setIsDark] = useState(false); + + useEffect(() => { + setIsDark(document.documentElement.classList.contains('dark')); + }, []); + + const toggle = () => { + const next = !isDark; + setIsDark(next); + document.documentElement.classList.toggle('dark', next); + localStorage.setItem('theme', next ? 'dark' : 'light'); + }; + + return ( + + ); +} diff --git a/src/content/config.ts b/src/content/config.ts new file mode 100644 index 0000000..42d3a41 --- /dev/null +++ b/src/content/config.ts @@ -0,0 +1,38 @@ +import { defineCollection, z } from 'astro:content'; + +const members = defineCollection({ + type: 'content', + schema: z.object({ + name: z.string(), + role: z.enum(['Faculty', 'Ph.D.', 'Masters', 'Undergraduate', 'Alumni', 'Postdoc']), + photoUrl: z.string().optional(), + joinDate: z.string(), + email: z.string().optional(), + website: z.string().optional(), + researchInterests: z.array(z.string()).optional(), + order: z.number().optional(), + }), +}); + +const news = defineCollection({ + type: 'content', + schema: z.object({ + title: z.string(), + date: z.coerce.date(), + type: z.enum(['Award', 'Publication', 'Event', 'Announcement', 'General']), + excerpt: z.string().optional(), + }), +}); + +const research = defineCollection({ + type: 'content', + schema: z.object({ + title: z.string(), + status: z.enum(['Active', 'Extended']), + description: z.string(), + icon: z.string().optional(), + order: z.number().optional(), + }), +}); + +export const collections = { members, news, research }; diff --git a/src/content/members/aviral-shrivastava.md b/src/content/members/aviral-shrivastava.md new file mode 100644 index 0000000..e08ef82 --- /dev/null +++ b/src/content/members/aviral-shrivastava.md @@ -0,0 +1,11 @@ +--- +name: "Aviral Shrivastava" +role: "Faculty" +joinDate: "2006" +email: "aviral.shrivastava@asu.edu" +website: "https://labs.engineering.asu.edu/mps-lab/" +researchInterests: ["Embedded Systems", "Compiler Design", "Computer Architecture", "Cyber-Physical Systems", "Autonomous Vehicles"] +order: 1 +--- + +Dr. Aviral Shrivastava is a Professor in the School of Computing and Augmented Intelligence at Arizona State University and the director of the MPS (Making Programming Simple) Lab. His research focuses on making programming of complex computing platforms simple, efficient, and reliable. His work spans embedded systems, compilers, computer architecture, cyber-physical systems, and autonomous vehicles. diff --git a/src/content/members/hwisoo-so.md b/src/content/members/hwisoo-so.md new file mode 100644 index 0000000..1cb845e --- /dev/null +++ b/src/content/members/hwisoo-so.md @@ -0,0 +1,9 @@ +--- +name: "Hwisoo So" +role: "Ph.D." +joinDate: "2020" +researchInterests: ["DNN Accelerators", "Hardware Design", "Edge Computing"] +order: 5 +--- + +Hwisoo So is a Ph.D. student at MPS Lab working on efficient neural network accelerator architectures for edge devices. His research focuses on designing hardware that enables practical deployment of deep learning models. diff --git a/src/content/members/shail-dave.md b/src/content/members/shail-dave.md new file mode 100644 index 0000000..b20ae4a --- /dev/null +++ b/src/content/members/shail-dave.md @@ -0,0 +1,9 @@ +--- +name: "Shail Dave" +role: "Alumni" +joinDate: "2018" +researchInterests: ["Machine Learning Accelerators", "Neural Architecture Search", "Hardware-Software Co-design"] +order: 10 +--- + +Dr. Shail Dave completed his Ph.D. at MPS Lab working on efficient deployment of deep learning models on specialized hardware accelerators. His research contributed to compiler techniques for spatial DNN accelerators. diff --git a/src/content/news/dac-2024-award.md b/src/content/news/dac-2024-award.md new file mode 100644 index 0000000..cc8a8f0 --- /dev/null +++ b/src/content/news/dac-2024-award.md @@ -0,0 +1,8 @@ +--- +title: "Best Paper Award at DAC 2024" +date: 2024-06-25 +type: "Award" +excerpt: "Our paper on efficient neural network accelerator design received the Best Paper Award at the Design Automation Conference (DAC) 2024." +--- + +We are thrilled to announce that our paper presented at the 61st Design Automation Conference (DAC) 2024 has won the Best Paper Award. This recognition highlights the innovative work being done at MPS Lab in hardware-software co-design for deep learning. diff --git a/src/content/news/tcps-2024.md b/src/content/news/tcps-2024.md new file mode 100644 index 0000000..fda4dc9 --- /dev/null +++ b/src/content/news/tcps-2024.md @@ -0,0 +1,8 @@ +--- +title: "New Publication in IEEE TCPS" +date: 2024-03-15 +type: "Publication" +excerpt: "Our latest work on timestamp-free synchronization for cyber-physical systems has been published in IEEE Transactions on Cyber-Physical Systems." +--- + +A new paper from MPS Lab has been accepted and published in the IEEE Transactions on Cyber-Physical Systems. The work presents novel methods for achieving precise timing in networked cyber-physical systems without requiring explicit timestamp exchange. diff --git a/src/content/research/ai-compilers.md b/src/content/research/ai-compilers.md new file mode 100644 index 0000000..b4e2748 --- /dev/null +++ b/src/content/research/ai-compilers.md @@ -0,0 +1,17 @@ +--- +title: "AI-driven Multi-Level Compilers" +status: "Active" +description: "Leveraging machine learning techniques to optimize compiler designs, creating intelligent intermediate representations for emerging and heterogeneous architectures." +icon: "BookOpen" +order: 3 +--- + +## AI-driven Multi-Level Compilers + +As computer architectures become increasingly heterogeneous, traditional compilation techniques struggle to fully utilize the available hardware. We are exploring the intersection of compilers and AI: + +- **Intelligent Compilations**: Using machine learning to guide compiler optimizations, significantly reducing the search space for the best compilation parameters. +- **Multi-Level Intermediate Representations (MLIR)**: Developing frameworks that allow compilers to represent and optimize code at various levels of abstraction, from high-level domain-specific constructs to low-level hardware instructions. +- **Heterogeneous Computing**: Creating programming models and compilers that simplify the process of writing software for systems that combine CPUs, GPUs, and custom accelerators. + +By making compilers smarter, we reduce the burden on programmers while maximizing the performance of modern computing hardware. diff --git a/src/content/research/intelligent-transportation.md b/src/content/research/intelligent-transportation.md new file mode 100644 index 0000000..9dd3011 --- /dev/null +++ b/src/content/research/intelligent-transportation.md @@ -0,0 +1,17 @@ +--- +title: "Intelligent Transportation Systems" +status: "Active" +description: "Developing robust software, perception pipelines, and safety-critical architectures for next-generation intelligent and autonomous vehicles." +icon: "Car" +order: 2 +--- + +## Intelligent Transportation Systems + +The future of mobility relies heavily on the safety, reliability, and intelligence of software systems in vehicles. At MPS Lab, we are tackling the most pressing challenges in autonomous driving: + +- **Perception Pipeline Optimization**: Improving the efficiency and accuracy of the software pipelines that process sensor data to understand the vehicle's surroundings. +- **Safety-Critical Architectures**: Designing computing architectures that can guarantee the strict timing and reliability requirements necessary for autonomous operation. +- **Hardware Acceleration for AVs**: Utilizing specialized hardware to process complex driving scenarios with minimal latency. + +Our work contributes to the development of safer and more efficient intelligent transportation systems, bridging the gap between advanced algorithms and practical vehicular computing platforms. diff --git a/src/content/research/ml-acceleration.md b/src/content/research/ml-acceleration.md new file mode 100644 index 0000000..d3452e2 --- /dev/null +++ b/src/content/research/ml-acceleration.md @@ -0,0 +1,17 @@ +--- +title: "Machine Learning Acceleration" +status: "Active" +description: "Hardware-software co-design and architectural innovations for efficient, high-performance execution of deep learning models on specialized accelerators and edge devices." +icon: "Cpu" +order: 1 +--- + +## Machine Learning Acceleration + +Deep learning models are becoming increasingly complex, requiring specialized hardware to achieve the necessary performance and energy efficiency. Our research focuses on: + +- **Hardware-Software Co-design**: Developing novel architectures and compilation techniques that work together to optimize neural network inference and training. +- **Edge AI**: Designing efficient accelerators for resource-constrained edge devices, enabling intelligent applications without relying on cloud computation. +- **Dataflow Optimization**: Creating tools to automatically determine and execute the most efficient dataflow mapping for specific neural network models on spatial accelerators. + +We aim to make deploying advanced machine learning models simple, efficient, and accessible across a vast range of computing environments. diff --git a/src/content/research/quantum-ml.md b/src/content/research/quantum-ml.md new file mode 100644 index 0000000..4aad178 --- /dev/null +++ b/src/content/research/quantum-ml.md @@ -0,0 +1,17 @@ +--- +title: "Quantum Machine Learning" +status: "Active" +description: "Pioneering the next generation of artificial intelligence by exploring the intersection of quantum computing and advanced machine learning models." +icon: "Brain" +order: 4 +--- + +## Quantum Machine Learning + +Quantum computing promises exponential speedups for specific classes of problems. At MPS Lab, we are investigating how quantum algorithms can revolutionize machine learning: + +- **Quantum Neural Networks**: Designing and simulating neural network architectures that operate on quantum principles. +- **Quantum Optimization**: Utilizing quantum algorithms to solve complex optimization problems that are critical to training large-scale machine learning models. +- **Hybrid Algorithms**: Developing practical approaches that combine classical computing resources with quantum processors to achieve near-term advantages. + +Our research in Quantum Machine Learning aims to prepare the groundwork for future-ready AI systems capable of tackling problems that are intractable for today's supercomputers. diff --git a/src/content/research/reliability-robustness-ml.md b/src/content/research/reliability-robustness-ml.md new file mode 100644 index 0000000..65aa6c1 --- /dev/null +++ b/src/content/research/reliability-robustness-ml.md @@ -0,0 +1,17 @@ +--- +title: "Reliability for Machine Learning" +status: "Extended" +description: "Ensuring the dependability and predictable performance of machine learning systems in the presence of hardware faults and adversarial conditions." +icon: "Shield" +order: 5 +--- + +## Reliability for Machine Learning + +As machine learning models are deployed in mission-critical applications, their reliability becomes paramount. Our extended research focuses on: + +- **Fault Tolerance**: Developing techniques to detect and recover from transient and permanent hardware faults during neural network execution. +- **Software-level Solutions**: Creating robust algorithms that can tolerate underlying hardware inaccuracies without significant loss in model accuracy. +- **Adversarial Robustness**: Understanding and mitigating vulnerabilities of AI systems to intentional perturbations or unexpected inputs. + +We strive to build machine learning systems that are not just intelligent, but also thoroughly dependable. diff --git a/src/data/publications.bib b/src/data/publications.bib new file mode 100644 index 0000000..8b8b424 --- /dev/null +++ b/src/data/publications.bib @@ -0,0 +1,3103 @@ +@conference{Joshi2025codes, + title = {ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors}, + author = {Sumedh Joshi and Hwisoo So and Aviral Shrivastava }, + url = {https://mpslab-asu.github.io/publications/papers/Joshi2025CODES.pdf, pdf https://mpslab-asu.github.io/publications/slides/Joshi2025CODES.pptx, slides}, + year = {2025}, + date = {2025-10-03}, + urldate = {2025-10-03}, + booktitle = {Proceedings of the 2025 International Conference on Hardware/Software Codesign and System Synthesis}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {Conference} +} + +@mastersthesis{Harapanahalli2025THESIS, + title = {SIGN: A Scalable Incident Detection, Localization, and Severity Estimation using Graph Neural Networks}, + author = {Kaustubh Harapanahalli}, + url = {https://mpslab-asu.github.io/publications/papers/Harapanahalli2025THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Harapanahalli2025THESIS.pptx, slides}, + year = {2025}, + date = {2025-07-07}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {Masters Thesis} +} + +@inproceedings{Lagudu2025LCTES, + title = {LUCI: Lightweight UI Command Interface}, + author = {Guna Lagudu and Vinayak Sharma and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lagudu2025LCTES.pdf, pdf https://mpslab-asu.github.io/publications/slides/Lagudu2025LCTES.pdf, slides}, + doi = {10.1145/3735452.3735536}, + year = {2025}, + date = {2025-06-16}, + urldate = {2025-06-16}, + booktitle = {Proceedings of Languages, Compilers, Tools and Theory of Embedded Systems (LCTES)}, + keywords = {}, + pubstate = {published}, + tppubtype = {Proceedings} +} + +@inproceedings{Kumar2025LCTES, + title = {DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing}, + author = {Abhinav Kumar and Atharva Khedkar and Hwisoo So and Megan Kuo and Ameya Gurjar and Partha Biswas and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kumar2025LCTES.pdf, pdf https://mpslab-asu.github.io/publications/slides/Kumar2025LCTES.pptx, slides}, + doi = {10.1145/3735452.3735527}, + year = {2025}, + date = {2025-06-16}, + urldate = {2025-06-16}, + booktitle = {Proceedings of Languages, Compilers, Tools and Theory of Embedded Systems (LCTES)}, + keywords = {}, + pubstate = {published}, + tppubtype = {Proceedings} +} + +@patent{Khayatian2025Patent, + title = {Cooperative Driving of Connected Autonomous Vehicles in Smart Cities using Responsibility-Sensitive Safety Rules}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Harshith Alamsetti and Aviral Shrivastava }, + url = {https://patents.google.com/patent/US12246753, Google Patents}, + year = {2025}, + date = {2025-03-11}, + urldate = {2025-03-11}, + howpublished = {https://patents.google.com/patent/US12246753/}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {Patent} +} + +@conference{Jagadeesha2025VLSISoC, + title = {TIPANGLE: Traffic Tracking at City Scale by Pose Estimation of Pan and Tilt Traffic Cameras on Edge Devices}, + author = {Shreehari Jagadeesha and Edward Andert and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jagadeesha2025VLSID.pdf, pdf https://mpslab-asu.github.io/publications/slides/Jagadeesha2025VLSID.pdf, slides}, + year = {2025}, + date = {2025-01-21}, + urldate = {2025-01-21}, + booktitle = {IEEE International Conference on Very Large System Integration and Embedded Systems}, + journal = {IEEE International Conference Very Large System Integration and Embedded Systems}, + keywords = {Best Paper Award, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {Conference} +} + +@article{Kim2024Access, + title = {Adversarial Defense on Harmony: Reverse Attack for Robust Models Against Adversarial Attack}, + author = {Yebon Kim and Jinhyo Jung and Hyunjun Kim and Hwisoo So and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee and Uiwon Hwang}, + url = {https://mpslab-asu.github.io/publications/papers/Hwisoo2024IEEE.pdf, pdf}, + year = {2024}, + date = {2024-11-25}, + urldate = {2024-11-25}, + booktitle = {IEEE Access}, + journal = {IEEE Access}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {Article} +} + +@mastersthesis{Joshi2025thesis, + title = {ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors}, + author = {Sumedh Joshi}, + url = {https://mpslab-asu.github.io/publications/papers/Joshi2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Joshi2024THESIS.pdf, slides}, + year = {2024}, + date = {2024-10-24}, + urldate = {2024-10-24}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {Masters Thesis} +} + +@mastersthesis{mendoza2024thesis, + title = {AEGIS: A Special-Purpose Computer Network For Strategic Cyber Defense}, + author = {Francis Mendoza}, + url = {https://mpslab-asu.github.io/publications/papers/Mendoza2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Mendoza2024THESIS.pdf, slides}, + year = {2024}, + date = {2024-09-30}, + urldate = {2024-09-30}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {Masters Thesis} +} + +@conference{Shrivastava2024Cases, + title = {Primer on Data in Quantum Machine Learning}, + author = {Aviral Shrivastava and Vinayak Sharma}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2024CASES.pdf, pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2024CASES.pptx, slides}, + year = {2024}, + date = {2024-09-29}, + urldate = {2024-09-29}, + booktitle = { 2024 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)}, + keywords = {Quantum Machine Learning}, + pubstate = {published}, + tppubtype = {Conference} +} + +@mastersthesis{Kumar2024thesis, + title = {DSP-MLIR: A Compiler for Digital Signal Processing in MLIR}, + author = {Abhinav Kumar and Aviral Shrivastava }, + url = {https://mpslab-asu.github.io/publications/papers/Kumar2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Kumar2024THESIS.pptx, slides}, + year = {2024}, + date = {2024-09-23}, + urldate = {2024-09-23}, + school = {Arizona State University}, + keywords = {Multi-level Intermediate Representation}, + pubstate = {published}, + tppubtype = {Masters Thesis} +} + +@conference{Peddiraju2024ITSC, + title = {IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing}, + author = {Sai Shashank Peddiraju and Kaustubh Harapanahalli and Edward Andert and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Peddiraju2024ITSC.pdf, pdf https://mpslab-asu.github.io/publications/posters/Peddiraju2024ITSC.pptx, slides}, + year = {2024}, + date = {2024-08-02}, + urldate = {2024-08-02}, + booktitle = {2024 IEEE 27th International Conference on Intelligent Transportation Systems (ITSC)}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {Conference} +} + +@conference{Andert2024dac, + title = {Conclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring}, + author = {Edward Andert and Francis Mendoza and Hans Behrens and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Andert2024DAC.pdf, pdf https://mpslab-asu.github.io/publications/slides/Andert2024DAC.pptx, slides}, + year = {2024}, + date = {2024-06-26}, + urldate = {2024-06-26}, + booktitle = {Proceedings of the 61st ACM/IEEE Design Automation Conference}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {Conference} +} + +@conference{Hwisoo2024DAC, + title = {Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs}, + author = {Jinhyo Jung and Hwisoo So and Woobin Ko and Sumedh Shridhar Joshi and Yebon Kim and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Hwisoo2024DAC.pdf, pdf https://mpslab-asu.github.io/publications/slides/Hwisoo2024DAC.pptx, slides}, + year = {2024}, + date = {2024-06-23}, + urldate = {2024-06-23}, + booktitle = {Proceedings of the 61st ACM/IEEE Design Automation Conference}, + journal = {Proceedings of the 61st ACM/IEEE Design Automation Conference}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {Conference} +} + +@phdthesis{Dave2024THESIS, + title = {An Agile Methodology for Designing Efficient Domain-Specific Architectures}, + author = {Shail Dave}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Dave2024THESIS.pptx, slides}, + year = {2024}, + date = {2024-06-10}, + urldate = {2024-06-10}, + keywords = {Machine Learning Accelerator Design}, + pubstate = {published}, + tppubtype = {PhD Thesis} +} + +@mastersthesis{Peddiraju2024Thesis, + title = {IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing}, + author = {Sai Shashank Peddiraju}, + url = {https://mpslab-asu.github.io/publications/papers/Peddiraju2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Peddiraju2024THESIS.pptx, slides}, + year = {2024}, + date = {2024-05-14}, + urldate = {2024-05-14}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {Masters Thesis} +} + +@patent{Dave2024Patent, + title = {Systems and methods for agile and explainable optimization of efficient hardware/software codesigns for domain-specific computing systems using bottleneck analysis}, + author = {Shail Dave and Aviral Shrivastava and Tony Nowatzki}, + url = {https://patents.google.com/patent/US20240134769A1, Google Patents}, + year = {2024}, + date = {2024-04-25}, + urldate = {2024-04-25}, + howpublished = {https://patents.google.com/patent/US20240134769A1/}, + keywords = {Machine Learning Accelerator Design}, + pubstate = {published}, + tppubtype = {Patent} +} + +@mastersthesis{Lagudu2024Thesis, + title = {LUCI: Multi-Application Orchestration Agent}, + author = {Guna Lagudu}, + url = {https://mpslab-asu.github.io/publications/papers/Lagudu2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Lagudu2024THESIS.pptx, slides}, + year = {2024}, + date = {2024-04-08}, + urldate = {2024-04-08}, + school = {Arizona State University}, + keywords = {LLM Applications}, + pubstate = {published}, + tppubtype = {Masters Thesis} +} + +@inproceedings{Dave2024ASPLOS, + title = {Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis}, + author = {Shail Dave and Tony Nowatzki and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2024ASPLOS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Dave2024ASPLOS.pptx, slides https://mpslab-asu.github.io/publications/posters/Dave2024ASPLOS.pdf, poster https://youtu.be/y-F1Cp66_oQ, teaser}, + year = {2024}, + date = {2024-04-02}, + urldate = {2024-04-02}, + booktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)}, + abstract = {Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive number of trials to obtain valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. In this paper, we propose Explainable-DSE – a framework for DSE of DNN accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE is able to identify the bottlenecks and therefore the reasons for design inefficiency, and can therefore make mitigating acquisitions in further explorations. We describe the construction of such bottleneck models for DNN accelerator domain. We also propose an API for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6× lower latency in 47× fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.}, + note = {Won Silver Medal at ACM Student Research Competition 2022-23 (Host: ACM SIGBED)}, + keywords = {Machine Learning Accelerator Design}, + pubstate = {published}, + tppubtype = {Proceedings} +} + +@patent{balasubramanian2024patent, + title = {Systems and methods for fast-mapping of coarse-grained reconfigurable arrays}, + author = {Mahesh Balasubramanian and Aviral Shrivastava}, + url = {https://patents.google.com/patent/US20240311230A1, Google Patents}, + year = {2024}, + date = {2024-03-13}, + urldate = {2024-03-13}, + howpublished = {https://patents.google.com/patent/US20240311230A1/}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {Patent} +} + +@patent{balasubramanian2024patent, + title = {Systems and methods for improved mapping of computational loops on reconfigurable architectures}, + author = {Mahesh Balasubramanian and Aviral Shrivastava}, + url = {https://patents.google.com/patent/US11928468B2, Google Patents}, + year = {2024}, + date = {2024-03-12}, + urldate = {2024-03-12}, + howpublished = {https://patents.google.com/patent/US11928468B2/}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {patent} +} + +@article{shrivastava2024IoTM, + title = {Design Methodology for Robust, Distributed Time-Sensitive Applications}, + author = {Aviral Shrivastava and Mohammad Khayatian and Bob Iannucci}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2024IEEE.pdf, pdf}, + year = {2024}, + date = {2024-01-11}, + urldate = {2024-01-11}, + journal = {IEEE Internet of Things Magazine}, + keywords = {Real-Time Systems, Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@article{Khayatian2024TCPS, + title = {Cooperative Driving of Connected Autonomous Vehicles using Responsibility Sensitive Safety Rules: A Control Barrier Functions Approach}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and I-Ching Tseng and Chung-Wei Lin and Calin Belta and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2024TCPS.pdf, pdf}, + year = {2024}, + date = {2024-01-01}, + urldate = {2024-01-01}, + journal = {IEEE Transactions on Cyber Physical Systems}, + volume = {8}, + issue = {1}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {article} +} + +@article{Willis2024TC, + title = {Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs}, + author = {Benjamin Willis and Aviral Shrivastava and Joshua Mack and Shail Dave and Chaitali Chakrabarti and John Brunhaver}, + url = {https://mpslab-asu.github.io/publications/papers/Willis2024TC.pdf, pdf}, + year = {2024}, + date = {2024-01-01}, + urldate = {2024-01-01}, + journal = {IEEE Transactions on Computers}, + keywords = {}, + pubstate = {published}, + tppubtype = {article} +} + +@workingpaper{sharma2023quantum, + title = {Quantum Polar Metric Learning: Efficient Classically Learned Quantum Embeddings}, + author = {Vinayak Sharma and Aviral Shrivastava }, + url = {https://mpslab-asu.github.io/publications/papers/Sharma2023Arxiv.pdf, pdf https://mpslab-asu.github.io/QPMeL/}, + doi = { https://doi.org/10.48550/arXiv.2312.01655}, + year = {2023}, + date = {2023-12-04}, + urldate = {2023-12-04}, + abstract = {Deep metric learning has recently shown extremely promising results in the classical data domain, creating well-separated feature spaces. This idea was also adapted to quantum computers via Quantum Metric Learning(QMeL). QMeL consists of a 2 step process with a classical model to compress the data to fit into the limited number of qubits, then train a Parameterized Quantum Circuit(PQC) to create better separation in Hilbert Space. However, on Noisy Intermediate Scale Quantum (NISQ) devices. QMeL solutions result in high circuit width and depth, both of which limit scalability. We propose Quantum Polar Metric Learning (QPMeL) that uses a classical model to learn the parameters of the polar form of a qubit. We then utilize a shallow PQC with Ry and Rz gates to create the state and a trainable layer of ZZ(θ)-gates to learn entanglement. The circuit also computes fidelity via a SWAP Test for our proposed Fidelity Triplet Loss function, used to train both classical and quantum components. When compared to QMeL approaches, QPMeL achieves 3X better multi-class separation, while using only 1/2 the number of gates and depth. We also demonstrate that QPMeL outperforms classical networks with similar configurations, presenting a promising avenue for future research on fully classical models with quantum loss functions.}, + howpublished = {ArXiV}, + keywords = {Quantum Machine Learning}, + pubstate = {published}, + tppubtype = {workingpaper} +} + +@mastersthesis{Jagadeesha2023THESIS, + title = {TIPANGLE: A Machine Learning Approach for Accurate Spatial Pan and Tilt Angle Determination of Pan Tilt Traffic Cameras}, + author = {Shreehari Jagadeesha}, + url = {https://mpslab-asu.github.io/publications/papers/Jagadeesha2023THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Jagadeesha2023THESIS.pptx, slides}, + year = {2023}, + date = {2023-11-10}, + urldate = {2023-11-10}, + school = {Arizona State University}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@article{so2023electronics, + title = {gemV-tool: A Comprehensive Soft Error Reliability for Machine Learning Estimation Tool for Design Space Exploration}, + author = {Hwisoo So and Yohan Ko and Jinhyo Jung and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Hwisoo2023Electronics.pdf, pdf}, + year = {2023}, + date = {2023-11-08}, + urldate = {2023-11-08}, + journal = {Electronics 2023, 12(22), 4573}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@conference{Dave2023TECHCON, + title = {Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures}, + author = {Shail Dave and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2023TECHCON.pdf, pdf https://mpslab-asu.github.io/publications/posters/Dave2023TECHCON.pptx, poster}, + year = {2023}, + date = {2023-09-11}, + urldate = {2023-09-11}, + booktitle = {Proceedings of the TECHCON}, + abstract = {Domain-specific architectures (DSAs) are increasingly designed to efficiently process a variety of workloads, such as deep learning, linear algebra, and graph analytics. Most research efforts have focused on proposing new DSAs or efficiently exploring hardware/software designs of previously proposed architecture templates. Recent architectural modeling or simulation frameworks for DSAs can analyze execution costs, e.g., for a limited architectural templates for dense DNNs such as systolic arrays or a spatial architecture with an array of processing elements and 3-level memory hierarchy. However, they are manually developed by domain-experts, containing several 1000s of lines-of-code, and extending them for characterizing new architectures is infeasible, such as DSAs for sparse DNNs. Further, the lack of automated architecture-level execution modeling limits the design space of novel architectures that can be explored/optimized, affecting overall efficiency of solutions, and it delays time-to-market with low sustainability of design process. To address this issue, this paper introduces DSAProf : a framework for automated execution modeling and bottleneck characterization by a modular, dataflow-driven approach. The framework uses a flow-graph-based methodology for modeling DSAs in a modular manner via a library of architectural components and analyzing their executions. The methodology can account for analytically modeling and simulating intricacies in the presence of a variety of architectural features such as asynchronous execution of workgroups, sparse data processing, arbitrary buffer hierarchies, and multi-chip or mixed-precision modules. Preliminary evaluations of modeling previously proposed DSAs for dense/sparse deep learning demonstrate that our approach is extensible for novel DSAs and it can accurately and automatically characterize their latency and identify execution bottlenecks, without requiring designers to manually build analysis/simulator from scratch for every DSA.}, + keywords = {Machine Learning Accelerator Design}, + pubstate = {published}, + tppubtype = {conference} +} + +@article{Szeto2023TECS, + title = {B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles}, + author = {Matthew Szeto and Edward Andert and Aviral Shrivastava and Martin Reisslein and Chung Wei Lin and Christ Richmond}, + url = {https://mpslab-asu.github.io/publications/papers/Szeto2023TECS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Szeto2023THESIS.pptx, slides}, + year = {2023}, + date = {2023-09-09}, + urldate = {2023-09-09}, + journal = {ACM Transactions on Embedded Computing Systems}, + volume = {22}, + number = {154}, + issue = {5}, + pages = {1-23}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {article} +} + +@article{Mehrabian2023MICPRO, + title = {A run-time verification method with consideration of uncertainties for cyber-physical systems}, + author = {Mohammadreza Mehrabian and Mohammad Khayatian and Aviral Shrivastava and Patricia Derler and Hugo Andrade}, + url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2023MICPRO.pdf, pdf}, + year = {2023}, + date = {2023-06-22}, + urldate = {2023-06-22}, + journal = {Microprocessors and Microsystems}, + volume = {101}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{Hu2023MLSYS, + title = {GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing}, + author = {Yi Hu and Chaoran Zhang and Edward Andert and Harshul Singh and Aviral Shrivastava and James Laudon and Yanqi Zhou and Bob Iannucci and Carlee Joe-Wong}, + url = {https://mpslab-asu.github.io/publications/papers/Hu2023MLSYS.pdf, pdf}, + year = {2023}, + date = {2023-06-04}, + urldate = {2023-06-04}, + booktitle = {Proceedings of the Sixth Conference on Machine Learning and Systems (MLSys)}, + keywords = {Machine Learning Accelerator Design, Real-Time Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{Szeto2023THESIS, + title = {B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles}, + author = {Matthew Szeto}, + url = {https://mpslab-asu.github.io/publications/papers/Szeto2023THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Szeto2023THESIS.pptx, slides}, + year = {2023}, + date = {2023-05-08}, + urldate = {2023-05-08}, + school = {Arizona State University}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{Ranjbar2023DATE, + title = {Learning-Oriented Reliability for Machine Learning Improvement of Computing Systems From Transistor to Application Level}, + author = {Behnaz Ranjbar and Florian Klemme and Paul R. Genssler and Hussam Amrouch and Jinhyo Jung and Shail Dave and Hwisoo So and Kyongwoo Lee and Aviral Shrivastava and Ji-Yung Lin and Pieter Weckx and Subrat Mishra and Francky Catthoor and Dwaipayan Biswas and Akash Kumar}, + url = {https://mpslab-asu.github.io/publications/papers/Ranjbar2023DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Ranjbar2023DATE.pptx, slides}, + year = {2023}, + date = {2023-04-17}, + urldate = {2023-04-17}, + booktitle = {Proceedings of the 26th International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Efficient Embedded Computing, Machine Learning Accelerator Design, Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{ParkTIV2023, + title = {Blame-Free Motion Planning in Hybrid Traffic}, + author = {Sanggu Park and Edward Andert and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Park2023TIV.pdf, paper}, + year = {2023}, + date = {2023-04-05}, + urldate = {2023-04-05}, + journal = {IEEE Transactions on Intelligent Vehicles}, + pages = {1-10}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {article} +} + +@article{Didehban2023TDSC, + title = {Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication}, + author = {Moslem Didehban and Hwisoo So and Prudhvi Gali and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2023TDSC.pdf, paper}, + year = {2023}, + date = {2023-02-14}, + urldate = {2023-02-14}, + journal = {IEEE Transactions on Dependable and Secure Computing}, + volume = {1}, + pages = {1-16}, + abstract = {Transient faults or soft errors are considered one of the most daunting Reliability for Machine Learning challenges for microprocessors. Software solutions for soft error protection are attractive because they can provide flexible and effective error protection. For instance, nZDC [1] state-of-the-art instruction duplication error protection scheme achieves a high degree of error detection by verifying the results of memory write operations and utilizes an effective control-flow checking mechanism. However, nZDC control-flow checking mechanism is architecture-dependent and suffers from some vulnerability holes. In this work, we address these issues by substituting nZDC control-flow checking mechanism with a general (ISA-independent) scheme and propose two transformations, coarse-grained scheduling, and asymmetric control-flow signatures, for hard-to-detect control flow errors. Fault injection experiments on different hardware components of synthesizable Verilog description of an OpenRISC-based microprocessor reveal that the proposed transformation shows 85% less silent data corruptions compared to nZDC. In addition, programs protected by the proposed scheme run on average around 37% faster than nZDC-protected programs.}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@article{Shrivastava2023D&T, + title = {Report on the 2022 Embedded Systems Week (ESWEEK)}, + author = {Aviral Shrivastava and Xiaobo Sharon Hu}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2023D&T.pdf, pdf}, + year = {2023}, + date = {2023-01-23}, + urldate = {2023-01-23}, + journal = {IEEE Design & Test}, + volume = {40}, + issue = {1}, + pages = {108-111}, + abstract = {Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences [the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES); the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS); and the International Conference on Embedded Software (EMSOFT)] and a variety of symposia, hot-topic workshops, tutorials, and education classes, ESWEEK presents to the attendees a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.}, + keywords = {Cyber Physical and IoT Systems, Efficient Embedded Computing, Machine Learning Accelerator Design, Real-Time Systems, Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@mastersthesis{Ta2022THESIS, + title = {COMSAT: Modified Modulo Scheduling Techniques for Acceleration on Unknown Trip Count and Early Exit Loops}, + author = {Quoc Long Vinh Ta}, + url = {https://mpslab-asu.github.io/publications/papers/Ta2022THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Ta2022THESIS.pptx, slides }, + year = {2022}, + date = {2022-12-08}, + urldate = {2022-12-08}, + school = {Arizona State University}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{Andert2022ITSC, + title = {Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs}, + author = {Edward Andert and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Andert2022ITSC.pdf, pdf https://mpslab-asu.github.io/publications/slides/Andert2022ITSC.pptx, slides https://docs.google.com/presentation/d/1-i4m5GRfRn3lsFdo4RAhaY4qxdRgBfrX/edit?usp=sharing&ouid=101396061526471459814&rtpof=true&sd=true , slides}, + year = {2022}, + date = {2022-10-08}, + urldate = {2022-10-08}, + booktitle = {Proceedings of the IEEE 25th International Conference on Intelligent Transportation Systems (ITSC)}, + organization = {IEEE}, + keywords = {Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{Jung2022JSA, + title = {Root cause analysis of soft-error-induced failures from hardware and software perspectives}, + author = {Jinhyo Jung and Yohan Ko and Hwisoo So and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jung2022JSA.pdf, pdf }, + year = {2022}, + date = {2022-07-08}, + urldate = {2022-07-08}, + journal = {Journal of Systems Architecture (JSA)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@article{So2022TACO, + title = {EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults}, + author = {Hwisoo So and Moslem Didehban and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/So2022TACO.pdf, paper }, + year = {2022}, + date = {2022-07-05}, + urldate = {2022-07-05}, + journal = {ACM Transactions on Architecture and Code Optimization (TACO)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@workshop{Dave2022SNN, + title = {Efficient Processing of Sparse and Compact DNN Models on Hardware Accelerators: Survey and Insights}, + author = {Shail Dave and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/posters/Dave2022SNN.pdf, poster}, + year = {2022}, + date = {2022-07-01}, + urldate = {2022-07-01}, + booktitle = {In Annual Workshop on Sparsity in Neural Networks (SparseNN)}, + keywords = {GPU Computing, Machine Learning Accelerator Design}, + pubstate = {published}, + tppubtype = {workshop} +} + +@mastersthesis{Park2022Thesis, + title = {Blame-Free Motion Planning in Hybrid Traffic}, + author = {Sanggu Park}, + url = {https://mpslab-asu.github.io/publications/papers/Park2022THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Park2022THESIS.pptx, slides}, + year = {2022}, + date = {2022-05-11}, + urldate = {2022-05-11}, + school = {Arizona State University}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{Dave2022VTS, + title = {Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems}, + author = {Shail Dave and Alberto Marchisio and Muhammad Abdullah Hanif and Amira Guesmi and Aviral Shrivastava and Ihsen Alouani and Muhammad Shafique}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2022VTS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Dave2022VTS.pptx, slides}, + year = {2022}, + date = {2022-04-25}, + urldate = {2022-04-25}, + booktitle = {Proceedings of the 2022 IEEE 40th VLSI Test Symposium (VTS)}, + abstract = {The real-world use cases of Machine Learning (ML) have exploded over the past few years. However, the current computing infrastructure is insufficient to support all real-world applications and scenarios. Apart from high efficiency requirements, modern ML systems are expected to be highly reliable against hardware failures as well as secure against adversarial and IP stealing attacks. Recent developments have also highlighted various privacy concerns. Towards trustworthy ML systems, in this work we highlight different challenges faced by the embedded systems community towards enabling efficient, dependable and secure deployment of ML. To address these challenges, we present an agile design methodology to generate efficient, reliable and secure ML systems based on user-defined constraints and objectives.}, + keywords = {Efficient Embedded Computing, Machine Learning Accelerator Design, Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@bachelorthesis{Cunningham2022THESIS, + title = {Making a Real-Time Operating System for the Raspberry Pi 2B}, + author = {Christian Cunningham}, + url = {https://mpslab-asu.github.io/publications/papers/Cunningham2022THESIS.pdf, thesis https://mpslab-asu.github.io/publications/papers/Cunningham2022THESIS.pptx, slides https://github.com/MPSLab-ASU/Jobbed, Code}, + year = {2022}, + date = {2022-04-09}, + urldate = {2022-04-09}, + school = {Arizona State University}, + keywords = {Real-Time Systems}, + pubstate = {published}, + tppubtype = {bachelorthesis} +} + +@inproceedings{Balasubramanian2022DATE, + title = {PathSeeker: A Fast Mapping Algorithm for CGRAs}, + author = {Mahesh Balasubramanian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2022DATE.pdf, pdf https://mpslab-asu.github.io/publications/slides/Balasubramanian2022DATE.pptx, slides}, + year = {2022}, + date = {2022-03-16}, + urldate = {2022-03-16}, + booktitle = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)}, + journal = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{Huang2022DATE, + title = {Compatibility Checking for Autonomous Lane-Changing Assistance Systems}, + author = {Po-Yu Huang and Kai-Wei Liu and Zong-Lun Li and Sanggu Park and Edward Andert and Chung-Wei Lin and Aviral Shrivastava }, + url = {https://mpslab-asu.github.io/publications/papers/Huang2022DATE.pdf, pdf https://mpslab-asu.github.io/publications/slides/Huang2022DATE.pptx, slides https://mpslab-asu.github.io/publications/slides/Huang2022DATE.pdf, poster}, + year = {2022}, + date = {2022-03-16}, + urldate = {2022-03-16}, + booktitle = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@patent{Khayatian2022PATENT, + title = {Systems and methods for intersection management of connected autonomous vehicles}, + author = {Mohammad Khayatian and Aviral Shrivastava and Mohammadreza Mehrabian}, + url = {https://patents.google.com/patent/US11269330B2, Google Patents}, + year = {2022}, + date = {2022-03-08}, + urldate = {2022-03-08}, + howpublished = {https://patents.google.com/patent/US11269330B2/}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {patent} +} + +@workshop{Dave2022LATTE, + title = {Design Space Description Language for Automated and Comprehensive Exploration of Next-Gen Hardware Accelerators}, + author = {Shail Dave and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2022LATTE.pdf, pdf https://mpslab-asu.github.io/publications/slides/Dave2022LATTE.pptx, slides https://capra.cs.cornell.edu/latte22/, workshop https://youtu.be/Z5jZ2dbE0To, talk}, + year = {2022}, + date = {2022-03-01}, + urldate = {2022-03-01}, + booktitle = {Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE)}, + abstract = {Exploration of accelerators typically involves an architectural template specified in architecture description language (ADL). It can limit the design space that can be explored, reusability and automation of system stack, explainability, and exploration efficiency. We envision Design Space Description Language (DSDL) for comprehensive, reusable, explainable, and agile DSE. We describe how its flow graph abstraction enables comprehensive DSE of modular designs, with architectural components organized in various hierarchies and groups. We discuss automation of characterizing, simulating, and programming new architectures. Lastly, we describe how DSDL flow graphs facilitate bottleneck analysis, yielding explainability of costs and selected designs and super-fast exploration.}, + note = {co-located with ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).}, + keywords = {Coarse-Grained Reconfigurable Arrays, Machine Learning Accelerator Design}, + pubstate = {published}, + tppubtype = {workshop} +} + +@article{Khayatian2022TCPS, + title = {Plan B - Design Methodology for Cyber-Physical Systems Robust to Timing Failure}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Edward Andert and Reese Grimsley and Kyle Liang and Yi Hu and Ian McCormack and Carlee Joe-Wong and Jonathan Aldrich and Bob Iannucci and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2022TCPS.pdf, pdf}, + year = {2022}, + date = {2022-01-31}, + urldate = {2022-01-31}, + journal = {ACM Transactions on Cyber Physical Systems (TCPS)}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {article} +} + +@article{So2021ELECTRONICS, + title = {Revisiting Symptom-Based Fault Tolerant Techniques against Soft Errors}, + author = {Hwisoo So and Moslem Didehban and Yohan Ko and Reiley Jeyapaul and Jongho Kim and Youngbin Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/So2021ELECTRONICS.pdf, pdf}, + year = {2021}, + date = {2021-12-04}, + urldate = {2021-12-04}, + journal = {MDPI Electronics}, + volume = {10}, + number = {23}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@phdthesis{Balasubramanian2021THESIS, + title = {Compiler Design for Accelerating Applications on Coarse-Grained Reconfigurable Architectures}, + author = {Mahesh Balasubramanian }, + url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2021THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Balasubramanian2021THESIS.pptx, slides}, + year = {2021}, + date = {2021-10-25}, + urldate = {2021-12-13}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@inproceedings{Ko2021ICCD, + title = {Comprehensive Failure Analysis against Soft Errors from Hardware and Software Perspectives}, + author = {Yohan Ko and Jin Hyo Jung and Hwisoo So and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Ko2021ICCD.pdf, paper https://mpslab-asu.github.io/publications/slides/Ko2021ICCD.pptx, slides}, + year = {2021}, + date = {2021-10-24}, + urldate = {2021-10-24}, + booktitle = {Proceedings of the 2021 IEEE International Conference on Computer Design (ICCD)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{Dave2021PIEEE, + title = {Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights}, + author = {Shail Dave and Riyadh Baghdadi and Tony Nowatzki and Sasikanth Avancha and Aviral Shrivastava and Baoxin Li}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2021PIEEE.pdf, paper}, + year = {2021}, + date = {2021-10-01}, + urldate = {2021-10-01}, + journal = {Proceedings of the IEEE (PIEEE)}, + note = {arXiv: 2007.00864}, + keywords = {Coarse-Grained Reconfigurable Arrays, Machine Learning Accelerator Design, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@phdthesis{Mehrabian2021THESIS, + title = {A Methodology and Formalism to Monitor Timing Specifications Of Cyber-Physical Systems}, + author = {Mohammadreza Mehrabian}, + url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2021THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Mehrabian2021THESIS.pptx, slides}, + year = {2021}, + date = {2021-07-06}, + urldate = {2021-07-06}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@phdthesis{Khayatian2021PhDThesis, + title = {Safe and Robust Cooperative Algorithms for Connected Autonomous Vehicles}, + author = {Mohammad Khayatian}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2021Thesis.pdf, pdf https://mpslab-asu.github.io/publications/slides/Khayatian2021Thesis.pptx, slides}, + year = {2021}, + date = {2021-06-23}, + urldate = {2021-06-23}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@inproceedings{KhayatianICCPS2021, + title = {Cooperative Driving of Connected Autonomous Vehicles Using Responsibility-Sensitive Safety (RSS) Rules}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Harshith Allamsetti and Kai Wei and Po Yu and Chung-Wei Lin and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2021ICCPS.pdf, paper https://mpslab-asu.github.io/publications/slides/Khayatian2021ICCPS.pptx, slide}, + year = {2021}, + date = {2021-04-10}, + urldate = {2021-04-10}, + booktitle = {Proceedings of the 12th ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS)}, + journal = {ICCPS}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{SoDATE2021, + title = {CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults}, + author = {Hwisoo So and Moslem Didehban and Jinhyo Jung and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/So2021DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/So2021DATE.pptx, slides}, + year = {2021}, + date = {2021-02-01}, + urldate = {2021-02-01}, + booktitle = {Proceedings of the 24th International Conference on Design Automation and Test in Europe (DATE)}, + journal = {Proceedings of the 24th International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{SinghTACO2020, + title = {SPX64: A Scratchpad Memory for General-Purpose Microprocessors}, + author = {Abhishek Singh and Shail Dave and PanteA Zardoshti and Robert Brotzman and Chao Zhang and Xiaochen Guo and Aviral Shrivastava and Gang Tan and Michael Spear}, + url = {https://mpslab-asu.github.io/publications/papers/Singh2020TACO.pdf, paper}, + year = {2021}, + date = {2021-01-18}, + journal = {ACM Transactions on Architecture and Code Optimization (TACO)}, + keywords = {Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{KhayatianITSC2020, + title = {R^{2}IM -- Robust and Resilient Intersection Management of Connected Autonomous Vehicles}, + author = {Mohammad Khayatian and Rachel Dedinsky and Sarthake Choudhary and Mohammadreza Mehrabian and Aviral Shrivastava}, + url = {https://MPSLab-ASU.github.io/publications/papers/Khayatian2020ITSC.pdf, paper https://MPSLab-ASU.github.io/publications/slides/Khayatian2020ITSC.pptx, slides}, + year = {2020}, + date = {2020-09-20}, + booktitle = {2020 IEEE International Conference on Intelligent Transportation System Conference (ITSC)}, + organization = {IEEE}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{Balasubramanian2020TCAD, + title = {CRIMSON: Compute-intensive loop acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs}, + author = {Mahesh Balasubramanian and Aviral Shrivastava }, + url = {https://MPSLab-ASU.github.io/publications/papers/Balasubramanian2020TCAD.pdf, paper}, + year = {2020}, + date = {2020-09-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {article} +} + +@article{KhayatianTCPS2020, + title = {A Survey on Intersection Management of Connected Autonomous Vehicles}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Edward Andert and Rachel Dedinsky and Sarthake Choudhary and Yingyan Lou and Aviral Shrivastava}, + url = {https://MPSLab-ASU.github.io/publications/papers/Khayatian2020TCPS.pdf, paper}, + year = {2020}, + date = {2020-07-20}, + journal = {ACM Transactions on Cyber-Physical Systems}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {article} +} + +@mastersthesis{Allamsetti2020thesis, + title = {Cooperative Driving of Connected Autonomous Vehicles Using Responsibility Sensitive Safety Rules}, + author = {Harshith Allamsetti}, + url = {https://MPSLab-ASU.github.io/publications/papers/Allamsetti2020THESIS.pdf, paper https://MPSLab-ASU.github.io/publications/slides/Allamsetti2020THESIS.pptx, slides}, + year = {2020}, + date = {2020-06-25}, + urldate = {2020-06-25}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{BalasubramanianI2020IPDPS, + title = {Scaling of Union of Intersections for Inference of Granger Causal Networks from Observational Data}, + author = {Mahesh Balasubramanian and Trevor Ruiz and Brandon Cook and Mr Prabhat and Sharmodeep Bhattacharyya and Aviral Shrivastava and Kristofer Bouchard}, + url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2020IPDPS.pdf, paper https://mpslab-asu.github.io/publications/slides/Balasubramanian2020IPDPS.pptx, slides}, + year = {2020}, + date = {2020-05-01}, + booktitle = {Proceeding of the 34th IEEE International Parallel & Distributed Processing Symposium (IPDPS)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{DaveICASSP2020, + title = {dMazeRunner: Optimizing Convolutions on Dataflow Accelerators}, + author = {Shail Dave and Aviral Shrivastava and Youngbin Kim and Sasikanth Avancha and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2020ICASSP.pdf, paper https://mpslab-asu.github.io/publications/slides/Dave2020ICASSP.pptx, slides https://github.com/MPSLab-ASU/dMazeRunner, code https://www.youtube.com/watch?v=21F79Taelts, video}, + year = {2020}, + date = {2020-04-09}, + urldate = {2020-04-09}, + booktitle = {ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)}, + note = {Invited}, + keywords = {Machine Learning Accelerator Design}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@workshop{DedinskyASD2019, + title = {A Dependable Detection Mechanism for Intersection Management of Connected Autonomous Vehicles}, + author = {Rachel Dedinsky and Mohammad Khayatian and Mohammadreza Mehrabian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dedinsky2019ASD.pdf, pdf http://asd.userweb.mwn.de/Archives/2019/index.html, workshop}, + year = {2019}, + date = {2019-03-28}, + urldate = {2019-03-28}, + booktitle = {Workshop on Autonomous Systems Design (ASD 2019)}, + note = {co-located with 22nd International Conference on Design Automation and Test in Europe (DATE).}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {workshop} +} + +@mastersthesis{DedinskyMSThesis2019, + title = {R2IM: Reliable and Robust Intersection Manager Robust to Rogue Vehicles}, + author = {Rachel Dedinsky}, + url = {https://mpslab-asu.github.io/publications/papers/Dedinsky2019THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Dedinsky2019THESIS.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + school = {Arizona State University}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{LinVLSID2019, + title = {Efficient Heap Data Management on Software Managed Manycore Architectures}, + author = {Jinn-Pean Lin and Jing Lu and Jian Cai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lin2019VLSID.pdf, paper https://mpslab-asu.github.io/publications/slides/Lin2019VLSID.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KimVLSID2019, + title = {WCET-Aware Stack Frame Management of Embedded Systems using Scratchpad Memories}, + author = {Yooseong Kim and Mohammad Khayatian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2019VLSID.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2019VLSID.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)}, + keywords = {Cyber Physical and IoT Systems, Power, Temperature and Variation Aware Computing, Real-Time Systems, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{SoDATE2019, + title = {A software-level Redundant MultiThreading for Soft/Hard Error Detection and Recovery}, + author = {Hwisoo So and Moslem Didehban and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/So2019DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/So2019DATE.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of the 22nd International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{DaveTECS2019, + title = {DMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators}, + author = {Shail Dave and Youngbin Kim and Sasikanth Avancha and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2019TECS.pdf, paper https://mpslab-asu.github.io/publications/slides/Dave2019TECS.pptx, slides https://mpslab-asu.github.io/publications/posters/Dave2019TECS.pdf, poster https://github.com/MPSLab-ASU/dMazeRunner, code}, + year = {2019}, + date = {2019-01-01}, + urldate = {2019-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + volume = {18}, + number = {5s}, + note = {Special Issue on ESWEEK 2019 - Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)}, + keywords = {Machine Learning Accelerator Design}, + pubstate = {published}, + tppubtype = {article} +} + +@article{RisheekesanTECS2019, + title = {Control Flow Checking or Not? (for Soft Errors)}, + author = {Abhishek Risheekesan and Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Risheekesan2019TECS.pdf, paper}, + year = {2019}, + date = {2019-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@phdthesis{Lu2019PhDThesis, + title = {Application-aware Performance Optimization for Software Managed Manycore Architectures}, + author = {Jing Lu}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2019THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Lu2019THESIS.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + school = {Arizona State University}, + keywords = {Power, Temperature and Variation Aware Computing, Software Branch Hinting, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@inproceedings{ShrivastavaDAC2019, + title = {Software Approaches for In-time Resilience}, + author = {Aviral Shrivastava and Moslem Didehban}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2019DAC.pdf, paper}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of the 56th Annual Design Automation Conference (DAC)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{KhayatianTCPS2019, + title = {Crossroads+: A Time-Aware Approach for Intersection Management of Connected Autonomous Vehicles}, + author = {Mohammad Khayatian and Yingyan Lou and Mohammadreza Mehrabian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2019TCPS.pdf, paper}, + year = {2019}, + date = {2019-01-01}, + journal = {ACM Transactions on Cyber-Physical Systems (TCPS)}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{Hekmatnejad2019MEMOCODE, + title = {Encoding and Monitoring Responsibility Sensitive Safety Rules for Automated Vehicles in Signal Temporal Logic}, + author = {Mohammad Hekmatnejad and Shakiba Yaghoubi and Adel Dokhanchi and Heni Ben Amor and Aviral Shrivastava and Lina Karam and Georgios Fainekos}, + url = {https://mpslab-asu.github.io/publications/papers/Hekmatnejad2019MEMOCODE.pdf, paper https://mpslab-asu.github.io/publications/slides/Hekmatnejad2019MEMOCODE.pdf, slides}, + year = {2019}, + date = {2019-01-01}, + urldate = {2019-01-01}, + booktitle = {Proceedings of the 2019 17th ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KimICCD2019, + title = {Static Function Prefetching for Efficient Code Management on Scratchpad Memory}, + author = {Youngbin Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2019ICCD.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2019ICCD.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of the 2019 IEEE International Conference on Computer Design (ICCD)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@workshop{DaveDATEDEMO2018, + title = {CCF: A CGRA Compilation Framework}, + author = {Shail Dave and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2018DATEDEMO.pdf, pdf https://youtu.be/iGV1lHsjy4w, talk https://github.com/MPSLab-ASU/CCF, code}, + year = {2018}, + date = {2018-03-21}, + booktitle = {University Booth at the 21st International Conference on Design Automation and Test in Europe (DATE) }, + keywords = {}, + pubstate = {published}, + tppubtype = {workshop} +} + +@inproceedings{BalasubramanianDATE2018, + title = {LASER: A Hardware/Software Approach to Accelerate Complicated Loops on CGRAs}, + author = {Mahesh Balasubramanian and Shail Dave and Aviral Shrivastava and Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2018DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Balasubramanian2018DATE.pptx, slides}, + year = {2018}, + date = {2018-01-01}, + booktitle = {Proceedings of the 21st International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{DidehbanTR2018, + title = {A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments}, + author = {Moslem Didehban and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2018TR.pdf, paper}, + year = {2018}, + date = {2018-01-01}, + journal = {IEEE Transactions on Reliability for Machine Learning}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{KhayatianRTSS2018, + title = {RIM: Robust Intersection Management for Connected Autonomous Vehicles}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2018RTSS.pdf, paper https://mpslab-asu.github.io/publications/slides/Khayatian2018RTSS.pptx, slides}, + year = {2018}, + date = {2018-01-01}, + booktitle = {Proceedings of the 39th IEEE Real-Time Systems Symposium (RTSS)}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{MehrabianDAC2018, + title = {TMA: An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems}, + author = {Mohammadreza Mehrabian and Mohammad Khayatian and Ahmed Moussa and Aviral Shrivastava and Ya-Shian Li and Patricia Derler and Edward Griffor and Hugo A Andrade and Marc Weiss and John Eidson}, + url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2018DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Mehrabian2018DAC.pptx, slides}, + year = {2018}, + date = {2018-01-01}, + booktitle = {Proceedings of the 55th Annual Design Automation Conference (DAC)}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@phdthesis{Didehban2018PhDThesis, + title = {Software Techniques For Dependable Execution}, + author = {Moslem Didehban}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2018THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Didehban2018THESIS.pptx, slides}, + year = {2018}, + date = {2018-01-01}, + school = {Arizona State University}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@inproceedings{DaveDAC2018, + title = {RAMP: Resource-Aware Mapping for CGRAs}, + author = {Shail Dave and Mahesh Balasubramanian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2018DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Dave2018DAC.pptx, slides https://mpslab-asu.github.io/publications/posters/Dave2018DAC.pdf, poster }, + year = {2018}, + date = {2018-01-01}, + urldate = {2018-01-01}, + booktitle = {Proceedings of the 55th Annual Design Automation Conference (DAC)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaDAC2017, + title = {A Testbed to Verify the Timing Behavior of Cyber-Physical Systems}, + author = {Aviral Shrivastava and Mohammadreza Mehrabian and Mohammad Khayatian and Patricia Derler and Hugo A Andrade and Kevin Stanton and Ya-Shian Li-Baboud and Edward Griffor and Marc Weiss and John Eidson}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2017DAC.pdf, paper }, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of The 54th Annual Design Automation Conference (DAC)}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{DidehbanICCAD2017, + title = {NEMESIS: A Software Approach for Computing in Presence of Soft Errors}, + author = {Moslem Didehban and Aviral Shrivastava and Dheeraj Lokam}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2017ICCAD.pdf, paper https://mpslab-asu.github.io/publications/slides/Didehban2017ICCAD.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{CaiDATE2017, + title = {Reducing Code Management Overhead in Software-Managed Multicores}, + author = {Jian Cai and Yooseong Kim and Youngbin Kim and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Cai2017DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Cai2017DATE.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of the 2017 International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{AndertMSTHESIS2017, + title = {Crossroads - A Time-Sensitive Autonomous Intersection Management Technique}, + author = {Edward Andert}, + url = {https://www.youtube.com/watch?v=pX5TjijLP9o&feature=youtu.be, video https://mpslab-asu.github.io/publications/papers/Andert2017THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Andert2017THESIS.pptx, slides }, + year = {2017}, + date = {2017-01-01}, + school = {Arizona State University}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{DidehbanDAC2017, + title = {An Integrated Safe and Fast Recovery Scheme from Soft Errors}, + author = {Moslem Didehban and Dheeraj Lokam and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2017DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Didehban2017DAC.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of The 54th Annual Design Automation Conference (DAC)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{AndertDAC2017, + title = {Crossroads - A Time-Sensitive Autonomous Intersection Management Technique}, + author = {Edward Andert and Mohammad Khayatian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Andert2017DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Andert2017DAC.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of The 54th Annual Design Automation Conference (DAC)}, + note = {Best Paper Award Candidate}, + keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{KoTECS2017, + title = {Protecting Caches from Soft Errors: A Microarchitect's Perspective}, + author = {Yohan Ko and Reiley Jeyapaul and Youngbin Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Ko2017TECS.pdf, paper }, + year = {2017}, + date = {2017-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + volume = {16}, + number = {4}, + pages = {93:1-93:28}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@phdthesis{KimPHDTHESIS2017, + title = {WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems}, + author = {Yooseong Kim}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2017THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2017THESIS.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + school = {Arizona State University}, + note = {Outstanding Computer Science Graduating PhD Student of the Year Award}, + keywords = {Cyber Physical and IoT Systems, Power, Temperature and Variation Aware Computing, Real-Time Systems, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@article{KimTECS2017, + title = {WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory}, + author = {Yooseong Kim and David Broman and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2017TECS.pdf, paper}, + year = {2017}, + date = {2017-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + volume = {16}, + number = {4}, + pages = {112:1-112:26}, + keywords = {Cyber Physical and IoT Systems, Power, Temperature and Variation Aware Computing, Real-Time Systems, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {article} +} + +@article{MehrabianTECS2017, + title = {Timestamp Temporal Logic (TTL) for Time Testing of Cyber-Physical Systems}, + author = {Mohammadreza Mehrabian and Mohammad Khayatian and Aviral Shrivastava and John Eidson and Patricia Derler and Hugo A Andrade and Ya-Shian Li-Baboud and Edward Griffor and Marc Weiss and Kevin Stanton}, + url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2017TECS.pdf, paper https://mpslab-asu.github.io/publications/slides/Mehrabian2017TECS.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + volume = {16}, + number = {169}, + series = {5s}, + note = {Special Issue on ESWEEK 2017 - Proceedings of the International Conference on Embedded Software (EMSOFT)}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {article} +} + +@mastersthesis{LinMSThesis2017, + title = {Optimizing Heap Data Management on Software Managed Many-core Architectures}, + author = {Jinn-Pean Lin}, + url = {https://mpslab-asu.github.io/publications/papers/Lin2017THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Lin2017THESIS.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + school = {Arizona State University}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@phdthesis{CaiPHDTHESIS2017, + title = {Scratchpad Management in Software Managed Manycore Architectures}, + author = {Jian Cai}, + url = {https://mpslab-asu.github.io/publications/papers/Cai2017THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Cai2017THESIS.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + school = {Arizona State University}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@inproceedings{CaiASAP2016, + title = {Efficient Pointer Management of Stack Data for Software Managed Multicores}, + author = {Jian Cai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Cai2016ASAP.pdf, paper https://mpslab-asu.github.io/publications/slides/Cai2016ASAP.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{ShrivastavaIET2016, + title = {Automatic Management of Software Programmable Memories in Manycore Architectures}, + author = {Aviral Shrivastava and Nikil Dutt and Jian Cai and Majid Shoushtari and Bryan Donyanavard and Hossein Tajik}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2016IET.pdf, paper }, + year = {2016}, + date = {2016-01-01}, + journal = {IET Computers & Digital Techniques}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{DidehbanDAC2016, + title = {NZDC: A Compiler technique for near Zero Silent data Corruption}, + author = {Moslem Didehban and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2016DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Didehban2016DAC.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of The 53rd Annual Design Automation Conference (DAC)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{LokamMSTHESIS2016, + title = {InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes}, + author = {Dheeraj Lokam}, + url = {https://mpslab-asu.github.io/publications/papers/Lokam2016THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Lokam2016THESIS.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + school = {Arizona State University}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@article{JeyapaulVLSI2016, + title = {Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability for Machine Learning}, + author = {Reiley Jeyapaul and Roberto Flores and Alfonso Avila and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2016TVLSI.pdf, paper}, + year = {2016}, + date = {2016-01-01}, + journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{ShrivastavaCODESISSS2016, + title = {Time in Cyber-Physical Systems}, + author = {Aviral Shrivastava and Patricia Derler and Ya-Shian Li and Kevin Stanton and Mohammad Khayatian and Hugo A Andrade and Marc Weiss and John Eidson and Sundeep Chandhoke}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2016CODES.pdf, paper }, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of the international symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS)}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KimICCAD2016, + title = {Splitting Functions in Code Management on Scratchpad Memories}, + author = {Youngbin Kim and Jian Cai and Yooseong Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2016ICCAD.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2016ICCAD.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{TanikellaASAP2016, + title = {GemV: A Validated Toolset for the Early Exploration of System Reliability for Machine Learning}, + author = {Srinivas Karthik Tanikella and Yohan Ko and Reiley Jeyapaul and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Tanikella2016ASAP.pdf, paper https://mpslab-asu.github.io/publications/slides/Tanikella2016ASAP.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{TanikellaMSTHESIS2016, + title = {GemV: A Validated Micro-architecture Vulnerability Estimation Tool}, + author = {Srinivas Karthik Tanikella}, + url = {https://mpslab-asu.github.io/publications/papers/Tanikella2016THESIS.pdf, paper }, + year = {2016}, + date = {2016-01-01}, + school = {Arizona State University}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{CaiVLSID2016, + title = {Software Coherence Management on Non-Coherent Cache Multi-cores}, + author = {Jian Cai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Cai2016VLSID.pdf, paper https://mpslab-asu.github.io/publications/slides/Cai2016VLSID.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of 29th International Conference on VLSI Design (VLSID)}, + note = {(Best Student Paper Award)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@patent{BaiPATENT2015, + title = {Stack data management for software managed multi-core processors}, + author = {Ke Bai and Aviral Shrivastava and Jing Lu}, + year = {2015}, + date = {2015-01-01}, + howpublished = {http://www.google.com/patents/US9015689}, + note = {Patent}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {patent} +} + +@inproceedings{AndradeRECONFIG2015, + title = {Towards a Reconfigurable Distributed Testbed to Enable Advanced Research and Development of Timing and Synchronization in Cyber-Physical Systems}, + author = {Hugo A Andrade and Patricia Derler and John Eidson and Ya-Shian Li-Baboud and Aviral Shrivastava and Kevin Stanton and Marc Weiss}, + url = {https://mpslab-asu.github.io/publications/papers/Andrade2015RECONFIG.pdf, paper }, + year = {2015}, + date = {2015-01-01}, + booktitle = {International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, + keywords = {Cyber Physical and IoT Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{RuCASES2015, + title = {Optimization of Multi-Channel BCH Error Decoding for Common Cases}, + author = {Russell Dill and Aviral Shrivastava and Hyunok Oh}, + url = {https://mpslab-asu.github.io/publications/papers/Dill2015CASES.pdf, paper https://mpslab-asu.github.io/publications/slides/Dill2015CASES.pptx, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {In Proceedings of the 2014 international conference on Compilers, architecture, and synthesis for embedded systems (CASES)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{HokeunRTAS2015, + title = {A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems}, + author = {Hokeun Kim and David Broman and Edward A Lee and Michael Zimmer and Aviral Shrivastava and Junkwang Oh}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2015RTAS.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2015RTAS.pdf, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {Real-Time and Embedded Technology and Applications Symposium (RTAS)}, + keywords = {Cyber Physical and IoT Systems, Real-Time Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{DillMASTERTHESIS2015, + title = {Optimization of Multi-Channel BCH Error Decoding for Common Cases}, + author = {Russell Dill}, + url = {https://mpslab-asu.github.io/publications/papers/Dill2015THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Dill2015THESIS.pptx, slides}, + year = {2015}, + date = {2015-01-01}, + school = {Arizona State University}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@article{PagerTECS2015, + title = {A Software Scheme for Multithreading on CGRAs}, + author = {Jared Pager and Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Pager2015TECS.pdf, paper}, + year = {2015}, + date = {2015-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{RadhikaDATE2015, + title = {Path Selection Based Acceleration of Conditionals in CGRAs}, + author = {Shri Hari Rajendran Radhika and Aviral Shrivastava and Mahdi Hamzeh}, + url = {https://mpslab-asu.github.io/publications/papers/Radhika2015DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Radhika2015DATE.slides, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {Proceedings of the 2015 International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{RawatDATE2015, + title = {Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures}, + author = {Tushar Rawat and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Rawat2015DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Rawat2015DATE.pptx, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {Proceedings of the 2015 International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{LuTECS2015, + title = {Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores}, + author = {Jing Lu and Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2015TECS.pdf, paper}, + year = {2015}, + date = {2015-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{YohanDAC2015, + title = {Guidelines to Design Parity Protected Write-back L1 Data Cache}, + author = {Yohan Ko and Reiley Jeyapaul and Youngbin Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Ko2015DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Ko2015DAC.pptx, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {Proceedings of The 52nd Annual Design Automation Conference (DAC)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaCASA2014, + title = {Control Flow Checking or Not?(for Soft Errors)}, + author = {Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2014CASA.pdf, paper}, + year = {2014}, + date = {2014-05-01}, + booktitle = {2014 Conference on Computer Animation and Social Agents}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@phdthesis{BaiPHDTHESIS2014, + title = {Compiler and Runtime for Memory Management on Software Managed Manycore Processors}, + author = {Ke Bai}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2014THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Bai2014THESIS.pptx, slides}, + year = {2014}, + date = {2014-02-01}, + urldate = {2014-02-01}, + school = {Arizona State University}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@article{JeyapaulTPDS2013, + title = {UnSync-CMP: Multicore CMP Architecture for Energy Efficient Soft Error Reliability for Machine Learning}, + author = {Reiley Jeyapaul and Abhishek Risheekesan and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2014TPDS.pdf, paper}, + year = {2014}, + date = {2014-01-01}, + journal = {Transactions on Parallel and Distributed Systems}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{KimRTAS2014, + title = {WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores}, + author = {Yooseong Kim and David Broman and Jian Cai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2014RTAS.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2014RTAS.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + booktitle = {Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)}, + keywords = {Cyber Physical and IoT Systems, Power, Temperature and Variation Aware Computing, Real-Time Systems, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{HoltonCASES2014, + title = {Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM) Architectures}, + author = {Bryce Holton and Ke Bai and Aviral Shrivastava and Harini Ramaprasad}, + url = {https://mpslab-asu.github.io/publications/papers/Holton2014CASES.pdf, paper https://mpslab-asu.github.io/publications/slides/Holton2014CASES.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + booktitle = {Proceedings of the 2014 international conference on Compilers, architecture, and synthesis for embedded systems (CASES)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaDAC2014, + title = {Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors}, + author = {Aviral Shrivastava and Abhishek Risheekesan and Reiley Jeyapaul and Carole-Jean Wu}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2014DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Shrivastava2014DAC.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + booktitle = {Proceedings of the The 51st Annual Design Automation Conference (DAC)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{HamzehDAC2014, + title = {Branch-Aware Loop Mapping on CGRAs}, + author = {Mahdi Hamzeh and Aviral Shrivastava and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Hamzeh2014DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Hamzeh2014DAC.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + booktitle = {Proceedings of the The 51st Annual Design Automation Conference on (DAC), 2014}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{RawatMASTERTHESIS2014, + title = {Enabling Multithreaded Applications on Hybrid Shared Memory Many-core Architectures}, + author = {Tushar Rawat}, + url = {https://mpslab-asu.github.io/publications/papers/Rawat2014THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Rawat2014THESIS.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + school = {Arizona State University}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@mastersthesis{RadhikaMASTERTHESIS2014, + title = {Path Selection Based Branching for Coarse Grained Reconfigurable Arrays}, + author = {Shri Hari Rajendran Radhika}, + url = {https://mpslab-asu.github.io/publications/papers/Radhika2014THESIS.pdf, paper}, + year = {2014}, + date = {2014-01-01}, + school = {Arizona State University}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@mastersthesis{SalujaMASTERTHESIS2014, + title = {Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective}, + author = {Dipal Saluja}, + url = {https://mpslab-asu.github.io/publications/papers/Saluja2014THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Saluja2014THESIS.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + school = {Arizona State University}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@mastersthesis{HoltonMASTERTHESIS2014, + title = {Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM)}, + author = {Bryce Holton}, + url = {https://mpslab-asu.github.io/publications/papers/Holton2014THESIS.pdf, paper}, + year = {2014}, + date = {2014-01-01}, + school = {Arizona State University}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@article{LeeTECS2013, + title = {Software-Based Register File Vulnerability Reduction for Embedded Processors}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2013TECS.pdf, paper}, + year = {2013}, + date = {2013-11-01}, + journal = {ACM Transactions on Embedded Computing Systems}, + volume = {13}, + number = {1}, + pages = {38:1-38:20}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@article{JeyapaulTODAES2013, + title = {Enabling Energy Efficient Reliability for Machine Learning in Embedded Systems Through Smart Cache Cleaning}, + author = {Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2013TODAES.pdf, paper}, + year = {2013}, + date = {2013-10-01}, + journal = {Transactions on Design Automation of Electronic Systems}, + volume = {18}, + number = {4}, + pages = {53:1-53:25}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@article{KimTECS2013, + title = {Memory Performance Estimation of CUDA Programs}, + author = {Yooseong Kim and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2013TECS.pdf, paper}, + year = {2013}, + date = {2013-09-01}, + journal = {ACM Transactions on Embedded Computing Systems}, + volume = {13}, + number = {21}, + pages = {21:1-21:22}, + keywords = {GPU Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@article{BaiTECS2013, + title = {A Software-Only Scheme for Managing Heap Data on Limited Local Memory (LLM) Multicore Processors}, + author = {Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2013TECS.pdf, paper}, + year = {2013}, + date = {2013-08-01}, + journal = {ACM TECS: ACM Transactions on Embedded Computing Systems}, + volume = {13}, + number = {1}, + pages = {5:1-5:18}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {article} +} + +@mastersthesis{RhisheekesanMASTERTHESIS2013, + title = {Quantitative Evaluation of Control-flow based Soft Error Protection Mechanisms}, + author = {Abhishek Risheekesan}, + url = {https://mpslab-asu.github.io/publications/papers/Risheekesan2013THESIS.pdf, paper}, + year = {2013}, + date = {2013-03-01}, + school = {Arizona State University}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{BaiDATE2013, + title = {Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures}, + author = {Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2013DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Bai2013DATE.pptx, slides}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the 2013 International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{LuDAC2013, + title = {SSDM: Smart Stack Data Management for Software Managed Multicores (SMMs)}, + author = {Jing Lu and Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2013DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Lu2013DAC.pptx, slides}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the 50th Design Automation Conference (DAC)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{BaiCODESISSS2013, + title = {CMSM: An Efficient and Effective Code Management for Software Managed Multicores}, + author = {Ke Bai and Jing Lu and Aviral Shrivastava and Bryce Holton}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2013CODES.pdf, paper https://mpslab-asu.github.io/publications/slides/Bai2013CODES.pptx, slides}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the international symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{MahdiDAC2013, + title = {REGIMap: Register-aware Application Mapping on Coarse-grained Reconfigurable Architectures (CGRAs)}, + author = {Mahdi Hamzeh and Aviral Shrivastava and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Hamzeh2013DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Hamzeh2013DAC.pptx, slides}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the 50th Annual Design Automation Conference (DAC)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{BromanESLSYN2013, + title = {Precision Timed Infrastructure: Design Challenges}, + author = {David Broman and Michael Zimmer and Yooseong Kim and Hokeun Kim and Jian Cai and Aviral Shrivastava and Stephen A Edwards and Edward A Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Broman2013ESLSYN.pdf, paper}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the Electronic System Level Synthesis Conference (ESLsyn 2013)}, + keywords = {Cyber Physical and IoT Systems, Real-Time Systems}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{LeeVLSID2013, + title = {Power-Efficient Protection from Soft Errors}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2013VLSID.pdf, paper}, + year = {2013}, + date = {2013-01-01}, + booktitle = {2013 26th International Conference on VLSI Design (VLSID 2013)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{HongTVLSI2012, + title = {Return Data Interleaving for Multi-channel Embedded CMP Systems}, + author = {Fei Hong and Aviral Shrivastava and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Hong2012TVLSI.pdf}, + year = {2012}, + date = {2012-07-01}, + journal = {IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits}, + volume = {20}, + number = {7}, + pages = {1351-1354}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@phdthesis{JeyapaulPHDTHESIS2012, + title = {Smart Compilers for Reliable and Power-efficient Embedded Computing}, + author = {Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2012THESIS.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2012THESIS.pptx}, + year = {2012}, + date = {2012-05-01}, + school = {Arizona State University}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@article{LeeTECS2012, + title = {PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2012TECS.pdf}, + year = {2012}, + date = {2012-01-01}, + journal = {ACM TECS: ACM Transactions on Embedded Computing Systems}, + volume = {11}, + number = {2}, + pages = {26:1-26:27}, + keywords = {Power, Temperature and Variation Aware Computing, Processor Idle Cycle Aggregation}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{MahdiDAC2012, + title = {EPIMap: Using Epimorphism to Map Applications on CGRAs}, + author = {Mahdi Hamzeh and Aviral Shrivastava and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Hamzeh2012DAC.pdf https://mpslab-asu.github.io/publications/slides/Hamzeh2012DAC.pptx}, + year = {2012}, + date = {2012-01-01}, + booktitle = {Proceedings of the 49th Design Automation Conference (DAC)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{DiMASTERTHESIS2012, + title = {STL on Limited Local Memory (LLM) Multi-core Processors}, + author = {Di Lu}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2012THESIS.pdf https://mpslab-asu.github.io/publications/slides/Lu2012THESIS.pptx}, + year = {2012}, + date = {2012-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{LeeCODESISSS2012, + title = {Soft Errors: The Hardware-Software Interface}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Reiley Jeyapaul}, + year = {2012}, + date = {2012-01-01}, + booktitle = {Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis}, + pages = {577--578}, + booktitle = {ACM}, + address = {New York, NY, USA}, + series = {CODES+ISSS '12}, + crossref = {978-1-4503-1426-8}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{PiotrVLSI2012, + title = {Design of an RNS Reverse Converter for a New Five-Moduli Special Set}, + author = {Piotr Patronik and Krzysztof Berezowski and Janusz Biernat and Stanislaw J Piestrak and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Patronik2014GLSVLSI.pdf}, + year = {2012}, + date = {2012-01-01}, + urldate = {2012-01-01}, + pages = {67-70}, + booktitle = {Proceedings of the great lakes symposium on VLSI}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{FeiVLSI2011, + title = {Return Data Interleaving for Multi-Channel Embedded CMPs Systems}, + author = {Fei Hong and Aviral Shrivastava and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Hong2011TVLSI.pdf}, + year = {2011}, + date = {2011-06-01}, + journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, + number = {12769237}, + pages = {1351-1354}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@article{LeeTVLSI2011, + title = {Static Analysis of Register File Vulnerability}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2011TVLSI.pdf}, + year = {2011}, + date = {2011-04-01}, + journal = {IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits}, + volume = {30}, + number = {4}, + pages = {606-616}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{AarulVLSI2011, + title = {LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches}, + author = {Aarul Jain and Aviral Shrivastava and Chaitali Chakrabarti}, + url = {https://mpslab-asu.github.io/publications/papers/Jain2011VLSID.pdf https://mpslab-asu.github.io/publications/slides/Jain2011VLSID.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the 24th International Conference on VLSI Design}, + pages = {298-303}, + booktitle = {IEEE Computer Society}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{PiotrISLPED2011, + title = {Fast and Energy-Efficient Constant-Coefficient FIR Filters Using Residue Number System}, + author = {Piotr Patronik and Krzysztof Berezowski and Stanislaw Piestrak and Janusz Biernat and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Patronik2011ISLPED.pdf}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED)}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KimDAC2011, + title = {CuMAPz: A tool to Analyze Memory Access Patterns in CUDA}, + author = {Yooseong Kim and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2011DAC.pdf https://mpslab-asu.github.io/publications/slides/Kim2011DAC.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the 48th Design Automation Conference (DAC)}, + pages = {128-133}, + keywords = {GPU Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{JeyapaulICPP2011, + title = {UnSync: A Soft-Error Resilient Redundant Multicore Architecture}, + author = {Reiley Jeyapaul and Fei Hong and Aviral Shrivastava and Abhishek Risheekesan and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2011ICPP.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2011ICPP.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the International Conference on Parallel Processing (ICPP)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaICPP2011, + title = {Enabling Multithreading on CGRAs}, + author = {Aviral Shrivastava and Jared Pager and Reiley Jeyapaul and Mahdi Hamzeh and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2011ICPP.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2011ICPP.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the International Conference on Parallel Processing (ICPP)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{BaiASAP2011, + title = {Stack Data Management for Limited Local Memory (LLM) Multi-core Processors}, + author = {Ke Bai and Aviral Shrivastava and Saleel Kudchadker}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2011ASAP.pdf https://mpslab-asu.github.io/publications/slides/Bai2011ASAP.slides}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{BaiCASES2011, + title = {Vector class on limited local memory (LLM) multi-core processors}, + author = {Ke Bai and Di Lu and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2011CASES.pdf https://mpslab-asu.github.io/publications/slides/Bai2011CASES.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the 14th international conference on Compilers,architectures and synthesis for embedded systems (CASES)}, + pages = {215--224}, + booktitle = {ACM}, + address = {New York, NY, USA}, + series = {CASES '11}, + note = {ISBN 978-1-4503-0713-0}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{KimTODAES2011, + title = {Memory Access Optimization in compilation for Coarse Grain Reconfigurable Architectures}, + author = {Yongjoo Kim and Jongeun Lee and Aviral Shrivastava and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2011TODAES.pdf}, + year = {2011}, + date = {2011-01-01}, + journal = {ACM TODAES: ACM Transactions on Design Automation of Electronic Systems}, + volume = {11}, + number = {3}, + pages = {42:1-42:27}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {article} +} + +@article{KimTCAD2011, + title = {High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures}, + author = {Yongjoo Kim and Jongeun Lee and Aviral Shrivastava and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2011TCAD.pdf}, + year = {2011}, + date = {2011-01-01}, + journal = {IEEE TCAD: IEEE Transactions on Computer Aided Design}, + volume = {30}, + number = {11}, + pages = {1599 - 1609}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {article} +} + +@mastersthesis{PagerMASTERTHESIS2011, + title = {Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems}, + author = {Jared Pager}, + url = {https://mpslab-asu.github.io/publications/papers/Pager2011THESIS.pdf https://mpslab-asu.github.io/publications/slides/Pager2011THESIS.pptx}, + year = {2011}, + date = {2011-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{LuCODESISSS2011, + title = {Branch Penalty Reduction on IBM Cell SPUs via Software Branch Hinting}, + author = {Jing Lu and Yooseong Kim and Aviral Shrivastava and Chuan Huang}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2011CODES.pdf https://mpslab-asu.github.io/publications/slides/Lu2011CODES.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of CODES+ISSS}, + pages = {355-364}, + keywords = {Power, Temperature and Variation Aware Computing, Software Branch Hinting}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{JeyapaulCASES2011, + title = {Smart Cache Cleaning: Energy efficient vulnerability reduction in embedded processors}, + author = {Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2011CASES.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2011CASES.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems}, + pages = {105--114}, + booktitle = {ACM}, + series = {CASES '11}, + key = {978-1-4503-0713-0}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{LeeTODAES2010, + title = {Partitioning Techniques for Partially Protected Caches in Resource-Constrained Embedded Systems}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Ilya Issenin and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2010TODAES.pdf}, + year = {2010}, + date = {2010-10-01}, + journal = {ACM TODAES: ACM Transactions on Design Automation of Embedded Systems}, + volume = {15}, + number = {4}, + pages = {30:1-30:30}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{AaCODESISSS2010, + title = {Compilation Techniques for CGRAs: Exploring All Parallelization Approaches}, + author = {Tom Vander Aa and Praveen Raghavan and Scott Mahlke and Bjorn De Sutter and Aviral Shrivastava and Frank Hannig}, + url = {https://mpslab-asu.github.io/publications/papers/Vanderaa2010CODES.pdf}, + year = {2010}, + date = {2010-10-01}, + pages = {185-186}, + booktitle = {Hardware/Software Codesign and System Synthesis (CODES+ISSS)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{JungASAP2010, + title = {Dynamic code mapping for limited local memory systems}, + author = {Seungchul Jung and Aviral Shrivastava and Ke Bai}, + url = {https://mpslab-asu.github.io/publications/papers/Jung2010ASAP.pdf https://mpslab-asu.github.io/publications/slides/Jung2010ASAP.pptx}, + year = {2010}, + date = {2010-07-01}, + booktitle = {Proceedings of the International Conference on Application-specific Systems Architectures and Processors (ASAP)}, + note = {ISSN 1063-6268}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{LeeTCAD2010, + title = {A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2010TCAD.pdf}, + year = {2010}, + date = {2010-07-01}, + journal = {IEEE TCAD: IEEE Transactions on Computer Aided Design}, + volume = {29}, + number = {7}, + pages = {1018-1027}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{ShrivastavaLCTES2010, + title = {Cache Vulnerability Equations for protecting data in embedded processor caches from soft errors}, + author = {Aviral Shrivastava and Jongeun Lee and Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2010LCTES.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2010LCTES.slides}, + year = {2010}, + date = {2010-01-01}, + journal = {SIGPLAN}, + volume = {45}, + number = {4}, + pages = {143-152}, + booktitle = {Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems}, + note = {ISSN 0362-1340}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{JeyapaulSCOPES2010, + title = {B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems}, + author = {Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2010SCOPES.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2010SCOPES.pptx}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems(SCOPES)}, + pages = {2:1-2:10}, + series = {SCOPES '10}, + note = {ISBN 978-1-4503-0084-1}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KimLCTES2010, + title = {Operation and data mapping for CGRAs with multi-bank memory}, + author = {Yongjoo Kim and Jongeun Lee and Aviral Shrivastava and Jonghee Yoon and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2010LCTES.pdf https://mpslab-asu.github.io/publications/slides/Kim2010LCTES.slides}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 2010 International Conference on Languages Compilers and Tools for Embedded Systems (LCTES)}, + volume = {45}, + number = {4}, + pages = {17-26}, + note = {ISSN 0362-1340}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KimHIPEAC2010, + title = {Memory-Aware Application Mapping on Coarse Grain Reconfigurable Arrays}, + author = {Yongjoo Kim and Jongeun Lee and Aviral Shrivastava and Jonghee Yoon and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2010HIPEAC.pdf}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 2010 International Conference on High-Performance Embedded Architectures and Compilers (HIPEAC)}, + volume = {45}, + number = {4}, + pages = {17-26}, + note = {ISSN 0362-1340}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{ShrivastavaTVLSI2010, + title = {Reducing Functional Unit Power Consumption and its Variation using Leakage Sensors}, + author = {Aviral Shrivastava and Deepa Kannan and Sarvesh Bhardwaj and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2010TVLSI.pdf}, + year = {2010}, + date = {2010-01-01}, + journal = {IEEE TVLSI : IEEE Transactions on Very Large Scale Integration Systems}, + volume = {18}, + number = {6}, + pages = {988-997}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{BoydDATE2011, + title = {Power-Accuracy Tradeoffs in Human Activity Transition Detection}, + author = {Jeffrey Boyd and Hari Sundaram and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Boyd2010DATE.pdf https://mpslab-asu.github.io/publications/slides/Boyd2010DATE.pptx}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 2010 International Conference on Design Automation and Test in Europe (DATE)}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@book{PandaSPRINGER2010, + title = {Power-Efficient System Design}, + author = {Preeti Ranjan Panda and Aviral Shrivastava and B V N Silpa and Krishnaiah Gummidipudi}, + url = {http://www.springer.com/us/book/9781441963871}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Springer}, + edition = {1st edition}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {book} +} + +@mastersthesis{SaleelMASTERTHESIS2010, + title = {Managing Stack Data on Limited Local Memory Multi-core Processors}, + author = {Saleel Kudchadker}, + url = {https://mpslab-asu.github.io/publications/papers/Kudchadker2010THESIS.pdf https://mpslab-asu.github.io/publications/slides/Kudchadker2010THESIS.slides}, + year = {2010}, + date = {2010-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@mastersthesis{FeiMASTERTHESIS2010, + title = {UnSync: A Soft-Error Resilient Redundant CMP Architecture}, + author = {Fei Hong}, + url = {https://mpslab-asu.github.io/publications/papers/Hong2010THESIS.pdf}, + year = {2010}, + date = {2010-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inproceedings{BaiCODESISSS2010, + title = {Heap Data Management for Limited Local Memory (LLM) Multi-core Processors}, + author = {Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2010CODES.pdf https://mpslab-asu.github.io/publications/slides/Bai2010CODES.pptx}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 23th international symposium on System Synthesis (CODES+ISSS)}, + pages = {317-326}, + booktitle = {ACM Press}, + address = {New York, NY, USA}, + note = {ISBN}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{JungMASTERTHESIS2010, + title = {Dynamic Code Mapping for Limited Local Memory Systems}, + author = {Seungchul Jung}, + url = {https://mpslab-asu.github.io/publications/papers/Jung2010THESIS.pdf https://mpslab-asu.github.io/publications/slides/Jung2010THESIS.pptx}, + year = {2010}, + date = {2010-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@article{JeyapaulVLSID2010, + title = {Code Transformations for TLB Power Reduction}, + author = {Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2010IJPP.pdf}, + year = {2010}, + date = {2010-01-01}, + journal = {International Journal of Parallel Programming}, + volume = {38}, + number = {3-4}, + pages = {254-276}, + booktitle = {Springer US}, + note = {ISSN 0885-7458}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@inbook{PandaBOOK2010, + title = {Basic Low Power Digital Design}, + author = {Preeti Ranjan Panda and B V N Silpa and Aviral Shrivastava and Krishnaiah Gummidipudi}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Power-efficient System Design}, + number = {978-1-4419-6387-1}, + pages = {11-39}, + booktitle = {Springer US}, + chapter = {2}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inbook} +} + +@inbook{PandaBook2010_2, + title = {Power Aware Operating Systems, Compilers, and Application Software}, + author = {Preeti Ranjan Panda and B V N Silpa and Aviral Shrivastava and Krishnaiah Gummidipudi}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Power-efficient System Design}, + number = {978-1-4419-6387-1}, + pages = {139-181}, + booktitle = {Springer US}, + chapter = {5}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inbook} +} + +@inproceedings{ChokshiCASES2009, + title = {Exploiting residue number system for power-efficient digital signal processing in embedded processors}, + author = {Rooju Chokshi and Krzysztof Berezowski and Aviral Shrivastava and Stanislaw Piestrak}, + url = {https://mpslab-asu.github.io/publications/papers/Chokshi2009CASES.pdf https://mpslab-asu.github.io/publications/slides/Chokshi2009CASES.pptx}, + year = {2009}, + date = {2009-01-01}, + booktitle = {CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems}, + pages = {19-28}, + note = {ISBN 978-1-60558-626-7}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{LeeLCTES2009, + title = {A compiler optimization to reduce soft errors in register files}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2009LCTES.pdf https://mpslab-asu.github.io/publications/slides/Lee2009LCTES.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {LCTES '09: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems}, + pages = {41-49}, + note = {ISBN 978-1-60558-356-3}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{SoaresVLSISOC2009, + title = {Adaptive Reduced Bit-width Instruction Set Architecture (adapt-rISA)}, + author = {Sandro Neves Soares and Ashok Halambi and Aviral Shrivastava and Flavio Rech Wagner and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Soares2009VLSISOC.pdf https://mpslab-asu.github.io/publications/slides/Soares2009VLSISOC.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {VLSI-SOC 2009 :Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integreation}, + keywords = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{MylavarapuDATE2009, + title = {FSAF: File system aware flash translation layer for NAND Flash Memories}, + author = {Sai Krishna Mylavarapu and Siddharth Choudhuri and Aviral Shrivastava and Jongeun Lee and T Givargis}, + url = {https://mpslab-asu.github.io/publications/papers/Mylavarapu2009DATE.pdf https://mpslab-asu.github.io/publications/slides/Mylavarapu2009DATE.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {Design, Automation Test in Europe Conference Exhibition (DATE)}, + note = {ISSN 1530-1591}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{LeeDATE2009, + title = {Static analysis to mitigate soft errors in register files}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2009DATE.pdf https://mpslab-asu.github.io/publications/slides/Lee2009DATE.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {Design, Automation Test in Europe Conference Exhibition (DATE)}, + note = {ISSN 1530-1591}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KannanASPDAC2009, + title = {A software solution for dynamic stack management on scratch pad memory}, + author = {Arun Kannan and Aviral Shrivastava and Amit Pabalkar and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2009ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Kannan2009ASPDAC.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation}, + pages = {612-617}, + note = {ISBN 978-1-4244-2748-2}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{LeeASPDAC2009, + title = {Compiler-managed register file protection for energy-efficient soft error reduction}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2009ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Lee2009ASPDAC.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation}, + pages = {618-623}, + note = {ISBN 978-1-4244-2748-2}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{JeyapaulVLSI2009, + title = {Code Transformations for TLB Power Reduction}, + author = {Reiley Jeyapaul and Sandeep Marathe and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2009VLSID.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2009VLSID.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {VLSID '09: Proceedings of the International Conference on VLSI Design}, + pages = {413-418}, + note = {ISBN 978-0-7695-3506-7}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{ArunMASTERTHESIS2009, + title = {A Software-Only Solution for Stack Management on Systems with Scratch Pad Memory}, + author = {Arun Kannan}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2009THESIS.pdf https://mpslab-asu.github.io/publications/slides/Kannan2009THESIS.slides}, + year = {2009}, + date = {2009-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@article{ShrivastavaTCAD2009, + title = {A Software-only solution to use Scratch Pads for Stack Data}, + author = {Aviral Shrivastava and Arun Kannan and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2009TCADA.pdf}, + year = {2009}, + date = {2009-01-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + volume = {28}, + number = {11}, + pages = {1719-1728}, + note = {ISSN 0278-0070}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {article} +} + +@article{ShrivastavaTCADCIL2009, + title = {Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures}, + author = {Aviral Shrivastava and Ilya Issenin and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2009TCADB.pdf}, + year = {2009}, + date = {2009-01-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + volume = {28}, + number = {3}, + pages = {461-466}, + note = {ISSN 0278-0070}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@article{YoonTVLSI2009, + title = {A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures}, + author = {Jonghee Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Yoon2009TVLSI.pdf}, + year = {2009}, + date = {2009-01-01}, + journal = {IEEE Transactions on Very Large Scale Integrated Circuits}, + volume = {17}, + number = {11}, + pages = {1565-1579}, + note = {ISSN 1063-8210}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {article} +} + +@article{LeeTVLSI2009, + title = {Partially Protected Caches to Reduce Failures due to Soft Errors in Multimedia Applications}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Ilya Issenin and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2009TVLSI.pdf}, + year = {2009}, + date = {2009-01-01}, + journal = {IEEE Transactions on VLSI}, + volume = {17}, + number = {9}, + pages = {1343-1348}, + note = {ISSN 1063-8210}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@mastersthesis{AmitMASTERTHESIS2009, + title = {A Dynamic Code Mapping Technique for Scratch Pad Memories in Embedded Systems}, + author = {Amit Pabalkar}, + url = {https://mpslab-asu.github.io/publications/papers/Pabalkar2009THESIS.pdf https://mpslab-asu.github.io/publications/slides/Pabalkar2009THESIS.slides}, + year = {2009}, + date = {2009-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@mastersthesis{RoojuMASTERTHESIS2009, + title = {Residue number system enhancements for programmable processors}, + author = {Rooju Chokshi}, + url = {https://mpslab-asu.github.io/publications/papers/Chokshi2009THESIS.pdf https://mpslab-asu.github.io/publications/slides/Chokshi2009THESIS.slides}, + year = {2009}, + date = {2009-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@mastersthesis{SaiMASTERTHESIS2009, + title = {Improving Application Response Times of Nand Flash based Systems}, + author = {Sai Krishna Mylavarapu}, + url = {https://mpslab-asu.github.io/publications/papers/Mylavarapu2009THESIS.pdf https://mpslab-asu.github.io/publications/slides/Mylavarapu2009THESIS.slides}, + year = {2009}, + date = {2009-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@techreport{LeeTECHREPORT2008, + title = {Cross-Layer Interactions of Error Control Schemes in Mobile Multimedia Systems}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Minyoung Kim and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008REPORTA.pdf}, + year = {2008}, + date = {2008-07-01}, + institution = {University of California, Irvine}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {techreport} +} + +@article{ParkTCAD2008, + title = {Register File Power Reduction Using Bypass Sensitive Compiler}, + author = {Sanghyun Park and Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau and Yunheung Paek and Eugene Earlie}, + url = {https://mpslab-asu.github.io/publications/papers/Park2008TCAD.pdf}, + year = {2008}, + date = {2008-06-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + volume = {27}, + number = {6}, + pages = {1155-1159}, + note = {ISSN 0278-0070}, + keywords = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@techreport{LeeTECHREPORT2008_2, + title = {Partially Protected Caches to Reduce Failures due to Soft Errors in Mission-Critical Multimedia Systems}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Ilya Issenin and Nikil Dutt and Nalini Venkatasubramanian}, + year = {2008}, + date = {2008-06-01}, + institution = {University of California, Irvine}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {techreport} +} + +@inproceedings{LeeCODESISSS2008, + title = {Static analysis of processor stall cycle aggregation}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008CODES.pdf https://mpslab-asu.github.io/publications/slides/Lee2008CODES.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {CODES/ISSS '08: Proceedings of the international conference on Hardware/Software codesign and system synthesis}, + pages = {25-30}, + note = {ISBN 978-1-60558-470-6}, + keywords = {Power, Temperature and Variation Aware Computing, Processor Idle Cycle Aggregation}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{PabalkarHIPC2008, + title = {SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories}, + author = {Amit Pabalkar and Aviral Shrivastava and Arun Kannan and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Pabalkar2008HIPC.pdf https://mpslab-asu.github.io/publications/slides/Pabalkar2008HIPC.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {HIPC 2008 :International Conference on High Performance Computing}, + pages = {569-582}, + keywords = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{LeeMM2008, + title = {Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Minyoung Kim and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008MM.pdf https://mpslab-asu.github.io/publications/slides/Lee2008MM.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {MM '08: Proceeding of the 16th ACM international conference on Multimedia}, + pages = {319-328}, + note = {ISBN 978-1-60558-303-7}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ParkDATE2008, + title = {Hiding cache miss penalty using priority-based execution for embedded processors}, + author = {Sanghyun Park and Aviral Shrivastava and Yunheung Paek}, + year = {2008}, + date = {2008-01-01}, + booktitle = {DATE '08: Proceedings of the conference on Design, automation and test in Europe}, + note = {ISBN 978-3-9810801-3-1}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{YoonDAC2008, + title = {SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures}, + author = {Jonghee Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Reiley Jeyapaul and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Yoon2008ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Yoon2008ASPDAC.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation}, + pages = {776-782}, + note = {ISBN 978-1-4244-1922-7 (Best Paper Award Candidate)}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaDAC2008, + title = {A compiler-in-the-loop framework to explore horizontally partitioned cache architectures}, + author = {Aviral Shrivastava and Ilya Issenin and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2008ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2008ASPDAC.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation}, + pages = {328-333}, + note = {ISBN 978-1-4244-1922-7}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KannanVLSID2008, + title = {PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors}, + author = {Deepa Kannan and Aseem Gupta and Aviral Shrivastava and Nikil Dutt and Fadi J Kurdahi}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2008VLSIDA.pdf https://mpslab-asu.github.io/publications/slides/Kannan2008VLSIDA.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {VLSID '08: Proceedings of the 21st International Conference on VLSI Design}, + pages = {421-427}, + note = {ISBN 0-7695-3083-4}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{KannanVLSI2008, + title = {Temperature and Process Variations aware Power Gating of Functional Units}, + author = {Deepa Kannan and Aviral Shrivastava and Vipin Mohan and Sarvesh Bhardwaj and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2008VLSIDB.pdf}, + year = {2008}, + date = {2008-01-01}, + booktitle = {VLSID '08: Proceedings of the 21st International Conference on VLSI Design}, + pages = {515-520}, + note = {ISBN 0-7695-3083-4}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@incollection{MishraPDL2008, + title = {ADL-Driven Methodologies for Design Automation of Programmable Architectures}, + author = {Prabhat Mishra and Aviral Shrivastava}, + url = {http://dl.acm.org/citation.cfm?id=1481522}, + year = {2008}, + date = {2008-01-01}, + booktitle = {Processor Description Languages: Applications and Methodologies}, + series = {Systems on Silicon}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {incollection} +} + +@article{LeeDESDMR2008, + title = {Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008DESD.pdf https://mpslab-asu.github.io/publications/slides/Lee2008DESD.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {DIPES 2008 :IFIP Conference on Distributed and Parallel Embedded Systems}, + journal = {Distributed Embedded Systems: Design, Middleware and Resources}, + volume = {271}, + pages = {213-225}, + note = {10.1007/978-0-387-09661-2_21}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{KannanVLSID2008_2, + title = {Power Reduction of Functional Units Considering Temperature and Process Variations}, + author = {Deepa Kannan and Aviral Shrivastava and Sarvesh Bhardwaj and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2008VLSIDC.pdf https://mpslab-asu.github.io/publications/slides/Kannan2008VLSIDC.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {VLSID'08: Proceedings of the 21st International Conference on VLSI Design}, + pages = {533--539}, + booktitle = {IEEE Computer Society}, + address = {Washington, DC, USA}, + note = {ISBN 0-7695-3083-4}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@mastersthesis{JeyapaulMASTERTHESIS2008, + title = {Static Analysis to Mitigate Soft Error Failures in Processors}, + author = {Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2008THESIS.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2008THESIS.pptx}, + year = {2008}, + date = {2008-01-01}, + school = {Arizona State University}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {mastersthesis} +} + +@inbook{MishraBOOK2008, + title = {ADL-driven Methodologies for Design Automation of Embedded Processors}, + author = {Prabhat Mishra and Aviral Shrivastava}, + year = {2008}, + date = {2008-01-01}, + booktitle = {Processor Description Languages}, + pages = {13-33}, + booktitle = {Elsevier Inc.}, + chapter = {2}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inbook} +} + +@inproceedings{LeeACMMM2008, + title = {Mitigating the Impact of Hardware Defects on Multimedia Applications � A Cross-Layer Approach}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Minyoung Kim and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008MM.pdf https://mpslab-asu.github.io/publications/slides/Lee2008MM.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {ACM International Conference on Multimedia}, + booktitle = {ACM}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{BakerCODESISSS2007, + title = {Smart driver for power reduction in next generation bistable electrophoretic display technology}, + author = {Michael A Baker and Aviral Shrivastava and Karam S Chatha}, + url = {https://mpslab-asu.github.io/publications/papers/Baker2007CODES.pdf https://mpslab-asu.github.io/publications/slides/Baker2007CODES.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {CODES+ISSS '07: Proceedings of international conference on Hardware/software codesign and system synthesis}, + pages = {197-202}, + note = {ISBN 978-1-59593-824-4}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{YoonWASP2007, + title = {Power Conscious Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm}, + author = {Jonghee Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/slides/Yoon2007WASP.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {WASP '07: Workshop on Application Specific Processors}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ZhuDATE2007, + title = {Interactive presentation: Functional and timing validation of partially bypassed processor pipelines}, + author = {Qiang Zhu and Aviral Shrivastava and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Zhu2007DATE.pdf https://mpslab-asu.github.io/publications/slides/Zhu2007DATE.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {DATE '07: Proceedings of the conference on Design, automation and test in Europe}, + pages = {1164-1169}, + note = {ISBN 978-3-9810801-2-4}, + keywords = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{MisraICC2007, + title = {Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors}, + author = {Satyajayant Misra and Guoliang Xue and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Misra2007ICC.pdf https://mpslab-asu.github.io/publications/slides/Misra2007ICC.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {ICC '07. IEEE International Conference on Communications}, + pages = {3057-3062}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@incollection{ShrivastavaTCDHOAMCG22007, + title = {Compiler Aided Design of Embedded Computers}, + author = {Aviral Shrivastava and Nikil Dutt}, + url = {https://www.crcpress.com/The-Compiler-Design-Handbook-Optimizations-and-Machine-Code-Generation/Srikant-Shankar/9781420043822}, + year = {2007}, + date = {2007-01-01}, + booktitle = {The Compiler Design Handbook: Optimizations and Machine Code Generation:2nd Edition}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {incollection} +} + +@article{ParkTCAD2007, + title = {Automatic Design Space Exploration of Register Bypasses in Embedded Processors}, + author = {Sanghyun Park and Aviral Shrivastava and Eugene Earlie and Nikil Dutt and Alexandru Nicolau and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Park2007TCAD.pdf}, + year = {2007}, + date = {2007-01-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + volume = {26}, + number = {12}, + pages = {2102-2115}, + note = {ISSN 0278-0070}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@inproceedings{YoonVLSI2007, + title = {Efficient Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm}, + author = {Jonghee Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Reiley Jeyapaul and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Yoon2007VLSID.pdf https://mpslab-asu.github.io/publications/slides/Yoon2007VLSID.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {2007 International Conference on VLSI Design (VLSID 2007)}, + booktitle = {IEEE}, + keywords = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{LeeCASES2006, + title = {Mitigating soft error failures for multimedia applications by selective data protection}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Ilya Issenin and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2006CASES.pdf https://mpslab-asu.github.io/publications/slides/Lee2006CASES.slides}, + year = {2006}, + date = {2006-01-01}, + booktitle = {CASES '06: Proceedings of the international conference on Compilers, architecture and synthesis for embedded systems}, + pages = {411-420}, + note = {ISBN 1-59593-543-6}, + keywords = {Reliability for Machine Learning}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ParkLCTES2006, + title = {Bypass Aware Instruction Scheduling for Register File Power Reduction}, + author = {Sanghyun Park and Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau and Yunheung Paek and Eugene Earlie}, + url = {https://mpslab-asu.github.io/publications/papers/Park2006LCTES.pdf https://mpslab-asu.github.io/publications/slides/Park2006LCTES.slides}, + year = {2006}, + date = {2006-01-01}, + booktitle = {Proceedings of the conference on Language, Compilers and Tool support for Embedded Systems}, + pages = {173-181}, + note = {ISBN 0362-1340}, + keywords = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ParkDATE2006, + title = {Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors}, + author = {Sanghyun Park and Eugene Earlie and Aviral Shrivastava and Alexandru Nicolau and Nikil Dutt and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Park2006DATE.pdf https://mpslab-asu.github.io/publications/slides/Park2006DATE.slides}, + year = {2006}, + date = {2006-01-01}, + booktitle = {DATE '06: Proceedings of the conference on Design, automation and test in Europe}, + pages = {1197-1202}, + note = {ISBN 3-9810801-0-6}, + keywords = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@article{MishraTODAES2006, + title = {Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs}, + author = {Prabhat Mishra and Aviral Shrivastava and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Mishra2006TOADAES.pdf}, + year = {2006}, + date = {2006-01-01}, + journal = {ACM Transactions on Design Automation of Electronic Systems}, + volume = {11}, + number = {3}, + pages = {626-658}, + note = {ISSN 1084-4309}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@article{ShrivastavaTVLSI2006, + title = {Retargetable pipeline hazard detection for partially bypassed processors}, + author = {Aviral Shrivastava and Eugene Earlie and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2006TVLSI.pdf}, + year = {2006}, + date = {2006-01-01}, + booktitle = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, + volume = {14}, + pages = {791-801}, + note = {ISBN 1063-8210}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {article} +} + +@article{ShrivastavaTODAES2006, + title = {Compilation framework for code size reduction using reduced bit-width ISAs (rSAs)}, + author = {Aviral Shrivastava and Partha Biswas and Ashok Halambi and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2006TODAES.pdf}, + year = {2006}, + date = {2006-01-01}, + journal = {ACM Transactions on Design Automation of Electronic Systems}, + volume = {11}, + number = {1}, + pages = {123-146}, + note = {ISSN 1084-4309}, + keywords = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + tppubtype = {article} +} + +@phdthesis{ShrivastavaPHDTHESIS2006, + title = {Compiler-in-Loop Exploration of Programmable Embedded Systems}, + author = {Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2006THESIS.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2006THESIS.slides}, + year = {2006}, + date = {2006-01-01}, + school = {Donald Bren School of Information and Computer Sciences}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {phdthesis} +} + +@inproceedings{ShrivastavaCASES2005, + title = {Compilation techniques for energy reduction in horizontally partitioned cache architectures}, + author = {Aviral Shrivastava and Ilya Issenin and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2005CASES.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2005CASES.slides}, + year = {2005}, + date = {2005-01-01}, + booktitle = {CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems}, + pages = {90-96}, + note = {ISBN 1-59593-149-X}, + keywords = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaCODESISSS2005, + title = {Aggregating processor free time for energy reduction}, + author = {Aviral Shrivastava and Eugene Earlie and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2005CODES.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2005CODES.slides}, + year = {2005}, + date = {2005-01-01}, + booktitle = {CODES+ISSS '05: Proceedings of the international conference on Hardware/software codesign and system synthesis}, + pages = {154-159}, + note = {ISBN 1-59593-161-9}, + keywords = {Power, Temperature and Variation Aware Computing, Processor Idle Cycle Aggregation}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaDATE2005, + title = {PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors}, + author = {Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau and Eugene Earlie}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2005DATE.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2005DATE.slides}, + year = {2005}, + date = {2005-01-01}, + booktitle = {DATE '05: Proceedings of the conference on Design, Automation and Test in Europe}, + keywords = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaTECHCONSRC2005, + title = {Compiler-in-the-Loop ADL-driven Early Architectural Exploration}, + author = {Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau and Eugene Earlie}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2005TECHCON.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2005TECHCON.slides}, + year = {2005}, + date = {2005-01-01}, + booktitle = {TECHCON 2005: Semiconductor Research Corporation}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaCODES2004, + title = {Operation tables for scheduling in the presence of incomplete bypassing.}, + author = {Aviral Shrivastava and Eugene Earlie and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2004CODES.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2004CODES.slides}, + year = {2004}, + date = {2004-01-01}, + booktitle = {CODES+ISSS}, + pages = {194-199}, + keywords = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaASPDAC2004, + title = {Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)}, + author = {Aviral Shrivastava and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2004ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2004ASPDAC.slides}, + year = {2004}, + date = {2004-01-01}, + booktitle = {ASP-DAC '04: Proceedings of the 2004 conference on Asia South Pacific design automation}, + pages = {475-477}, + note = {ISBN 0-7803-8175-0}, + keywords = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@techreport{PasrichaTECHREPORT2003, + title = {A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor}, + author = {Sudeep Pasricha and Partha Biswas and Prabhat Mishra and Aviral Shrivastava and Atri Mandal and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Pasricha2003REPORT.pdf}, + year = {2003}, + date = {2003-04-01}, + institution = {University of California, Irvine}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {techreport} +} + +@inproceedings{HalambiISSS2002, + title = {A design space exploration framework for reduced bit-width instruction set architecture (rISA) design}, + author = {Ashok Halambi and Aviral Shrivastava and Partha Biswas and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Halambi2002ISSS.pdf https://mpslab-asu.github.io/publications/slides/Halambi2002ISSS.slides}, + year = {2002}, + date = {2002-01-01}, + booktitle = {ISSS '02: Proceedings of the 15th international symposium on System Synthesis}, + pages = {120-125}, + note = {ISBN 1-58113-576-9}, + keywords = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{HalambiDATE2002, + title = {An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs}, + author = {Ashok Halambi and Aviral Shrivastava and Partha Biswas and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Halambi2002DATE.pdf https://mpslab-asu.github.io/publications/slides/Halambi2002DATE.slides}, + year = {2002}, + date = {2002-01-01}, + booktitle = {DATE '02: Proceedings of the conference on Design, automation and test in Europe}, + pages = {402}, + keywords = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{HalambiSCOPES2001, + title = {A customizable compiler framework for embedded systems}, + author = {Ashok Halambi and Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Halambi2001SCOPES.pdf}, + year = {2001}, + date = {2001-01-01}, + booktitle = {In SCOPES}, + booktitle = {Springer}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + +@inproceedings{ShrivastavaVLSI2000, + title = {Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming}, + author = {Aviral Shrivastava and Mohit Kumar and Sanjiv Kapoor and Shashi Kumar and M Balakrishnan}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2000VLSID.pdf}, + year = {2000}, + date = {2000-01-01}, + booktitle = {VLSID '00: Proceedings of the 13th International Conference on VLSI Design}, + pages = {110}, + note = {ISBN 0-7695-0487-6}, + keywords = {Efficient Embedded Computing}, + pubstate = {published}, + tppubtype = {inproceedings} +} + diff --git a/src/env.d.ts b/src/env.d.ts new file mode 100644 index 0000000..acef35f --- /dev/null +++ b/src/env.d.ts @@ -0,0 +1,2 @@ +/// +/// diff --git a/src/layouts/Layout.astro b/src/layouts/Layout.astro new file mode 100644 index 0000000..59b998c --- /dev/null +++ b/src/layouts/Layout.astro @@ -0,0 +1,37 @@ +--- +import '../styles/main.scss'; + +interface Props { + title: string; + description?: string; +} + +const { title, description = 'MPS Lab — Making Programming Simple at Arizona State University' } = Astro.props; +--- + + + + + + + + + {title} | MPS Lab @ ASU + + + + + +
+ +
+ + + diff --git a/src/pages/contact.astro b/src/pages/contact.astro new file mode 100644 index 0000000..bcad32b --- /dev/null +++ b/src/pages/contact.astro @@ -0,0 +1,84 @@ +--- +import Layout from '../layouts/Layout.astro'; +import Navbar from '../components/astro/Navbar.astro'; +import Footer from '../components/astro/Footer.astro'; +--- + + + + +
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