diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..999c6d9 --- /dev/null +++ b/.gitignore @@ -0,0 +1,56 @@ +# Local node_modules +node_modules/ +.npm/ + +# Build outputs +dist/ +.output/ +.vercel/ +.netlify/ +.worker/ +public/build/ + +# Astro dev/build outputs +.astro/ +server.log +server_new.pid + +# Logs +logs +*.log +npm-debug.log* +yarn-debug.log* +yarn-error.log* +pnpm-debug.log* +lerna-debug.log* + +# OS/Editor +.DS_Store +.AppleDouble +.LSOverride +Icon +._* +.DocumentRevisions-V100 +.fseventsd +.Spotlight-V100 +.TemporaryItems +.Trashes +.VolumeIcon.icns +.com.apple.timemachine.donotpresent + +# IDEs +.idea/ +.vscode/ + +# Environment variables +.env +.env.* +!.env.example + +# Temporary files +tmp/ +temp/ + +*scrape* + +venv/ diff --git a/MPS Lab Astro Pipeline Design.md b/MPS Lab Astro Pipeline Design.md new file mode 100644 index 0000000..73ecdba --- /dev/null +++ b/MPS Lab Astro Pipeline Design.md @@ -0,0 +1,156 @@ +# **MPS Lab Website Overhaul: System Architecture & Implementation Guide** + +## **1\. System Overview** + +This document serves as the implementation blueprint for the MPS Lab website overhaul. The system is designed as a highly performant, fully static website that utilizes the Island **Architecture**. + +**Core Tech Stack:** + +* **Framework:** Astro (Static Site Generation mode) +* **UI Libraries:** React (for complex interactive components only), Tailwind CSS (styling), SCSS/Sass (Theme management), Lucide React (icons). +* **Data Parsing:** bibtex-parse-js (Publications), fuse.js (Client-side search). +* **Hosting:** GitHub Pages via GitHub Actions. +* **Development Environment:** Docker & Docker Compose (Isolated runtime). + +## **2\. UI Design Concepts** + +Below is the targeted visual design for the new MPS Lab website. The design emphasizes a clean, highly readable "Modern Academic" layout with subtle ASU branding (Maroon and Gold accents), ample whitespace, and an accessible grid system for research areas. + +![][image1] + +* **Visual Identity:** Heavy Navy Blue and Green headers (derived from the lab logo) balanced against clean white backgrounds, with ASU Maroon serving as the primary call-to-action color. +* **Component Library:** Tailwind CSS is used to enforce consistent padding, rounded corners, and mobile-first responsive grids across all devices, mapping directly to SCSS-managed theme variables. + +### **Reference Websites (Style Inspiration)** + +To guide the visual development and component styling, the following websites should be used as benchmarks for the aesthetic direction: + +**Modern Academic Focus (Clean, Accessible, Institutional):** + +* [**Stanford AI Lab (SAIL)**](https://ai.stanford.edu/)**:** Excellent use of whitespace, clear typography, and a highly functional layout that feels both academic and modern. +* [**MIT CSAIL**](https://www.csail.mit.edu/)**:** Great example of managing large amounts of news, research groups, and publications without feeling cluttered. +* [**Berkeley AI Research (BAIR)**](https://bair.berkeley.edu/)**:** Minimalist approach that prioritizes content (papers and blog posts) over heavy graphics. + +## **3\. Requirement Fulfillment Mapping** + +* **Req 1: No Backend Needed:** Astro compiles the entire application into pure HTML/CSS/JS during the build step. The site is hosted on GitHub Pages, requiring zero active server management. +* **Req 2: Markdown-Driven Updates:** Lab members, news, and project updates are managed via Astro **Content Collections**. Adding a new Ph.D. student with a pop-up card simply requires dropping a student-name.md file with YAML frontmatter into the src/content/members/ directory. No HTML editing is required. +* **Req 3: Single-File Publication Updates:** Publications are stored in a single src/data/publications.bib file. At build time, Astro parses this file into JSON and passes it to an interactive React Search component. + +## **4\. Agent Implementation Blueprint** + +*Instructions for the Agentic System:* Execute the implementation in the following sequential phases. + +### **Phase 1: Containerized Development Environment Setup** + +**Objective:** Isolate the build tools and runtime environment using Docker *first* to ensure consistency and provide the npm runtime required for the subsequent scaffolding phases. + +1. **Create docker-compose.yml:** In the empty root directory, create a Docker Compose file that maps the local source code into a Node.js container. +2. **Isolate Dependencies:** Use an anonymous volume for node\_modules to prevent host OS conflicts with the container's compiled modules. +3. **Implementation Configuration:** + version: '3.8' + services: + astro: + image: node:20-alpine + working\_dir: /app + volumes: + \- .:/app + \- /app/node\_modules \# Isolates container node\_modules from the host + ports: + \- "4321:4321" \# Astro's default dev port + command: sh \-c "npm install && npm run dev \-- \--host 0.0.0.0" + +### **Phase 2: Initialization & Configuration** + +**Objective:** Scaffold the project and install dependencies using the containerized Node environment established in Phase 1\. + +1. **Initialize Astro:** Run the scaffolding command through the container into the current directory (.): + docker-compose run \--rm astro npm create astro@latest . \-- \--template minimal +2. **Install integrations:** docker-compose run \--rm astro npx astro add react tailwind +3. **Install specific libraries:** docker-compose run \--rm astro npm install lucide-react fuse.js bibtex-parse-js sass +4. **Configure:** Update astro.config.mjs to ensure output: 'static' and that React/Tailwind integrations are active. +5. **Execution:** Once configured, developers/agents will strictly use docker-compose up to start the live-reloading dev server. No source code resides inside the image itself; it is fully mounted from the host. + +### **Phase 3: Directory Structure Setup** + +**Objective:** Establish the routing and data layer skeleton. + +/ +├── public/ \# Static assets (logos, CVs, PDFs) +├── src/ +│ ├── components/ \# Reusable UI parts +│ │ ├── astro/ \# Static UI (Nav, Footer, Static Cards) +│ │ └── react/ \# Interactive UI (Search, ThemeToggle, Modals) +│ ├── content/ \# Markdown Collections +│ │ ├── config.ts \# Zod Schemas for Type Safety +│ │ ├── news/ \# .md files for updates +│ │ └── members/ \# .md files for students/faculty +│ ├── data/ +│ │ └── publications.bib \# The single source of truth for papers +│ ├── layouts/ +│ │ └── Layout.astro \# Global HTML wrapper (Dark mode logic here) +│ ├── pages/ \# Route mapping (index.astro, publications.astro) +│ └── styles/ \# SCSS Theme configuration +│ ├── main.scss \# Main stylesheet importing themes and tailwind +│ ├── \_theme-light.scss \# Light/Academic theme color variables +│ └── \_theme-dark.scss \# Dark/Alternate theme color variables +├── docker-compose.yml \# Containerized dev environment configuration + +### **Phase 4: The Content Collection Layer (Markdown)** + +**Objective:** Enable non-developers to update the site without touching HTML. + +1. **Define Schemas (src/content/config.ts):** \* Create a schema for members requiring name, role (Faculty, Ph.D., Alumni), photoUrl, joinDate, and bio. + * Create a schema for news requiring title, date, and type. +2. **Implementation:** Build an Astro component (MemberGrid.astro) that uses getCollection('members') to loop through the markdown files and render the UI cards. Use a React component (\) if the "pop-up card" requires complex state (like a click-to-expand overlay). + +### **Phase 5: The Publication Pipeline (Single-File)** + +**Objective:** Implement the searchable, filterable publication list. + +1. **Build-Time Parsing:** In src/pages/publications.astro, use Node's fs module to read src/data/publications.bib. +2. Pass the string to bibtex-parse-js to convert it into a structured JavaScript array. +3. **The Interactive Island:** Pass that parsed JSON array as a prop to a React component: \. +4. **Search Logic:** Inside PublicationSearch.jsx, initialize fuse.js on the papers array. Bind an \ to a React state to filter the rendered list in real-time. Render tags (e.g., Year, Topic) that modify a filter state. + +### **Phase 6: UI, SCSS Theme Management, and Responsiveness** + +**Objective:** Apply the MPS Lab styling requirements using dedicated SCSS files connected to Tailwind. + +1. **SCSS Theme Setup:** \* In src/styles/\_theme-light.scss, define the light mode CSS variables (e.g., \--color-primary: \#8C1D40; \--color-bg: \#ffffff;). + * In src/styles/\_theme-dark.scss, define the exact same variables with dark mode values (e.g., \--color-primary: \#FFC627; \--color-bg: \#0f172a;). + * In src/styles/main.scss, import Tailwind directives (@tailwind base; etc.) and import both theme files, nesting the dark theme variables under a .dark class. + * Import main.scss globally inside src/layouts/Layout.astro. +2. **Tailwind Configuration:** In tailwind.config.mjs, map Tailwind's color palette to your SCSS CSS variables (e.g., theme: { extend: { colors: { primary: 'var(--color-primary)' } } }). This ensures bg-primary automatically respects the active SCSS theme file. +3. **Responsiveness:** Ensure all grids use mobile-first breakpoints (e.g., grid-cols-1 md:grid-cols-2 lg:grid-cols-4). Hide desktop navs and show hamburger menus on screens smaller than md. +4. **Dark Mode Engine:** \* Ensure darkMode: 'class' is set in tailwind.config.mjs. + * Create a React component \ that toggles the dark class on the \ element and saves the user's preference to localStorage. + * Add a tiny inline \ in the \ of Layout.astro to read localStorage before the page paints to prevent theme flickering. + +ThemeToggle client:only="react" /\> that toggles the dark class on the \ element and saves the user's preference to localStorage. + +Add a tiny inline \ in the \ of Layout.astro to read localStorage before the page paints to prevent theme flickering. + +### **Phase 7: Google Forms & External Integrations** + +**Objective:** Integrate lead capture/contact forms seamlessly. + +1. Create src/pages/contact.astro. +2. Extract the \ embed code from the desired Google Form. +3. Wrap the iframe in a responsive Tailwind container (aspect-video w-full max-w-2xl mx-auto) to ensure it scales correctly on mobile devices without breaking the layout. + +### **Phase 8: Deployment Configuration** + +**Objective:** Automate GitHub Pages hosting. + +1. Create .github/workflows/deploy.yml. +2. Use the official Astro GitHub Pages action (actions/configure-pages, actions/upload-pages-artifact, actions/deploy-pages). +3. Ensure site and base (if deploying to a subpath) are configured in astro.config.mjs. + +## **5\. Security & Maintenance Notes** + +* **Zero-JS by Default:** Only components explicitly marked with client:load, client:visible, or client:only (like the Search bar or Theme Toggle) will ship JavaScript to the user. Everything else is pure, lightning-fast HTML. +* **Data Integrity:** The Zod schemas in src/content/config.ts will intentionally fail the GitHub Actions build if a lab member accidentally forgets to add a required field (like a Date or Title) to their Markdown file, preventing broken UI from reaching production. +* **Docker Portability:** Because the entire runtime is containerized, any lab member (regardless of OS) can build and test the site locally using docker-compose up without dealing with npm version conflicts or missing global dependencies. + +[image1]: \ No newline at end of file diff --git a/README.md b/README.md index bfc25cf..9f049cd 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,265 @@ -Making Programming Simple Lab: -https://labs.engineering.asu.edu/mps-lab/ +# MPS Lab @ ASU — Website -MPS Lab Publications: https://labs.engineering.asu.edu/mps-lab/publications/ +The official website for the **Make Programming Simple (MPS) Lab** at Arizona State University. Built with [Astro](https://astro.build/), [React](https://react.dev/), and [Tailwind CSS](https://tailwindcss.com/). + +**Live Website:** [https://mpslab-asu.github.io](https://mpslab-asu.github.io) + +--- + +## Tech Stack + +| Layer | Technology | +|-------|-----------| +| Framework | Astro 5 (static output) | +| UI Components | Astro (`.astro`) + React Islands | +| Styling | Tailwind CSS + SCSS (light/dark themes) | +| Icons | Lucide React | +| Search | Fuse.js (fuzzy search for publications) | +| Publications | BibTeX → `bibtex-parse-js` | +| Markdown | `marked` (for FAQ) + Custom `rehype-figure-caption` plugin | + +--- + +## Project Structure + +``` +src/ +├── components/ +│ ├── astro/ # Navbar, Footer, MemberGrid +│ └── react/ # PublicationSearch, GalleryGrid, ImageLightbox, ThemeToggle +├── content/ # Astro Content Collections +│ ├── members/ # Lab member profiles +│ ├── news/ # News & announcements +│ ├── research/ # Research area pages +│ ├── resources/ # Reading lists per research area +│ ├── faq/ # Categorized FAQs (Markdown files) +│ └── gallery/ # Lab event galleries +├── data/ +│ ├── publications.bib # BibTeX publication database +│ ├── software.json # Scraped software projects +│ └── sponsors.json # Scraped sponsor data +├── layouts/ +│ └── Layout.astro # Base HTML layout +├── pages/ +│ ├── index.astro # Home page (includes Sponsors) +│ ├── people.astro # People directory (tabbed by role) +│ ├── publications.astro # Searchable publications & Software tabs +│ ├── gallery/index.astro # Lab Gallery archive +│ ├── gallery/[...slug].astro # Event-specific photo grids (React Lightbox) +│ ├── faq.astro # Categorized accordion FAQ +│ ├── contact.astro # Contact page +│ ├── members/[...slug].astro # Individual member profiles +│ ├── research/index.astro # Research overview +│ ├── research/[...slug].astro # Individual research pages +│ ├── teaching.astro # Teaching homepage (list of courses) +│ └── teaching/ # Individual course pages (e.g. mla.astro) +└── plugins/ + └── rehype-figure-caption.mjs # Image caption plugin +public/ +├── images/ # Member photos, research, gallery assets, sponsor logos +├── assets/ # PDFs, manuals, and syllabi for teaching/software +└── docs/ # Resumes, documents +``` + +--- + +## Prerequisites + +- **Node.js** v20+ (or Docker) + +--- + +## Local Development + +### Node.js + +```bash +npm install +npm run dev +``` + +Open [http://localhost:4321](http://localhost:4321). + +### Docker + +```bash +docker compose up +``` + +Open [http://localhost:4321](http://localhost:4321). Stop with `docker compose down`. + +--- + +## Build & Deploy + +```bash +npm run build # Type-check + static build → dist/ +npm run preview # Preview the built site locally +``` + +The site deploys as a static site to **GitHub Pages**. + +--- + +## Content Management + +### Members (`src/content/members/`) + +Each `.md` file represents a lab member. + +```yaml +--- +name: "Jane Doe" +role: "Ph.D." # Faculty | Ph.D. | Masters | Undergraduate | Postdoc | Alumni | Visiting Student | Visiting Faculty +joinDate: "2023" +image: "/images/members/jane-doe.jpg" +email: "jdoe@asu.edu" # optional +website: "https://..." # optional +github: "https://github.com/..." # optional +linkedin: "https://..." # optional +resume: "/docs/resumes/..." # optional +researchInterests: ["Topic A", "Topic B"] # optional +isAlumni: false # optional +currentPosition: "..." # optional (for alumni) +--- + +Bio text goes here (markdown supported). +``` + +### News and Awards (`src/content/news/`) + +#### Manual Addition +Create a new `.md` file in `src/content/news/`. + +```yaml +--- +date: "2024" # Can be a full date (YYYY-MM-DD) or just the year +type: "Publication" # Award | Publication | Event | Announcement | General +description: "A concise description of the news. Supports **Markdown**." +--- +``` + +#### Automated Scraping +Run the scraper to fetch updates from the legacy site: +```bash +python scrape_news.py +``` + +### Research Areas (`src/content/research/`) + +```yaml +--- +title: "Research Area Name" +status: "Active" # Active | Extended +description: "One-line summary." +image: "/images/research/hero.jpg" # optional banner +icon: "Cpu" # Lucide icon name +order: 1 # display order +--- + +Markdown content. Supports images with captions: + +![Alt Text](/images/research/figure.png) +This text becomes a styled caption under the image (no blank line above). +``` + +### Resources / Reading Lists (`src/content/resources/`) + +```yaml +--- +researchArea: "Intelligent Transportation Systems" # must match research title exactly +resources: + - title: "Paper Title" + type: "Paper" # Paper | Book | Video | Tutorial | Tool | Publication + url: "https://..." + authors: "Authors" + description: "..." +--- +``` + +### FAQ (`src/content/faq/`) + +FAQs are managed via markdown files in the `faq` collection. + +```yaml +--- +category: "General" # Group name +icon: "💡" # Category emoji +order: 1 # Display order +items: + - question: "How do I X?" + answer: "Full answer supporting **markdown**." + externalLink: "" # Optional direct link + - question: "Link to service" + answer: "" + externalLink: "https://..." +--- +``` + +### Lab Gallery (`src/content/gallery/`) + +Showcases photos from lab events. + +```yaml +--- +title: "Lab Social 2024" +description: "Brief summary of the event." +date: 2024-03-20 +coverImage: "/images/gallery/lab-social-2024/social_1.png" +images: + - "/images/gallery/lab-social-2024/social_1.png" + - "/images/gallery/lab-social-2024/social_2.png" +location: "Tempe, AZ" +--- + +Optional detailed description of the event. +``` + +### Teaching Courses (`src/pages/teaching/`) + +Teaching courses are maintained as distinct Astro pages rather than a content collection, to allow completely custom layouts and styling per course syllabus. + +To add a new course: +1. Create a new `.astro` file inside `src/pages/teaching/` (e.g. `cse101.astro`). +2. Use the standard layout component: ` ... `. +3. Add the course link to the master list inside `src/pages/teaching.astro`. +4. Any course documents (e.g., syllabi PDF files) should be uploaded to `public/assets/teaching/` and linked via `/assets/teaching/filename.pdf`. + +### Publications (`src/data/publications.bib`) + +Managed in a BibTeX file. Key fields: +- `research` — Comma-separated tags matching research titles. +- `category` — Conference, Article, Patent, etc. +- `website` / `code` — Optional deep links. +- `url` — Paper/Slides links. Format: `http://link.com/p.pdf, pdf http://link.com/s.ppt, slides`. + +#### Software Tab +Powered by `src/data/software.json`: +```json +{ + "name": "Project Name", + "url": "https://github.com/...", + "description": "...", + "researchGroup": "AI Compilers", + "image": "/images/software/logo.png" +} +``` + +### Sponsors (`src/data/sponsors.json`) + +Displayed on the homepage. Scraped using `scrape_sponsors.py`. +```json +{ + "name": "Agency Name", + "logo": "/images/sponsors/logo.png", + "url": "https://..." +} +``` + +--- + +## Theming & UI + +- **Light/Dark Mode**: Persisted theme switch via `ThemeToggle`. +- **Interactive Gallery**: Immersive lightbox experience powered by `ImageLightbox.tsx` (React). +- **Markdown Rendering**: Answers in FAQ use `marked`. Research pages use Astro dynamic rendering. diff --git a/astro.config.mjs b/astro.config.mjs new file mode 100644 index 0000000..c0b060b --- /dev/null +++ b/astro.config.mjs @@ -0,0 +1,27 @@ +import react from '@astrojs/react'; +import tailwind from '@astrojs/tailwind'; +import { defineConfig } from 'astro/config'; +import rehypeFigureCaption from './src/plugins/rehype-figure-caption.mjs'; + +export default defineConfig({ + output: 'static', + site: 'https://MPSLab-ASU.github.io', + markdown: { + rehypePlugins: [rehypeFigureCaption], + }, + integrations: [ + react(), + tailwind({ + applyBaseStyles: false, + }), + ], + vite: { + css: { + preprocessorOptions: { + scss: { + api: 'modern-compiler', + }, + }, + }, + }, +}); diff --git a/docker-compose.yml b/docker-compose.yml new file mode 100644 index 0000000..d81a4f1 --- /dev/null +++ b/docker-compose.yml @@ -0,0 +1,10 @@ +services: + astro: + image: node:20-alpine + working_dir: /app + volumes: + - .:/app + - /app/node_modules + ports: + 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"unist-util-visit": "^5.1.0" + }, + "devDependencies": { + "@types/node": "^25.3.0", + "cheerio": "^1.2.0" + } +} diff --git a/parse_news.py b/parse_news.py new file mode 100644 index 0000000..abc90a5 --- /dev/null +++ b/parse_news.py @@ -0,0 +1,15 @@ +import os +import re + +news_dir = "src/content/news" +types = set() + +for file in os.listdir(news_dir): + if file.endswith('.md'): + with open(os.path.join(news_dir, file), 'r') as f: + content = f.read() + match = re.search(r'type:\s*"(.*?)"', content) + if match: + types.add(match.group(1)) + +print("Types found:", types) diff --git a/public/assets/software/TMAManual.pdf b/public/assets/software/TMAManual.pdf new file mode 100644 index 0000000..2e7276f Binary files /dev/null and b/public/assets/software/TMAManual.pdf differ diff --git a/public/assets/software/TTLConsistencyCheckerManual.pdf b/public/assets/software/TTLConsistencyCheckerManual.pdf new file mode 100644 index 0000000..19777b6 Binary files /dev/null and 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+
+
diff --git a/src/components/astro/MemberGrid.astro b/src/components/astro/MemberGrid.astro new file mode 100644 index 0000000..d3ce44f --- /dev/null +++ b/src/components/astro/MemberGrid.astro @@ -0,0 +1,169 @@ +--- +import { getCollection } from 'astro:content'; + +interface Props { + roleFilter?: string; + researchFilter?: string; + alumniTypeFilter?: string | string[]; + compact?: boolean; +} + +const { roleFilter, researchFilter, alumniTypeFilter, compact = false } = Astro.props; + +let allMembers = await getCollection('members'); +if (roleFilter === 'Alumni') { + allMembers = allMembers.filter(m => m.data.role === 'Alumni' || m.data.isAlumni === true); +} else if (roleFilter) { + allMembers = allMembers.filter(m => m.data.role === roleFilter); +} +if (alumniTypeFilter) { + const types = Array.isArray(alumniTypeFilter) ? alumniTypeFilter : [alumniTypeFilter]; + allMembers = allMembers.filter(m => { + if (!m.data.alumniType) return false; + const memberTypes = Array.isArray(m.data.alumniType) ? m.data.alumniType : [m.data.alumniType]; + return memberTypes.some(t => types.includes(t)); + }); +} +if (researchFilter) { + const filterLower = researchFilter.toLowerCase(); + allMembers = allMembers.filter(m => + m.data.researchInterests && + m.data.researchInterests.some(ri => ri.toLowerCase() === filterLower) + ); +} +// Determine graduation date value for sorting +const getGraduationValue = (gradStr: string | string[] | undefined): number => { + if (!gradStr) return 0; + + // If array, grab the first one or we can find the max year. Let's just find the max year. + const strs = Array.isArray(gradStr) ? gradStr : [gradStr]; + let maxValue = 0; + + for (const s of strs) { + // Example: 'Spring 2024', 'Fall 2023', '2020' + const match = s.match(/(Spring|Summer|Fall|Winter)?\s*(\d{4})/i); + if (match) { + const year = parseInt(match[2], 10); + let seasonVal = 0; + const season = (match[1] || '').toLowerCase(); + if (season === 'spring') seasonVal = 1; + else if (season === 'summer') seasonVal = 2; + else if (season === 'fall') seasonVal = 3; + else if (season === 'winter') seasonVal = 4; + + // E.g., 2024.3, 2024.1 + const val = year + (seasonVal / 10); + if (val > maxValue) { + maxValue = val; + } + } + } + return maxValue; +} + +if (roleFilter === 'Alumni' || alumniTypeFilter) { + // Sort by graduation (newest to oldest), fallback to order + allMembers.sort((a, b) => { + const valA = getGraduationValue(a.data.graduated); + const valB = getGraduationValue(b.data.graduated); + + if (valA !== valB) { + return valB - valA; // Descending + } + return (a.data.order ?? 99) - (b.data.order ?? 99); + }); +} else { + // Default sorting + allMembers.sort((a, b) => (a.data.order ?? 99) - (b.data.order ?? 99)); +} + +const roleColors: Record = { + 'Principle Investigator': 'bg-primary/10 text-primary', + 'Ph.D.': 'bg-blue-100 text-blue-700 dark:bg-blue-900/30 dark:text-blue-300', + 'Masters': 'bg-green-100 text-green-700 dark:bg-green-900/30 dark:text-green-300', + 'Postdoc': 'bg-purple-100 text-purple-700 dark:bg-purple-900/30 dark:text-purple-300', + 'Alumni': 'bg-gray-100 text-gray-600 dark:bg-gray-800 dark:text-gray-400', +}; +--- + +{allMembers.length > 0 && compact && ( + +)} + +{allMembers.length > 0 && !compact && ( +
+ {allMembers.map(async (member) => { + const { Content } = await member.render(); + return ( + + {member.data.image || member.data.photoUrl ? ( + {member.data.name} + ) : ( +
+ {member.data.name.split(' ').map((n: string) => n[0]).join('')} +
+ )} + + +

{member.data.name}

+
+ + {member.data.role} + +
+ + {(member.data.graduated || member.data.alumniType) && ( +
+

+ {member.data.graduated && (Array.isArray(member.data.graduated) + ? member.data.graduated.map((g: string) => Graduated: {g}) + : Graduated: {member.data.graduated})} +

+
+ )} + + {(member.data.university || member.data.duration) && ( +
+ {member.data.university && (Array.isArray(member.data.university) + ? member.data.university.map((u: string) =>

{u}

) + :

{member.data.university}

)} + {member.data.duration && (Array.isArray(member.data.duration) + ? member.data.duration.map((d: string) =>

{d}

) + :

{member.data.duration}

)} +
+ )} + + {member.data.currentPosition && ( +
+

{member.data.currentPosition}

+
+ )} + + {member.data.researchInterests && member.data.researchInterests.length > 0 && ( +
+

Research Areas

+
+ {member.data.researchInterests.slice(0, 3).map(tag => ( + {tag} + ))} +
+
+ )} + + {member.data.email && ( +

{member.data.email}

+ )} + + + ); + })} +
+)} diff --git a/src/components/astro/Navbar.astro b/src/components/astro/Navbar.astro new file mode 100644 index 0000000..4430943 --- /dev/null +++ b/src/components/astro/Navbar.astro @@ -0,0 +1,114 @@ +--- +import ThemeToggle from "../react/ThemeToggle"; + +const navLinks = [ + { href: "/", label: "Home" }, + { href: "/research", label: "Research" }, + { href: "/publications", label: "Publications" }, + { href: "/teaching", label: "Teaching" }, + { href: "/people", label: "People" }, + { href: "/news", label: "News" }, + { href: "/gallery", label: "Gallery" }, + { href: "/faq", label: "FAQ" }, + { href: "/contact", label: "Contact" }, +]; + +const currentPath = Astro.url.pathname; +--- + + + + diff --git a/src/components/astro/NewsSidebar.astro b/src/components/astro/NewsSidebar.astro new file mode 100644 index 0000000..e354de7 --- /dev/null +++ b/src/components/astro/NewsSidebar.astro @@ -0,0 +1,64 @@ +--- +const { currentPath } = Astro.props; + +const links = [ + { + href: "/news", + label: "Lab Updates", + icon: "M19 20H5a2 2 0 01-2-2V6a2 2 0 012-2h10a2 2 0 012 2v1m2 13a2 2 0 01-2-2V7m2 13a2 2 0 002-2V9a2 2 0 00-2-2h-2m-4-3H9M7 16h6M7 8h6v4H7V8z", + }, + { + href: "/news/awards", + label: "Awards", + icon: "M5 3v4M3 5h4M6 17v4m-2-2h4m5-16l2.286 6.857L21 12l-5.714 2.143L13 21l-2.286-6.857L5 12l5.714-2.143L13 3z", + }, +]; + +// Normalize paths for exact matching (e.g., removing trailing slashes) +const normalizePath = (p: string) => p.replace(/\/$/, "") || "/"; +const normalizedCurrent = normalizePath(currentPath); +--- + + diff --git a/src/components/react/GalleryGrid.tsx b/src/components/react/GalleryGrid.tsx new file mode 100644 index 0000000..2d3fc42 --- /dev/null +++ b/src/components/react/GalleryGrid.tsx @@ -0,0 +1,52 @@ +import React, { useState } from 'react'; +import ImageLightbox from './ImageLightbox'; + +interface GalleryGridProps { + images: string[]; +} + +const GalleryGrid: React.FC = ({ images }) => { + const [isOpen, setIsOpen] = useState(false); + const [selectedIndex, setSelectedIndex] = useState(0); + + const openLightbox = (index: number) => { + setSelectedIndex(index); + setIsOpen(true); + }; + + return ( +
+
+ {images.map((image, index) => ( +
openLightbox(index)} + > + {`Gallery +
+ + + + + +
+
+ ))} +
+ + setIsOpen(false)} + /> +
+ ); +}; + +export default GalleryGrid; diff --git a/src/components/react/ImageLightbox.tsx b/src/components/react/ImageLightbox.tsx new file mode 100644 index 0000000..ebbb464 --- /dev/null +++ b/src/components/react/ImageLightbox.tsx @@ -0,0 +1,94 @@ +import { ChevronLeft, ChevronRight, X, ZoomIn, ZoomOut } from 'lucide-react'; +import React, { useCallback, useEffect, useState } from 'react'; + +interface ImageLightboxProps { + images: string[]; + initialIndex?: number; + isOpen: boolean; + onClose: () => void; +} + +const ImageLightbox: React.FC = ({ images, initialIndex = 0, isOpen, onClose }) => { + const [currentIndex, setCurrentIndex] = useState(initialIndex); + const [isZoomed, setIsZoomed] = useState(false); + + const handleNext = useCallback(() => { + setCurrentIndex((prev) => (prev + 1) % images.length); + setIsZoomed(false); + }, [images.length]); + + const handlePrev = useCallback(() => { + setCurrentIndex((prev) => (prev - 1 + images.length) % images.length); + setIsZoomed(false); + }, [images.length]); + + const handleKeyDown = useCallback((e: KeyboardEvent) => { + if (e.key === 'Escape') onClose(); + if (e.key === 'ArrowRight') handleNext(); + if (e.key === 'ArrowLeft') handlePrev(); + }, [onClose, handleNext, handlePrev]); + + useEffect(() => { + if (isOpen) { + document.body.style.overflow = 'hidden'; + window.addEventListener('keydown', handleKeyDown); + } else { + document.body.style.overflow = 'unset'; + } + return () => window.removeEventListener('keydown', handleKeyDown); + }, [isOpen, handleKeyDown]); + + if (!isOpen) return null; + + return ( +
+ + +
+ {currentIndex + 1} / {images.length} +
+ + + + + +
+ {`Gallery setIsZoomed(!isZoomed)} + /> +
+ +
+ + +
+
+ ); +}; + +export default ImageLightbox; diff --git a/src/components/react/PublicationCard.tsx b/src/components/react/PublicationCard.tsx new file mode 100644 index 0000000..83cbd44 --- /dev/null +++ b/src/components/react/PublicationCard.tsx @@ -0,0 +1,224 @@ +import { Check, Clipboard, Code, FileText, Image as ImageIcon, Link, PlaySquare, Presentation, Quote } from 'lucide-react'; +import { useState } from 'react'; + +export interface Publication { + citationKey: string; + entryType: string; + entryTags: { + author?: string; + title?: string; + booktitle?: string; + journal?: string; + year?: string; + research?: string; + url?: string; + website?: string; + code?: string; + category?: string; + }; +} + +interface PublicationCardProps { + pub: Publication; + validTags?: string[]; + onTypeClick?: (type: string) => void; + onTagClick?: (tag: string) => void; +} + +export default function PublicationCard({ pub, validTags = [], onTypeClick, onTagClick }: PublicationCardProps) { + const [expandedBibtex, setExpandedBibtex] = useState(null); + const [copiedKey, setCopiedKey] = useState(null); + + const getVenue = (p: Publication) => p.entryTags.booktitle || p.entryTags.journal || ''; + + const parseUrls = (urlString?: string) => { + if (!urlString) return []; + const parts = urlString.split(/(?=https?:\/\/)/); + return parts.map(p => { + const raw = p.trim(); + if (!raw) return null; + const commaIdx = raw.indexOf(','); + if (commaIdx !== -1) { + const url = raw.substring(0, commaIdx).trim(); + let label = raw.substring(commaIdx + 1).trim() || 'Link'; + + const lowerLabel = label.toLowerCase(); + if (lowerLabel.includes('pdf')) label = 'Paper'; + else if (lowerLabel.includes('ppt') || lowerLabel.includes('slide')) label = 'Slides'; + + return { url, label }; + } + return { url: raw, label: 'Link' }; + }).filter(Boolean) as { url: string, label: string }[]; + }; + + const getIconForLabel = (label: string) => { + const l = label.toLowerCase(); + if (l.includes('pdf')) return ; + if (l.includes('slide') || l.includes('ppt')) return ; + if (l.includes('poster')) return ; + if (l.includes('teaser') || l.includes('video')) return ; + return ; + }; + + const generateBibtex = (pub: Publication) => { + let result = `@${pub.entryType}{${pub.citationKey},\n`; + for (const [key, value] of Object.entries(pub.entryTags)) { + if (value !== undefined && value !== null && key !== 'url' && key !== 'website' && key !== 'code') { + result += ` ${key} = {${value}},\n`; + } + } + result += `}`; + return result; + }; + + const handleCopyBibtex = async (pub: Publication) => { + const bibtex = generateBibtex(pub); + try { + await navigator.clipboard.writeText(bibtex); + setCopiedKey(pub.citationKey); + setTimeout(() => setCopiedKey(null), 2000); + } catch (err) { + console.error('Failed to copy bibtex: ', err); + } + }; + + return ( +
+
+

+ {pub.entryTags.title || pub.citationKey} +

+

+ {pub.entryTags.author?.replace(/ and /ig, '; ')} +

+
+ + {pub.entryTags.year} + + {pub.entryTags.category && ( + onTypeClick ? ( + + ) : ( + + {pub.entryTags.category} + + ) + )} + + {getVenue(pub)} + +
+ {pub.entryTags.research && ( +
+ {pub.entryTags.research.split(',').map(t => t.trim()) + .filter(t => validTags.length === 0 || validTags.some(v => v.toLowerCase() === t.toLowerCase())) + .map(kw => ( + onTagClick ? ( + + ) : ( + + {kw} + + ) + ))} +
+ )} +
+
+
+ {pub.entryTags.code && ( + + + Code + + )} + {pub.entryTags.website && ( + + + Website + + )} + {parseUrls(pub.entryTags.url).map((resource, i) => ( + + {getIconForLabel(resource.label)} + {resource.label} + + ))} + +
+
+ + {/* Expandable BibTeX Output */} + { + expandedBibtex === pub.citationKey && ( +
+
+ BibTeX + +
+ 
+                            {generateBibtex(pub)}
+
+
+ ) + } +
+ ); +} diff --git a/src/components/react/PublicationSearch.tsx b/src/components/react/PublicationSearch.tsx new file mode 100644 index 0000000..e4327b6 --- /dev/null +++ b/src/components/react/PublicationSearch.tsx @@ -0,0 +1,208 @@ +import Fuse from 'fuse.js'; +import { Filter, Search } from 'lucide-react'; +import { useEffect, useMemo, useState } from 'react'; +import type { Publication } from './PublicationCard'; +import PublicationCard from './PublicationCard'; + +interface Props { + papers: Publication[]; + validAuthors?: string[]; + validTags?: string[]; +} + +export default function PublicationSearch({ papers, validAuthors = [], validTags = [] }: Props) { + const [query, setQuery] = useState(''); + const [yearFilter, setYearFilter] = useState(''); + const [authorFilter, setAuthorFilter] = useState(''); + const [typeFilter, setTypeFilter] = useState(''); + const [tagFilter, setTagFilter] = useState(''); + const [currentPage, setCurrentPage] = useState(1); + const ITEMS_PER_PAGE = 20; + + // Initialize query and tag filter from URL parameters if present + useEffect(() => { + if (typeof window !== 'undefined') { + const params = new URLSearchParams(window.location.search); + const q = params.get('q'); + if (q) { + setQuery(q); + } + const tag = params.get('tag'); + if (tag) { + setTagFilter(tag); + } + } + }, []); + + // Reset to page 1 when any filter changes + useEffect(() => { + setCurrentPage(1); + }, [query, yearFilter, authorFilter, typeFilter, tagFilter]); + + const years = useMemo(() => { + const y = [...new Set(papers.map(p => p.entryTags.year).filter(Boolean))].sort().reverse(); + return y as string[]; + }, [papers]); + + const authors = useMemo(() => { + return [...validAuthors].sort(); + }, [validAuthors]); + + const types = useMemo(() => { + return [...new Set(papers.map(p => p.entryTags.category).filter(Boolean))].sort() as string[]; + }, [papers]); + + const tags = useMemo(() => { + return [...validTags].sort(); + }, [validTags]); + + const fuse = useMemo(() => new Fuse(papers, { + keys: [ + { name: 'entryTags.title', weight: 0.4 }, + { name: 'entryTags.author', weight: 0.3 }, + { name: 'entryTags.research', weight: 0.2 }, + { name: 'entryTags.year', weight: 0.1 }, + { name: 'entryTags.booktitle', weight: 0.1 }, + { name: 'entryTags.journal', weight: 0.1 }, + ], + threshold: 0.4, + includeScore: true, + }), [papers]); + + const filtered = useMemo(() => { + let results = query ? fuse.search(query).map(r => r.item) : papers; + if (yearFilter) { + results = results.filter(p => p.entryTags.year === yearFilter); + } + if (authorFilter) { + results = results.filter(p => p.entryTags.author?.includes(authorFilter)); + } + if (typeFilter) { + results = results.filter(p => p.entryTags.category === typeFilter); + } + if (tagFilter) { + results = results.filter(p => p.entryTags.research?.includes(tagFilter)); + } + return results; + }, [query, yearFilter, authorFilter, typeFilter, tagFilter, papers, fuse]); + + const totalPages = Math.ceil(filtered.length / ITEMS_PER_PAGE); + const startIndex = (currentPage - 1) * ITEMS_PER_PAGE; + const paginatedResults = useMemo(() => { + return filtered.slice(startIndex, startIndex + ITEMS_PER_PAGE); + }, [filtered, startIndex]); + + return ( +
+ {/* Search */} +
+ + setQuery(e.target.value)} + className="w-full pl-10 pr-4 py-3 rounded-xl border bg-[var(--color-bg-card)] text-[var(--color-text)] border-[var(--color-border)] focus:ring-2 focus:ring-[var(--color-primary)] focus:border-transparent outline-none transition-all" + /> +
+ + {/* Filters */} +
+
+ + +
+
+ + +
+
+ + +
+ +
+ + +
+
+ + {/* Results Count */} +

+ Showing {filtered.length > 0 ? startIndex + 1 : 0}-{Math.min(startIndex + ITEMS_PER_PAGE, filtered.length)} of {filtered.length} publications +

+ + {/* Publication List */} +
+ {paginatedResults.map(pub => ( + + ))} +
+ + {totalPages > 1 && ( +
+ + + Page {currentPage} of {totalPages} + + +
+ )} + + { + filtered.length === 0 && ( +
+ +

No publications match your search.

+
+ ) + } +
+ ); +} diff --git a/src/components/react/SoftwareCard.tsx b/src/components/react/SoftwareCard.tsx new file mode 100644 index 0000000..956d155 --- /dev/null +++ b/src/components/react/SoftwareCard.tsx @@ -0,0 +1,62 @@ +import { Code, ExternalLink } from 'lucide-react'; + +interface SoftwareProject { + name: string; + url: string; + description: string; + researchGroup: string; + image: string; +} + +export default function SoftwareCard({ project }: { project: SoftwareProject }) { + // Clean up leading colons/dashes from description + let desc = project.description.trim(); + if (desc.startsWith(':') || desc.startsWith('-')) { + desc = desc.substring(1).trim(); + } + + const isGithub = project.url.toLowerCase().includes("github.com"); + + return ( +
+
+ {/* Header: image + title */} +
+ {project.image && ( + {project.name} + )} +
+

+ {project.name} +

+ + {project.researchGroup} + +
+
+ +

+ {desc} +

+
+ +
+ ); +} diff --git a/src/components/react/ThemeToggle.tsx b/src/components/react/ThemeToggle.tsx new file mode 100644 index 0000000..cd4312c --- /dev/null +++ b/src/components/react/ThemeToggle.tsx @@ -0,0 +1,27 @@ +import { Moon, Sun } from 'lucide-react'; +import { useEffect, useState } from 'react'; + +export default function ThemeToggle() { + const [isDark, setIsDark] = useState(false); + + useEffect(() => { + setIsDark(document.documentElement.classList.contains('dark')); + }, []); + + const toggle = () => { + const next = !isDark; + setIsDark(next); + document.documentElement.classList.toggle('dark', next); + localStorage.setItem('theme', next ? 'dark' : 'light'); + }; + + return ( + + ); +} diff --git a/src/content/config.ts b/src/content/config.ts new file mode 100644 index 0000000..cb4d881 --- /dev/null +++ b/src/content/config.ts @@ -0,0 +1,89 @@ +import { defineCollection, z } from 'astro:content'; + +const members = defineCollection({ + type: 'content', + schema: z.object({ + name: z.string(), + role: z.enum(['Principle Investigator', 'Ph.D.', 'Masters', 'Undergraduate', 'Alumni', 'Postdoc', 'Visiting Student', 'Visiting Faculty']), + photoUrl: z.string().optional(), + joinDate: z.string(), + email: z.string().optional(), + website: z.string().optional(), + github: z.string().optional(), + linkedin: z.string().optional(), + portfolio: z.string().optional(), + resume: z.string().optional(), + researchInterests: z.array(z.string()).optional(), + order: z.number().optional(), + image: z.string().optional(), + isAlumni: z.boolean().optional(), + alumniType: z.union([z.string(), z.array(z.string())]).optional(), + currentPosition: z.string().optional(), + graduated: z.union([z.string(), z.array(z.string())]).optional(), + university: z.union([z.string(), z.array(z.string())]).optional(), + duration: z.union([z.string(), z.array(z.string())]).optional(), + }), +}); + +const news = defineCollection({ + type: 'content', + schema: z.object({ + date: z.union([z.string(), z.date(), z.number()]), + type: z.enum(['Award', 'Publication', 'Event', 'Announcement', 'General']), + description: z.string(), + }), +}); + +const research = defineCollection({ + type: 'content', + schema: z.object({ + title: z.string(), + status: z.enum(['Active', 'Extended']), + description: z.string(), + image: z.string().optional(), + icon: z.string().optional(), + order: z.number().optional(), + }), +}); + +const resources = defineCollection({ + type: 'content', + schema: z.object({ + researchArea: z.string(), + resources: z.array(z.object({ + title: z.string(), + type: z.enum(['Paper', 'Book', 'Video', 'Tutorial', 'Tool', 'Publication']), + url: z.string().optional(), + authors: z.string().optional(), + description: z.string().optional(), + })), + }), +}); + +const faq = defineCollection({ + type: 'content', + schema: z.object({ + category: z.string(), + icon: z.string().optional(), + order: z.number().optional(), + items: z.array(z.object({ + question: z.string(), + answer: z.string().optional(), + externalLink: z.string().optional(), + })), + }), +}); + +const gallery = defineCollection({ + type: 'content', + schema: z.object({ + title: z.string(), + description: z.string(), + date: z.date(), + coverImage: z.string(), + images: z.array(z.string()), + location: z.string().optional(), + }), +}); + +export const collections = { members, news, research, resources, faq, gallery }; diff --git a/src/content/faq/administrative.md b/src/content/faq/administrative.md new file mode 100644 index 0000000..9a952d0 --- /dev/null +++ b/src/content/faq/administrative.md @@ -0,0 +1,34 @@ +--- +category: Administrative +icon: 📋 +order: 3 +items: +- question: How can I apply for a TA position? + answer: '' + externalLink: http://cidse.engineering.asu.edu/forstudent/graduate/teachingresearch-assistantships/ +- question: How can I contact my academic advisor? + answer: '' + externalLink: https://students.asu.edu/advising/directory +- question: How do I file an override request for a CSE/CEN course? + answer: '' + externalLink: http://cidse.engineering.asu.edu/forstudent/academic-advising/cidse-override-policy/ +- question: How can I enroll in a thesis/practicum/continuing registration course? + answer: '' + externalLink: https://cidse.engineering.asu.edu/forstudent/graduate/gradforms/ +- question: How do I contact ASU HR? + answer: '' + externalLink: https://cfo.asu.edu/hr +- question: How can I get assistance with my payroll or tax documents? + answer: '**Where to access my tax documents?** + + + Please go to MyASU -> Staff -> My Employment -> Payroll -> Tax Information -> W4 Tax Information (Federal) Please go to MyASU -> Staff -> My Employment -> Payroll -> Tax Information ->  A-4 Tax Information + (Arizona) + + + **How can I get information regarding ASU payroll?** + + + Please visit https://cfo.asu.edu/payroll or call on (480) 965-3601. ASU payroll is located at USB building.' + externalLink: '' +--- diff --git a/src/content/faq/general.md b/src/content/faq/general.md new file mode 100644 index 0000000..a4721e3 --- /dev/null +++ b/src/content/faq/general.md @@ -0,0 +1,157 @@ +--- +category: General +icon: 💡 +order: 4 +items: +- question: I am new to the lab; what do I need to do? + answer: '' + externalLink: https://docs.google.com/document/d/1Ab9FCx-FOphzkFxTyzaQuN4R9RKOV2Z0f9BR1AVK_Lc/edit?usp=sharing +- question: How to use Docker on Linux Servers? + answer: '' + externalLink: https://youtu.be/fqMOX6JJhGo?si=FXsav7SRqlekc9-x +- question: Is there a presentation template for lab meetings? + answer: '' + externalLink: https://docs.google.com/document/d/18S5cAicIsTDq7azR2ZExbGHxw7BI_koHPYK7cG8VY2U/edit?usp=sharing +- question: Who do I contact if I have a facility service request? + answer: '' + externalLink: https://cfo.asu.edu/requests-for-service +- question: How can I create my public web page @ ASU domain? + answer: 'Firstly, follow the link of a short tutorial, which shows steps to get a website using your ASURITE user name/ASUID. Create a website at ASU + + + Once, you have activated your site and reach to the MyFiles as described into the tutorial, follow the steps below – 1. You will see Folders Section in MyFiles. Locate www folder and click on it. 2. + Now you have reached the place where you can manage file and folders, related to your public webpage. 3. Access your public site using http://www.public.asu.edu/~ASURITE where ASURITE is your ASURITE + user name. 4. You will see that you can manage homepage of your public webpage using index.html, inside www folder. Publicwebsetup.html is for future reference. You can always access it through http://www.public.asu.edu/~ASURITE/publicwebsetup.html. + By default, index.html and publicwebsetup.html will be the same. 5. Modify index.html and add/remove files to the filespace into www folder. Have a decent public webpage. Good Luck!' + externalLink: '' +- question: Where can I apply for graduate fellowships? + answer: '**ASU Awards, Scholarships, and Fellowships** + + + Graduate College Fellowships and Awards + + + Fellowships and Scholarships from Ira A. Fultons Schools of Engineering + + + ASU Master’s Opportunity for Research in Engineering (MORE) + + + ASU Summer Research Internships (SURI) + + + ASU Fulton Undergraduate Research Initiative (FURI) + + + Fellowship list from ASU School of Computing and Augmented Intelligence (SCAI) + + + ASU Graduate and Professional Student Association (GPSA) Awards + + + ASU Scholarships Portal + + + **External lists of Fellowship Applications** + + + List from UMD CS + + + List from CMU CS + + + List from Caltech Grad Students Office + + + List from FAU Grad College' + externalLink: '' +- question: Which travel grants are available, and how should I apply to them? + answer: 'ASU Resources + + + GPSA Travel Grant – Travel Grants | Educational Outreach and Student Services + + + Graduate College Travel Grant – Travel Awards | Graduate College + + + SCAI Travel Grant – SCAI Conference Funding Application (Available only to Ph.D. students) + + + Usually, the organizations holding the conferences also provide travel grants, but this is not guaranteed to all conferences.' + externalLink: '' +- question: How do I contribute to the SCAI PhD Newsletter? + answer: '' + externalLink: https://bit.ly/phdnews +- question: What do I do if I get fake mail? + answer: Email [email protected] + externalLink: '' +- question: I need additional support from CIDSE IT. + answer: 'Where to submit CIDSE IT requests? For IT issues please submit a “ticket” by going to: http://links.asu.edu/SCAIIT/ + + + Once ticket is submitted your request will be in the queue and handled on a first-come-first-serve basis. + + + Please bookmark this address and start using it as soon as you can.' + externalLink: '' +- question: How do I get door access to certain rooms in the Centerpoint Building? + answer: 'If you are a registered ASU student or faculty member and need keycard access to the Centerpoint Building and specific labs/rooms, then visit: https://ets.engineering.asu.edu/keyless-door-entry-system-isaac/ + and fill out the appropriate information by clicking on the link for Tempe. You can do so by adding a new request. The request must be approved by the designated faculty for the facility that you are + requesting access to. + + + If you are unable to access certain doors in the Centerpoint Building, please email: [email protected] and copy Dr. Aviral.' + externalLink: '' +- question: How can I get a furniture accommodation? + answer: 'If you have ergonomic needs for particular furniture, ASU has a group that can assess such needs on an individual basis.  This is the only option I have to replace chairs in the lab as grant + funding cannot cover office furniture. Please review the following website. + + + Workplace accommodations | Arizona State University ( asu.edu ) For the students that are having issues the next steps would be to reach out to the following email addresses or phone number. [email protected] + or call 480-727-1770' + externalLink: '' +- question: I need a vacuum cleaner in the lab; where can I get access? + answer: '' + externalLink: https://cfo.asu.edu/requests-for-service +- question: Who do I contact for lab website-related queries? – Atharva + answer: 'LinkedIn + + + GitHub + + + I’m a Ph.D in Computer Science Student at ASU working in Compiler Design and Machine Learning Accelerators @MPS-Lab . Previously I worked as a Machine Learning Intern at AMD and HackerRank . + + + **Tech Stack**' + externalLink: '' +- question: Who do I contact for organizing a social event in the lab? – Kaustubh + answer: 'LinkedIn + + + GitHub + + + I have developed my core foundation in Computer Vision and AI, which presented opportunities for research and solution development in industrial settings, particularly with Siemens. Balancing technical + work with a commitment to my education, my path has evolved from organizing and instructing in learning programs to contributing to corporate roles in a research capacity, focusing on practical applications + and collaborative growth in Computer Vision and AI. + + + I am currently working on building a deeper understanding of Vision Transformers and their applications in Machine Learning Accelerator and Intelligent Traffic management settings. + + + I aim to pursue an Applied research role with an aptitude for Full-Stack Deep Learning.' + externalLink: '' +- question: I have not completed my Master’s Thesis, and I have completed two years. What should I do? + answer: Register 1 credit for the continued registration course. Process details can be found here – Continued Registration / Course Permission or Override requests . The same link can be used for Independent + Study and Internship requests. + externalLink: https://sites.google.com/asu.edu/scaigraduateprogramresources/forms-procedures +- question: I just published a paper; what should I do? + answer: '' + externalLink: https://docs.google.com/document/d/1K_1mURQnnEu_mCREu3U8CnjahDePJCcXELCELBmn0eE/edit?usp=sharing +- question: I am ready to schedule my Master’s thesis defense and graduate; what do I do? + answer: '' + externalLink: https://docs.google.com/document/d/1hUeRbJ9wAFbcMuKed6zrEUwu0rCZqmI7YVArTFDItLE/edit?usp=sharing +--- diff --git a/src/content/faq/on-campus-resources.md b/src/content/faq/on-campus-resources.md new file mode 100644 index 0000000..dad6ed1 --- /dev/null +++ b/src/content/faq/on-campus-resources.md @@ -0,0 +1,33 @@ +--- +category: On-Campus Resources +icon: 🏫 +order: 2 +items: +- question: Is there a way to get graduate/academic writing support at ASU? + answer: '' + externalLink: https://tutoring.asu.edu/graduate-writing-centers +- question: Where do I apply for on-campus jobs at ASU? + answer: '' + externalLink: https://students.asu.edu/employment/search +- question: If I have an issue with my computer or printer or need some cables or equipment, who should I contact? + answer: 'Where to submit CIDSE IT requests? For IT issues please submit a “ticket” by going to: http://links.asu.edu/SCAIIT/ + + + Once ticket is submitted your request will be in the queue and handled on a first-come-first-serve basis. + + + Please bookmark this address and start using it as soon as you can.' + externalLink: '' +- question: How can I connect with the marketing and communication people ? + answer: '' + externalLink: https://engineering.asu.edu/comm/ +- question: What are the counseling services available? + answer: '' + externalLink: https://eoss.asu.edu/counseling +- question: How do I create an account to use ASU Research Computing resources? Visit the “create an account” link and click on “I would like to register for an account “. + answer: '' + externalLink: https://asurc.atlassian.net/wiki/spaces/RC/overview +- question: How do I use the ASU Research Computing resources? Visit the New User Guide . + answer: '' + externalLink: https://asurc.atlassian.net/wiki/spaces/RC/pages/1905721457/New+User+Guide +--- diff --git a/src/content/faq/research.md b/src/content/faq/research.md new file mode 100644 index 0000000..e59e96e --- /dev/null +++ b/src/content/faq/research.md @@ -0,0 +1,109 @@ +--- +category: Research +icon: 📝 +order: 1 +items: +- question: How do I begin writing a paper? + answer: 'To start with: do not think that you will write a paper in one shot. Writing is a process, and has to be done in phases. There are three main phases of writing, i) Outlining, ii) Drafting, and + iii) Editing. + + + **Outlining:** + + Outlining is the phase when you write in bullets. You do not need to write complete sentences, just phrases are enough. The idea is to write bullets about what you are going to write. Try and fix the + structure of the paper, write down the sections and subsections, but inside them there are no sentences, just bullets. Your arguments, and the flow of the arguments are the main thing that you are trying + to fix. Once you have a version of the outline, then we iterate on the outline and refine it, until the story is set. It is must easier to iterate on outline, rather than writing, because i) outline + is smaller, so you can see and think about all of it at once, and ii) fixing it is much easier than fixing writing. + + + **Drafting:** + + Once the outline is set, then start converting bullets in paragraphs, and complete sentences. We iterate on draft, so that the idea is conveyed as accurately as possible. + + + **Editing:** + + Editing is the phase of going over your final draft, and fixing grammatical and sentence construction errors. + + + As you can see, the most important phase in technical writing is the outlining phase. Once that is fixed, rest is pretty fast.' + externalLink: '' +- question: Can I refer to a pre-writing resource to start the paper draft? + answer: '' + externalLink: https://docs.google.com/document/d/1nkCSMWl_f9kFp3DG34jDnLRZrdRqbevrF0dJwKdeJB4/edit?usp=sharing +- question: How should I review a paper? + answer: 'Write your review in 3 sections: 1. Summary of the paper in your words. 2. The plus points of the paper. 3. Concerns about the paper. 4. Evaluate the paper (on a scale of 1-10, with 10 being + the best). + + + Writing the plus points of a well-written paper is usually easy since that is the author’s primary job. If you are finding this hard, then the paper is clearly bad! + + + Spend your time in finding all the holes in the paper. There can be several shortcomings in the paper. Categorize them in major and minor concerns: Examples of major concerns: 1. Are assumptions wrong/unrealistic? + 2. Fair comparison against the latest related work? 3. Not discussed all the relevant related work? 4. State the contributions of the paper clearly? 5. Experiments must prove their contribution, not + something else 6. Is the problem important, or made up? + + + Examples of minor concerns: 1. Spelling mistakes 2. Grammar 3. Writing style' + externalLink: '' +- question: When and where can I submit my paper? + answer: '' + externalLink: https://docs.google.com/document/d/1BicNfbhI96Ubx_-XYTp6YjTZoc9ZRCHszbQxTQlQUbY/edit?usp=sharing +- question: Where should I write my paper? + answer: '' + externalLink: https://www.overleaf.com/ +- question: What should I do after my thesis is completed or a paper gets accepted? + answer: '' + externalLink: https://docs.google.com/document/d/1K_1mURQnnEu_mCREu3U8CnjahDePJCcXELCELBmn0eE/edit?usp=sharing +- question: What are some scholarships/research awards that I can apply to? + answer: '**Corporate Research Programs** + + + NVIDIA Academic Grant Program – Submit Anytime + + + Samsung Research Collaboration Program (SRP) – Feb + + + Samsung Advanced Institute of Technology (SAIT) Collaboration – Aug + + + Google Academic Research Awards (GARA) – July + + + IBM Ph.D. Fellowship Program – July + + + Apple Scholars in AI/ML PhD Fellowship – Deadline TBA + + + **External Fellowships & Scholarships** + + + Quad Fellowship – March 3, 2025 + + + Chateaubriand Fellowship Program – January + + + Mellon/ACLS Dissertation Innovation Fellowship – October + + + ACI Foundation Fellowships & Scholarships – November + + + John Ries Scholarship (ESCSI) – Deadline TBA + + + ASA Fellowships & Grants – Varies (check site) + + + Sigma Xi Grants-in-Aid of Research (GIAR) – March (Spring) / October (Fall) + + + Link Foundation Modeling, Simulation, and Training Fellowship – February' + externalLink: '' +- question: 'If you’re publishing papers in Open Access Journals , you can apply for funding here: ASU Open Access Publishing Fund .' + answer: '' + externalLink: https://doaj.org/ +--- diff --git a/src/content/gallery/dac-conference-2025.md b/src/content/gallery/dac-conference-2025.md new file mode 100644 index 0000000..108cb7f --- /dev/null +++ b/src/content/gallery/dac-conference-2025.md @@ -0,0 +1,14 @@ +--- +title: Design Automation Conference 2025 +description: Atharva and Kaustubh at DAC 2025 who were accepted to attend the conference as part of the Young Fellow Program. +date: 2025-06-24 +coverImage: /images/gallery/dac-2025/dac_1.jpeg +images: + - /images/gallery/dac-2025/dac_1.jpeg + - /images/gallery/dac-2025/dac_2.jpeg + - /images/gallery/dac-2025/dac_3.jpeg + - /images/gallery/dac-2025/dac_4.jpeg +location: San Francisco, CA +--- + +Atharva and Kaustubh at DAC 2025 who were accepted to attend the conference as part of the Young Fellow Program. Atharva presented his work on DSP-MLIR and Kaustubh presented his work on IncidentNet at the conference. diff --git a/src/content/members/abhinav-kumar.md b/src/content/members/abhinav-kumar.md new file mode 100644 index 0000000..d8e22bd --- /dev/null +++ b/src/content/members/abhinav-kumar.md @@ -0,0 +1,13 @@ +--- +name: "Abhinav Kumar" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/abhinav-kumar-96504a75/" +order: 5 +image: "/images/members/abhinav-kumar.jpeg" +isAlumni: true +alumniType: "Master’s Graduate" +graduated: "Fall 2024" +--- + +DSP-MLIR: A Compiler for Digital Signal Processing in MLIR diff --git a/src/content/members/abhishek-risheekesan.md b/src/content/members/abhishek-risheekesan.md new file mode 100644 index 0000000..03ee962 --- /dev/null +++ b/src/content/members/abhishek-risheekesan.md @@ -0,0 +1,14 @@ +--- +name: "Abhishek Risheekesan" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/abhishek-rhisheekesan-54753020" +order: 5 +image: "/images/members/abhishek-risheekesan.jpg" +isAlumni: true +currentPosition: "Engineering Manager, Intel Labs, Bangalore, India" +graduated: "Spring 2013" +alumniType: "Master’s Graduate" +--- + +Quantitative Evaluation of Control-flow based Soft Error Protection Mechanisms diff --git a/src/content/members/adam-awale.md b/src/content/members/adam-awale.md new file mode 100644 index 0000000..a99a6a0 --- /dev/null +++ b/src/content/members/adam-awale.md @@ -0,0 +1,13 @@ +--- +name: "Adam Awale" +role: "Ph.D." +joinDate: "2024" +github: "https://github.com/awaleadam" +linkedin: "https://www.linkedin.com/in/adam-awale/" +resume: "/docs/resumes/adam-awale.pdf" +order: 2 +image: "/images/members/adam-awale.jpeg" +researchInterests: ["Machine Learning Acceleration"] +--- + +As a passionate Computer Engineering PhD student at Arizona State University, I bring a wealth of experience in software development, research, and teaching. My electrical and computer engineering journey began at the University of Arizona, where I earned both my bachelor’s and master’s degrees. With a strong foundation in programming languages like Python, C++, and Java, I’ve contributed to cutting-edge projects in RISC-V systems, machine learning, and FPGA design. My professional experience spans roles at General Motors, Photometrics, and Microchip, where I’ve consistently improved processes and implemented innovative solutions. As I continue my doctoral studies, I’m excited to push the boundaries of computer engineering and contribute to groundbreaking research in the field. diff --git a/src/content/members/akhilanand.md b/src/content/members/akhilanand.md new file mode 100644 index 0000000..3f36f3a --- /dev/null +++ b/src/content/members/akhilanand.md @@ -0,0 +1,13 @@ +--- +name: "Akhil Anand" +role: "Undergraduate" +joinDate: "2024" +github: "https://github.com/kel404x" +linkedin: "https://www.linkedin.com/in/akhil-a-576b56288/" +resume: "/docs/resumes/akhilanand.pdf" +order: 4 +image: "/images/members/akhilanand.jpg" +researchInterests: ["Quantum Machine Learning"] +--- + +I’m a computer science undergraduate exploring MLIR as part of my research. I’mfascinated by how computers work under the hood—something we often take for granted. My interests lie in deep learning, compilers, and cryptography, and I am eagerto explore the fundamental aspects of computing in greater depth. diff --git a/src/content/members/aman-singh.md b/src/content/members/aman-singh.md new file mode 100644 index 0000000..6c4d378 --- /dev/null +++ b/src/content/members/aman-singh.md @@ -0,0 +1,13 @@ +--- +name: "Aman Singh" +role: "Masters" +joinDate: "2024" +github: "https://github.com/amanyagami" +linkedin: "https://www.linkedin.com/in/amanyagami" +resume: "/docs/resumes/aman-singh.pdf" +order: 3 +image: "/images/members/aman-singh.jpg" +researchInterests: ["Reliability for Machine Learning"] +--- + +Portfolio –Aman Singh | Computer Systems diff --git a/src/content/members/amit-pabalkar.md b/src/content/members/amit-pabalkar.md new file mode 100644 index 0000000..8b7a105 --- /dev/null +++ b/src/content/members/amit-pabalkar.md @@ -0,0 +1,14 @@ +--- +name: "Amit Pabalkar" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/amit-pabalkar-46007b3" +order: 5 +image: "/images/members/amit-pabalkar.jpg" +isAlumni: true +currentPosition: "Principal System Software Engineer at Nvidia, Santa Clara, California" +graduated: "Spring 2008" +alumniType: "Master’s Graduate" +--- + +A Dynamic Code Mapping Technique for Scratch Pad Memories in Embedded Systems diff --git a/src/content/members/arun-kannan.md b/src/content/members/arun-kannan.md new file mode 100644 index 0000000..a194d65 --- /dev/null +++ b/src/content/members/arun-kannan.md @@ -0,0 +1,14 @@ +--- +name: "Arun Kannan" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/arunkannan" +order: 5 +image: "/images/members/arun-kannan.jpg" +isAlumni: true +currentPosition: "Software Architect and Engineering Manager at Apple, Cupertino, California" +graduated: "Spring 2008" +alumniType: "Master’s Graduate" +--- + +A Software-Only Solution for Stack Management on Systems with Scratch Pad Memory diff --git a/src/content/members/atharva-khedkar.md b/src/content/members/atharva-khedkar.md new file mode 100644 index 0000000..86e7a1b --- /dev/null +++ b/src/content/members/atharva-khedkar.md @@ -0,0 +1,14 @@ +--- +name: "Atharva Khedkar" +role: "Ph.D." +email: "atharva.khedkar@asu.edu" +joinDate: "2024" +github: "http://github.com/atharvaKhedkar" +linkedin: "http://www.linkedin.com/in/atharvakhedkar/" +resume: "/docs/resumes/atharva-khedkar.pdf" +order: 2 +image: "/images/members/atharva-khedkar.jpg" +researchInterests: ["AI-driven Multi-Level Compilers"] +--- + +I’m a Ph.D in Computer Science Student at ASU working in Compiler Design and Machine Learning Accelerators@MPS-Lab. Previously I worked as a Machine Learning Intern atAMDandHackerRank. diff --git a/src/content/members/aviral-shrivastava.md b/src/content/members/aviral-shrivastava.md new file mode 100644 index 0000000..83d4175 --- /dev/null +++ b/src/content/members/aviral-shrivastava.md @@ -0,0 +1,22 @@ +--- +name: "Aviral Shrivastava" +role: "Principle Investigator" +joinDate: "2006" +email: "aviral.shrivastava@asu.edu" +resume: "/docs/resumes/aviral-shrivastava.pdf" +researchInterests: ["Machine Learning Acceleration", "AI-driven Multi-Level Compilers", "Intelligent Transportation Systems", "Quantum Machine Learning"] +order: 1 +image: "/images/members/aviral-shrivastava.jpg" +--- + +# Biography + +Dr. Aviral Shrivastava is a full Professor in the School of Computing and Augmented Intelligence (SCAI) at the Arizona State University, where he established and heads the Make Programming Simple Lab. He completed his Ph.D. in Information and Computer Science and from the University of California, Irvine, and bachelor’s in Computer Science and Engineering from IIT Delhi. + +**Research:** Dr. Aviral Shrivastava’s main theme of research in on Making Programming Simple for embedded, accelerated computing, cyber-physical, and quantum computing systems. Dr. Aviral Shrivastava and his students work on topics in computer architecture, compilers, machine learning acceleration, quantum computing systems, cyber-physical systems, intelligent transportation, autonomous vehicles. + +**Publications and Awards:** Dr. Aviral Shrivastava has co-authored 1 book and has contributed chapters in 4 books. He has more than 200 articles and conference papers in top embedded system journals and conferences, like DAC, ESWEEK, ACM TECS, and ACM TCPS. His papers have received several awards, including a best paper award at VLSI Design conference 2025, nomination for best paper award at DAC 2017, best student paper award at VLSI 2016, second highest ranked paper at LCTES 2010, and best paper candidate ASPDAC 2008. He has published more than a dozen papers in DAC (top conference in the field). Overall, his works have received more than 4200 citations, growing at the rate of over 350 citations every year. More than 6 of his papers have been cited more than 100 times. Overall, his h-index[1] is 36 (reference Google Scholar). His inventions have been granted 7 patents, and 4 more applications are pending. Dr. Aviral Shrivastava is the recipient of the prestigious 2010 NSF CAREER award. His student’s theses were awarded CIDSE outstanding Ph.D. thesis award in 2021 and 2017, and outstanding master’s thesis awards in 2010, 2017, and 2022. Dr. Aviral Shrivastava’s research efforts have been supported by federal agencies (NSF, DOE, NIST), state agencies (SFAZ), and industry. + +**Teaching and Mentoring:** Dr. Aviral Shrivastava has mentored 3 postdocs, 10 Ph.D. students, and over 25 Masters students. His students are well placed, including a full Professor at UNIST, South Korea, Assistant Professor at South Dakota School of Mines, Apple (x3), Qualcomm (x2), Nvidia(x2), AMD, Google, Benz etc. Dr. Aviral Shrivastava is currently supervising 1 postdoc, 4 Ph.D., and 7 Masters students. Dr. Aviral Shrivastava teaches undergraduate and graduate level courses on computer architecture, cyber-physical, and quantum computing systems. He has consistent student evaluations of over 4/5. + +**Service:** Dr. Aviral Shrivastava is currently serving as the Editor-in-Chief of IEEE ESL (Embedded Systems Letters), and in the steering committee of Languages Compilers, Theory and tools for Embedded Systems (LCTES), Embedded Systems Week (ESWEEK), Conference on HW/SW Codesign and System Synthesis (CODES+ISSS). He is serving as the track chair for the Autonomous Systems track at DAC 2025. Previously, he was the General Chair and program chair of (LCTES) 2024 and 2017 respectively. He was the General Chair of Embedded Systems Week (ESWEEK) 2022, which is the top event in the field of Embedded Systems, comprising of 3 conferences, 2 symposia and 7 workshops, 10 education classes, 7 tutorials, special sessions, Ph.D. forum, and student research competitions. His service has been recognized by IEEE through the 2023 IEEE CEDA Outstanding Service Award. He served as program chair of CODES+ISSS 2018, chair of the Design and Applications track of RTSS 2020, and chair of Autonomous Systems track at DAC 2023. He is serving as the associate editor for ACM Transactions of Cyber-Physical Systems (ACM TCPS), ACM Transactions Embedded Computing Systems (ACM TECS). He was associate editor of the IEEE Transactions on Computer Aided Design (IEEE TCAD) 2018-2023. Dr. Aviral Shrivastava also serves as the Graduate Program Chair of CS programs at ASU. diff --git a/src/content/members/ayush-gupta.md b/src/content/members/ayush-gupta.md new file mode 100644 index 0000000..7e02807 --- /dev/null +++ b/src/content/members/ayush-gupta.md @@ -0,0 +1,17 @@ +--- +name: "Ayush Gupta" +role: "Undergraduate" +joinDate: "2024" +github: "https://github.com/papapizzeria0608" +linkedin: "https://www.linkedin.com/in/ayush-gupta-90237a218/" +resume: "/docs/resumes/ayush-gupta.pdf" +order: 4 +image: "/images/members/ayush-gupta.jpg" +researchInterests: ["AI-driven Multi-Level Compilers"] +--- + +I am an undergraduate student in Computer Science with a minor inBusiness, where I have developed a strong foundation in machinelearning, computer vision, and their applications to real-worldproblems. My early research explored applying ML techniques tohealthcare, including EMG-based gesture recognition and signalclassification. + +I am currently working at the MPS Lab on optimizing auto tuners forlarge language model inferencing through the MLIR (Multi-LevelIntermediate Representation) framework, focusing on compiler-levelperformance improvements and scalable system design. + +I aim to pursue research at the intersection of efficient deeplearning systems and applied AI, contributing to advancements in modeloptimization and deployment for large-scale intelligent systems. diff --git a/src/content/members/bryce-holton.md b/src/content/members/bryce-holton.md new file mode 100644 index 0000000..4083f03 --- /dev/null +++ b/src/content/members/bryce-holton.md @@ -0,0 +1,14 @@ +--- +name: "Bryce Holton" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/bryce-holton-a7850691" +order: 5 +image: "/images/members/bryce-holton.jpg" +isAlumni: true +currentPosition: "CTO at Alaris, Scottsdale, Arizona" +graduated: "Spring 2014" +alumniType: "Master’s Graduate" +--- + +Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM) diff --git a/src/content/members/christian-cunningham.md b/src/content/members/christian-cunningham.md new file mode 100644 index 0000000..1a4163a --- /dev/null +++ b/src/content/members/christian-cunningham.md @@ -0,0 +1,13 @@ +--- +name: "Christian Cunningham" +role: "Alumni" +joinDate: "2024" +website: "https://christiancunningham.xyz/" +order: 5 +image: "/images/members/christian-cunningham.jpg" +isAlumni: true +graduated: "Spring 2022" +alumniType: "Undergraduate Researcher" +--- + +Making a Real-Time Operating System for the Raspberry Pi 2B diff --git a/src/content/members/curt-john-bansil.md b/src/content/members/curt-john-bansil.md new file mode 100644 index 0000000..514b455 --- /dev/null +++ b/src/content/members/curt-john-bansil.md @@ -0,0 +1,13 @@ +--- +name: "Curt John Bansil" +role: "Masters" +joinDate: "2024" +github: "https://github.com/kurtis-b" +linkedin: "https://www.linkedin.com/in/curtbansil/" +resume: "/docs/resumes/curt-john-bansil.pdf" +order: 3 +image: "/images/members/curt-john-bansil.jpg" +researchInterests: ["Machine Learning Acceleration"] +--- + +Currently, I am focusing on machine learning acceleration using FPGAs–specifically with the Versal and Ryzen devices. I’m working towards attaining an understanding of how machine learning accelerators can be constructed to more efficiently run inference on edge devices. diff --git a/src/content/members/dheeraj-lokam.md b/src/content/members/dheeraj-lokam.md new file mode 100644 index 0000000..b9c36af --- /dev/null +++ b/src/content/members/dheeraj-lokam.md @@ -0,0 +1,12 @@ +--- +name: "Dheeraj Lokam" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/dheerajlokam" +order: 5 +image: "/images/members/dheeraj-lokam.jpg" +isAlumni: true +currentPosition: "‎Senior Hardware Safety Engineer at NVIDIA, Santa Clara, California" +graduated: "Fall 2016" +alumniType: "Master’s Graduate" +--- diff --git a/src/content/members/di-lu.md b/src/content/members/di-lu.md new file mode 100644 index 0000000..7515129 --- /dev/null +++ b/src/content/members/di-lu.md @@ -0,0 +1,14 @@ +--- +name: "Di Lu" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/di-lu-6ab79a24" +order: 5 +image: "/images/members/di-lu.jpg" +isAlumni: true +currentPosition: "Software Engineer at Google, California" +graduated: "Spring 2012" +alumniType: "Master’s Graduate" +--- + +STL on Limited Local Memory (LLM) Multi-core Processors diff --git a/src/content/members/dipal-saluja.md b/src/content/members/dipal-saluja.md new file mode 100644 index 0000000..efdae5c --- /dev/null +++ b/src/content/members/dipal-saluja.md @@ -0,0 +1,14 @@ +--- +name: "Dipal Saluja" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/dipal-saluja-19936227" +order: 5 +image: "/images/members/dipal-saluja.jpg" +isAlumni: true +currentPosition: "Senior Software Engineer at Cruise, Nattick, Massachusetts" +graduated: "Summer 2014" +alumniType: "Master’s Graduate" +--- + +Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective diff --git a/src/content/members/edward-andert.md b/src/content/members/edward-andert.md new file mode 100644 index 0000000..8472903 --- /dev/null +++ b/src/content/members/edward-andert.md @@ -0,0 +1,12 @@ +--- +name: "Edward Andert" +role: "Ph.D." +joinDate: "2024" +github: "https://github.com/eandert" +linkedin: "https://www.linkedin.com/in/eddie-andert-00428056/" +order: 2 +image: "/images/members/edward-andert.jpg" +researchInterests: ["Intelligent Transportation Systems"] +--- + +Edward Andert is a Ph.D. student in Computer Engineering at Arizona State University. His research focuses on using cooperative sensor fusion of data from autonomous vehicles to detect and prevent errors from turning into crashes on the road. Edward is currently working on end-to-end trust scoring of autonomous vehicles using cooperative data. Prior to starting the Ph.D., Edward had a Master’s degree in Computer Engineering from ASU. Edward previously worked for Intel and Mobileye as an autonomous vehicle software engineer. diff --git a/src/content/members/fei-hong.md b/src/content/members/fei-hong.md new file mode 100644 index 0000000..33b01a1 --- /dev/null +++ b/src/content/members/fei-hong.md @@ -0,0 +1,14 @@ +--- +name: "Fei Hong" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/feihong" +order: 5 +image: "/images/members/fei-hong.jpg" +isAlumni: true +currentPosition: "Staff II Software Engineer at Broadcom, Santa Clara, California" +graduated: "Spring 2011" +alumniType: "Master’s Graduate" +--- + +UnSync: A Soft-Error Resilient Redundant CMP Architecture diff --git a/src/content/members/francis-mendoza.md b/src/content/members/francis-mendoza.md new file mode 100644 index 0000000..296c132 --- /dev/null +++ b/src/content/members/francis-mendoza.md @@ -0,0 +1,13 @@ +--- +name: "Francis Mendoza" +role: "Alumni" +joinDate: "2024" +website: "https://orcid.org/0009-0005-6936-3285" +order: 5 +image: "/images/members/francis-mendoza.jpg" +isAlumni: true +alumniType: "Master’s Graduate" +graduated: "Fall 2024" +--- + +AEGIS: A Special-Purpose Computer Network For Strategic Cyber Defense diff --git a/src/content/members/guna-lagudu.md b/src/content/members/guna-lagudu.md new file mode 100644 index 0000000..989e472 --- /dev/null +++ b/src/content/members/guna-lagudu.md @@ -0,0 +1,13 @@ +--- +name: "Guna Lagudu" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/guna-sekhar-sai-harsha-lagudu" +order: 5 +image: "/images/members/guna-lagudu.png" +isAlumni: true +alumniType: "Master’s Graduate" +graduated: "Summer 2024" +--- + +LUCI: Multi-Application Orchestration Agent diff --git a/src/content/members/hamed-attariani.md b/src/content/members/hamed-attariani.md new file mode 100644 index 0000000..feca39a --- /dev/null +++ b/src/content/members/hamed-attariani.md @@ -0,0 +1,12 @@ +--- +name: "Hamed Attariani" +role: "Visiting Faculty" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/hamed-attariani/" +order: 7 +image: "/images/members/hamed-attariani.jpg" +currentPosition: "Associate Professor, Wright State University (WSU), Department of Mechanical and Materials Engineering, Dayton, Ohio" +duration: "Summer 2025" +--- + + diff --git a/src/content/members/haotian-wu.md b/src/content/members/haotian-wu.md new file mode 100644 index 0000000..efb840f --- /dev/null +++ b/src/content/members/haotian-wu.md @@ -0,0 +1,9 @@ +--- +name: "Haotian Wu" +role: "Visiting Student" +joinDate: "2024" +order: 6 +image: "/images/members/haotian-wu.jpg" +university: "Chinese Academy of Sciences" +duration: "Fall 2019 — Summer 2020" +--- diff --git a/src/content/members/harrison-lubbers.md b/src/content/members/harrison-lubbers.md new file mode 100644 index 0000000..b220d14 --- /dev/null +++ b/src/content/members/harrison-lubbers.md @@ -0,0 +1,12 @@ +--- +name: "Harrison Lubbers" +role: "Alumni" +joinDate: "2024" +order: 5 +image: "/images/members/mps.jpg" +isAlumni: true +graduated: "Spring 2018" +alumniType: "Undergraduate Researcher" +--- + +Using an Open-Source Solution to Implement a Drone Cyber-Physical System. diff --git a/src/content/members/harshith-allamsetti.md b/src/content/members/harshith-allamsetti.md new file mode 100644 index 0000000..b09993e --- /dev/null +++ b/src/content/members/harshith-allamsetti.md @@ -0,0 +1,14 @@ +--- +name: "Harshith Allamsetti" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/harshithallamsetti" +order: 5 +image: "/images/members/harshith-allamsetti.jpg" +isAlumni: true +currentPosition: "System Design Engineer, Western Digital, Milpitas, California" +graduated: "Summer 2020" +alumniType: "Master’s Graduate" +--- + +Cooperative Driving of Connected Autonomous Vehicles Using Responsibility Sensitive Safety Rules diff --git a/src/content/members/hwisoo-so.md b/src/content/members/hwisoo-so.md new file mode 100644 index 0000000..5d92225 --- /dev/null +++ b/src/content/members/hwisoo-so.md @@ -0,0 +1,14 @@ +--- +name: "Hwisoo So" +role: "Alumni" +joinDate: "2024" +website: "https://scholar.google.com/citations?user=hzKEf24AAAAJ&hl=en" +order: 5 +image: "/images/members/hwisoo-so.jpg" +isAlumni: true +alumniType: "Post-Doctoral Researcher" +currentPosition: "Assistant Professor, Kyungpook National University, Daegu, South Korea" +graduated: "Spring 2019" +--- + + diff --git a/src/content/members/hyojun-lee.md b/src/content/members/hyojun-lee.md new file mode 100644 index 0000000..e398ce8 --- /dev/null +++ b/src/content/members/hyojun-lee.md @@ -0,0 +1,12 @@ +--- +name: "HyoJun Lee" +role: "Visiting Student" +joinDate: "2024" +website: "https://sites.google.com/view/yohanko/members/students?authuser=0#h.h1yffnu3lc3n" +order: 6 +image: "/images/members/hyojun-lee.jpg" +university: "Yonsei University, Wonju, Korea" +duration: "Fall 2025" +--- + +Areas of interest: ML Compilers diff --git a/src/content/members/hyunjun-kim.md b/src/content/members/hyunjun-kim.md new file mode 100644 index 0000000..e5df704 --- /dev/null +++ b/src/content/members/hyunjun-kim.md @@ -0,0 +1,12 @@ +--- +name: "Hyunjun Kim" +role: "Visiting Student" +joinDate: "2024" +website: "https://sites.google.com/view/yohanko/members/students?authuser=0#h.sfyo11cg78gi" +order: 6 +image: "/images/members/hyunjun-kim.jpeg" +university: "Yonsei University, Wonju, Korea" +duration: "Spring 2025" +--- + +Areas of interest: Reliable Autonomous Driving diff --git a/src/content/members/hyunok-oh.md b/src/content/members/hyunok-oh.md new file mode 100644 index 0000000..db5a68b --- /dev/null +++ b/src/content/members/hyunok-oh.md @@ -0,0 +1,12 @@ +--- +name: "Hyunok Oh" +role: "Visiting Faculty" +joinDate: "2024" +website: "https://sites.google.com/site/hyunokoh" +order: 7 +image: "/images/members/hyunok-oh.jpg" +currentPosition: "Full Professor, Hanyang University, Seoul, Korea" +duration: "Fall 2014 – Spring 2015" +--- + + diff --git a/src/content/members/jared-pager.md b/src/content/members/jared-pager.md new file mode 100644 index 0000000..b16d875 --- /dev/null +++ b/src/content/members/jared-pager.md @@ -0,0 +1,14 @@ +--- +name: "Jared Pager" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/jaredpager" +order: 5 +image: "/images/members/jared-pager.jpg" +isAlumni: true +currentPosition: "Software Engineer at Intel, Hillsboro, Oregon" +graduated: "Fall 2011" +alumniType: "Master’s Graduate" +--- + +Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems diff --git a/src/content/members/javier-ramirez.md b/src/content/members/javier-ramirez.md new file mode 100644 index 0000000..1853fc0 --- /dev/null +++ b/src/content/members/javier-ramirez.md @@ -0,0 +1,15 @@ +--- +name: "Javier Ramirez" +role: "Undergraduate" +joinDate: "2024" +github: "https://github.com/javier-cramirez" +linkedin: "https://www.linkedin.com/in/javier-c-ramirez/" +resume: "/docs/resumes/javier-ramirez.pdf" +order: 4 +image: "/images/members/javier-ramirez.png" +researchInterests: ["Intelligent Transportation Systems"] +--- + +I am currently a third year undergraduate at SCAI and SoMSS, pursuing a dual degree in Computer Science and Mathematics (Statistics). My work at MPS Lab is focused on intelligent transportation systems (ITS) — specifically, the problem of predicting traffic flow. + +Currently, I am trying to enhance my understanding of graph neural networks. My personal interests lie at the intersection of reinforcement learning and deep learning. diff --git a/src/content/members/jian-cai.md b/src/content/members/jian-cai.md new file mode 100644 index 0000000..fc87264 --- /dev/null +++ b/src/content/members/jian-cai.md @@ -0,0 +1,14 @@ +--- +name: "Jian Cai" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/jian-cai-05721142/" +order: 5 +image: "/images/members/jian-cai.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "Software Engineer at Google, Sunnyvale, California" +graduated: "Fall 2017" +--- + +Scratchpad Management in Software Managed Manycore Architectures diff --git a/src/content/members/jing-lu.md b/src/content/members/jing-lu.md new file mode 100644 index 0000000..b249fb4 --- /dev/null +++ b/src/content/members/jing-lu.md @@ -0,0 +1,14 @@ +--- +name: "Jing Lu" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/jing-lu-06a86021" +order: 5 +image: "/images/members/jing-lu.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "Staff Software Engineer at Apple, Cupertino, California" +graduated: "Spring 2019" +--- + +Application-aware Performance Optimization for Software Managed Manycore Architecture diff --git a/src/content/members/jinn-pean-lin.md b/src/content/members/jinn-pean-lin.md new file mode 100644 index 0000000..23789b7 --- /dev/null +++ b/src/content/members/jinn-pean-lin.md @@ -0,0 +1,14 @@ +--- +name: "Jinn-Pean Lin" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/晉平-林-b2377a104/" +order: 5 +image: "/images/members/jinn-pean-lin.jpg" +isAlumni: true +currentPosition: "Senior Software Engineer at ForcePoint, Campbell, California" +graduated: "Summer 2017" +alumniType: "Master’s Graduate" +--- + +Optimizing Heap Data Management on Software Managed Manycores diff --git a/src/content/members/jongeun-lee.md b/src/content/members/jongeun-lee.md new file mode 100644 index 0000000..6519c82 --- /dev/null +++ b/src/content/members/jongeun-lee.md @@ -0,0 +1,14 @@ +--- +name: "Jongeun Lee" +role: "Alumni" +joinDate: "2024" +website: "https://ecl.unist.ac.kr/~jlee/" +order: 5 +image: "/images/members/jongeun-lee.jpg" +isAlumni: true +alumniType: "Post-Doctoral Researcher" +currentPosition: "Full Professor and Dean of Academic Information Affairs, UNIST, Ulsan, South Korea" +graduated: "Spring 2009" +--- + + diff --git a/src/content/members/karthik-tanikella.md b/src/content/members/karthik-tanikella.md new file mode 100644 index 0000000..9443a5a --- /dev/null +++ b/src/content/members/karthik-tanikella.md @@ -0,0 +1,14 @@ +--- +name: "Karthik Tanikella" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/karthik-tanikella-7893b866" +order: 5 +image: "/images/members/mps.jpg" +isAlumni: true +currentPosition: "Software Engineer at Axsys Automation, Scottsdale, Arizona" +graduated: "Fall 2015" +alumniType: "Master’s Graduate" +--- + +GemV: A Validated Micro-architectural Vulnerability Estimation Tool diff --git a/src/content/members/kaustubh-harapanahalli.md b/src/content/members/kaustubh-harapanahalli.md new file mode 100644 index 0000000..91cb9a7 --- /dev/null +++ b/src/content/members/kaustubh-harapanahalli.md @@ -0,0 +1,22 @@ +--- +name: "Kaustubh Harapanahalli" +role: "Ph.D." +joinDate: "2023" +email: kharapan@asu.edu +github: "https://github.com/kaustubhharapanahalli" +linkedin: "https://www.linkedin.com/in/kmhalli/" +portfolio: "https://kaustubhharapanahalli.me/" +resume: "/docs/resumes/kaustubh-harapanahalli.pdf" +researchInterests: ["Intelligent Transportation Systems"] +order: 2 +image: "/images/members/kaustubh-harapanahalli.jpeg" +isAlumni: true +alumniType: "Master’s Graduate" +graduated: "Masters, Summer 2025" +--- + +I have developed my core foundation in Computer Vision and AI, which presented opportunities for research and solution development in industrial settings, particularly with Siemens. Balancing technical work with a commitment to my education, my path has evolved from organizing and instructing in learning programs to contributing to corporate roles in a research capacity, focusing on practical applications and collaborative growth in Computer Vision and AI. + +I am currently working on building a deeper understanding of Vision Transformers and their applications in Machine Learning Accelerator and Intelligent Traffic management settings. + +I aim to pursue an Applied research role with an aptitude for Full-Stack Deep Learning. diff --git a/src/content/members/ke-bai.md b/src/content/members/ke-bai.md new file mode 100644 index 0000000..0cbf724 --- /dev/null +++ b/src/content/members/ke-bai.md @@ -0,0 +1,14 @@ +--- +name: "Ke Bai" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/ke-bai-0844b820" +order: 5 +image: "/images/members/ke-bai.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "Senior Software Engineer at Google, Mountain View, California" +graduated: "Spring 2014" +--- + +Compiler and Runtime for Memory Management on Software Managed Manycore Processors diff --git a/src/content/members/kyoungwoo-lee.md b/src/content/members/kyoungwoo-lee.md new file mode 100644 index 0000000..60bb1df --- /dev/null +++ b/src/content/members/kyoungwoo-lee.md @@ -0,0 +1,12 @@ +--- +name: "Kyoungwoo Lee" +role: "Visiting Faculty" +joinDate: "2024" +website: "http://dclab.yonsei.ac.kr/kwlee/" +order: 7 +image: "/images/members/kyoungwoo-lee.bmp" +currentPosition: "Professor and Associate Dean of College of Computing, Yonsei University, Seoul, Korea" +duration: "Feb 2026, Feb 2024, Nov 2017, Feb 2016, Spring 2015, and June 2012." +--- + +Visited: Feb 2026, Feb 2024, Nov 2017, Feb 2016, Spring 2015, and June 2012. diff --git a/src/content/members/mahesh-balasubramanian.md b/src/content/members/mahesh-balasubramanian.md new file mode 100644 index 0000000..3139357 --- /dev/null +++ b/src/content/members/mahesh-balasubramanian.md @@ -0,0 +1,14 @@ +--- +name: "Mahesh Balasubramanian" +role: "Alumni" +joinDate: "2024" +website: "https://sites.google.com/asu.edu/maheshbala/" +order: 5 +image: "/images/members/mahesh-balasubramanian.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "Senior Engineer at Qualcomm Corporate R&D, San Diego, California." +graduated: "Fall 2021" +--- + +Compiler Design for Accelerating Applications on Coarse-Grained Reconfigurable Architectures diff --git a/src/content/members/matthew-szeto.md b/src/content/members/matthew-szeto.md new file mode 100644 index 0000000..9ba0229 --- /dev/null +++ b/src/content/members/matthew-szeto.md @@ -0,0 +1,11 @@ +--- +name: "Matthew Szeto" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/mattaszeto" +order: 5 +image: "/images/members/matthew-szeto.webp" +isAlumni: true +alumniType: "Master’s Graduate" +graduated: "Spring 2023" +--- diff --git a/src/content/members/megan-kuo.md b/src/content/members/megan-kuo.md new file mode 100644 index 0000000..3640305 --- /dev/null +++ b/src/content/members/megan-kuo.md @@ -0,0 +1,13 @@ +--- +name: "Megan Kuo" +role: "Masters" +joinDate: "2024" +github: "https://github.com/Megan0704-1" +linkedin: "https://linkedin.com/in/megankuo2001" +resume: "/docs/resumes/megan-kuo.pdf" +order: 3 +image: "/images/members/megan-kuo.jpg" +researchInterests: ["AI-driven Multi-Level Compilers"] +--- + +I am a Master’s student working at the intersection of machine learning, algorithms, Domain-Specific Languages (DSLs), and compilers. I am passionate about advancing the development of the AI stack, including technologies like MoJo, TVM, MLIR, LLVM, AI accelerators, and GPU computing. diff --git a/src/content/members/mohammad-khayatian.md b/src/content/members/mohammad-khayatian.md new file mode 100644 index 0000000..c1b7713 --- /dev/null +++ b/src/content/members/mohammad-khayatian.md @@ -0,0 +1,14 @@ +--- +name: "Mohammad Khayatian" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/mohammad-khayatian-b82347b7" +order: 5 +image: "/images/members/mohammad-khayatian.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "Senior Robotics Software Engineer, Vecna Robotics." +graduated: "Summer 2021" +--- + +Safe and Robust Cooperative Algorithms for Connected Autonomous Vehicles diff --git a/src/content/members/mohammadreza-mehrabian.md b/src/content/members/mohammadreza-mehrabian.md new file mode 100644 index 0000000..8af788f --- /dev/null +++ b/src/content/members/mohammadreza-mehrabian.md @@ -0,0 +1,14 @@ +--- +name: "Mohammadreza Mehrabian" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/mohammadreza-mehrabian" +order: 5 +image: "/images/members/mohammadreza-mehrabian.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "Assistant Professor, School of Engineering and Computer Science, University of the Pacific, Stockton, California." +graduated: "Summer 2021" +--- + +A Methodology and Formalism to Monitor Timing Specifications Of Cyber-Physical Systems diff --git a/src/content/members/moslem-didehban.md b/src/content/members/moslem-didehban.md new file mode 100644 index 0000000..1a50884 --- /dev/null +++ b/src/content/members/moslem-didehban.md @@ -0,0 +1,14 @@ +--- +name: "Moslem Didehban" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/moslem-didehban-49546559" +order: 5 +image: "/images/members/moslem-didehban.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "Senior Architect at NVIDIA, Santa Clara, CA" +graduated: "Fall 2018" +--- + +Software Techniques For Dependable Execution diff --git a/src/content/members/ozcan-ozturk.md b/src/content/members/ozcan-ozturk.md new file mode 100644 index 0000000..65d0ffd --- /dev/null +++ b/src/content/members/ozcan-ozturk.md @@ -0,0 +1,12 @@ +--- +name: "Ozcan Ozturk" +role: "Visiting Faculty" +joinDate: "2024" +website: "http://www.cs.bilkent.edu.tr/~ozturk/index.html" +order: 7 +image: "/images/members/ozcan-ozturk.jpg" +currentPosition: "Professor, Bilkent University, Ankara, Turkey" +duration: "Fall 2014" +--- + + diff --git a/src/content/members/quoc-long-vinh-ta.md b/src/content/members/quoc-long-vinh-ta.md new file mode 100644 index 0000000..d4c4778 --- /dev/null +++ b/src/content/members/quoc-long-vinh-ta.md @@ -0,0 +1,13 @@ +--- +name: "Quoc Long Vinh Ta" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/quoc-long-vinh-ta-b098a71ba" +order: 5 +image: "/images/members/quoc-long-vinh-ta.jpg" +isAlumni: true +graduated: "Fall 2022" +alumniType: "Master’s Graduate" +--- + +COMSAT: Modified Modulo Scheduling Techniques for Acceleration on Unknown Trip Count and Early Exit Loops diff --git a/src/content/members/rachel-dedinsky.md b/src/content/members/rachel-dedinsky.md new file mode 100644 index 0000000..a9adcfa --- /dev/null +++ b/src/content/members/rachel-dedinsky.md @@ -0,0 +1,16 @@ +--- +name: "Rachel Dedinsky" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/rachel-dedinsky" +order: 5 +image: "/images/members/rachel-dedinsky.jpg" +isAlumni: true +currentPosition: "Software Engineer, Microsoft, Redmond, Washington" +graduated: "Spring 2019" +alumniType: + - "Master’s Graduate" + - "Undergraduate Researcher" +--- + +R2IM – Reliable and Robust Intersection Manager Robust to Rogue Vehicles diff --git a/src/content/members/reiley-jeyapaul.md b/src/content/members/reiley-jeyapaul.md new file mode 100644 index 0000000..7274c4e --- /dev/null +++ b/src/content/members/reiley-jeyapaul.md @@ -0,0 +1,17 @@ +--- +name: "Reiley Jeyapaul" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/reileyjeyapaul" +order: 5 +image: "/images/members/reiley-jeyapaul.jpg" +isAlumni: true +alumniType: + - "Ph.D. Graduate" + - "Post-Doctoral Researcher" +currentPosition: "Senior Research Engineer at ARM Research, Austin, Texas" +graduated: + - "Spring 2012" +--- + +Smart Compilers for Reliable and Power-efficient Embedded Computing diff --git a/src/content/members/rishab-kashyap.md b/src/content/members/rishab-kashyap.md new file mode 100644 index 0000000..5964d01 --- /dev/null +++ b/src/content/members/rishab-kashyap.md @@ -0,0 +1,11 @@ +--- +name: "Rishab Kashyap" +role: "Masters" +joinDate: "2024" +github: "https://github.com/Rishabkashyap14" +linkedin: "https://www.linkedin.com/in/rishab-kashyap-4bb577195/" +resume: "https://drive.google.com/file/d/1FJbfZkICsTnf6TUfRx7OBgNOaoJw0XHs/view?usp=sharing" +order: 3 +image: "/images/members/rishab-kashyap.jpeg" +researchInterests: ["Machine Learning Acceleration"] +--- diff --git a/src/content/members/rooju-chokshi.md b/src/content/members/rooju-chokshi.md new file mode 100644 index 0000000..f8ac397 --- /dev/null +++ b/src/content/members/rooju-chokshi.md @@ -0,0 +1,12 @@ +--- +name: "Rooju Chokshi" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/rooju-chokshi-1328375" +order: 5 +image: "/images/members/rooju-chokshi.jpg" +isAlumni: true +currentPosition: "Principal Software Engineer at Microsoft, Redmond, Washington" +graduated: "Fall 2009" +alumniType: "Master’s Graduate" +--- diff --git a/src/content/members/russell-dill.md b/src/content/members/russell-dill.md new file mode 100644 index 0000000..9ac3673 --- /dev/null +++ b/src/content/members/russell-dill.md @@ -0,0 +1,14 @@ +--- +name: "Russell Dill" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/russdill" +order: 5 +image: "/images/members/russell-dill.jpg" +isAlumni: true +currentPosition: "Lead Operating Systems Engineer at Nikola Motor Company, Phoenix, Arizona" +graduated: "Spring 2015" +alumniType: "Master’s Graduate" +--- + +Optimization of Multi-Channel BCH Error Decoding for Common Cases diff --git a/src/content/members/rylen-sabhlok.md b/src/content/members/rylen-sabhlok.md new file mode 100644 index 0000000..fcaa41b --- /dev/null +++ b/src/content/members/rylen-sabhlok.md @@ -0,0 +1,13 @@ +--- +name: "Rylen Sabhlok" +role: "Undergraduate" +joinDate: "2024" +github: "https://github.com/Rylen-s" +linkedin: "https://www.linkedin.com/in/rylen-sabhlok" +resume: "/docs/resumes/rylen-sabhlok.pdf" +order: 4 +image: "/images/members/rylen-sabhlok.jpeg" +researchInterests: ["Intelligent Transportation Systems"] +--- + +I am currently studying the edge cases of Intelligent Transportation for my FURI Grant this fall. I am studying at ASU with a double major in Computer Science and Electrical Engineering, and I hope to pursue research in an intersecting field, such as Intelligent Robotics or Edge Computing. My passion has always lied in building and questioning, and as such I can’t wait to pursue further research, especially in the Deep Learning field. diff --git a/src/content/members/sai-mylavarapu.md b/src/content/members/sai-mylavarapu.md new file mode 100644 index 0000000..f335ce5 --- /dev/null +++ b/src/content/members/sai-mylavarapu.md @@ -0,0 +1,14 @@ +--- +name: "Sai Mylavarapu" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/saikrishnamylavarapu" +order: 5 +image: "/images/members/sai-mylavarapu.jpg" +isAlumni: true +currentPosition: "Senior Member of Technical Staff at Micron, Milpitas, California" +graduated: "Fall 2008" +alumniType: "Master’s Graduate" +--- + +Improving Application Response Times of Nand Flash based Systems diff --git a/src/content/members/sai-shashank-peddiraju.md b/src/content/members/sai-shashank-peddiraju.md new file mode 100644 index 0000000..cc6d13d --- /dev/null +++ b/src/content/members/sai-shashank-peddiraju.md @@ -0,0 +1,13 @@ +--- +name: "Sai Shashank Peddiraju" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/sai-shashank-peddiraju" +order: 5 +image: "/images/members/sai-shashank-peddiraju.jpg" +isAlumni: true +alumniType: "Master’s Graduate" +graduated: "Summer 2024" +--- + +IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing diff --git a/src/content/members/saleel-kudchadker.md b/src/content/members/saleel-kudchadker.md new file mode 100644 index 0000000..d19d128 --- /dev/null +++ b/src/content/members/saleel-kudchadker.md @@ -0,0 +1,14 @@ +--- +name: "Saleel Kudchadker" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/saleel-kudchadker-8b800a7" +order: 5 +image: "/images/members/saleel-kudchadker.jpg" +isAlumni: true +currentPosition: "Principal Member of Technical Staff at AMD, Santa Clara, California" +graduated: "Spring 2010" +alumniType: "Master’s Graduate" +--- + +Managing Stack Data on Limited Local Memory Multi-core Architectures diff --git a/src/content/members/sanggu-park.md b/src/content/members/sanggu-park.md new file mode 100644 index 0000000..41794a3 --- /dev/null +++ b/src/content/members/sanggu-park.md @@ -0,0 +1,14 @@ +--- +name: "Sanggu Park" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/sanggu-park-ba501a203" +order: 5 +image: "/images/members/sanggu-park.jpg" +isAlumni: true +currentPosition: "Military Officer, Republic of Korea" +graduated: "Summer 2022" +alumniType: "Master’s Graduate" +--- + +Blame-Free Motion Planning in Hybrid Traffic diff --git a/src/content/members/seungchul-jung.md b/src/content/members/seungchul-jung.md new file mode 100644 index 0000000..080117c --- /dev/null +++ b/src/content/members/seungchul-jung.md @@ -0,0 +1,14 @@ +--- +name: "SeungChul Jung" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/seungchuljung" +order: 5 +image: "/images/members/seungchul-jung.jpg" +isAlumni: true +currentPosition: "Senior Software Engineer at Emcore Corporation, San Francisco, California" +graduated: "Fall 2010" +alumniType: "Master’s Graduate" +--- + +Dynamic Code Mapping for Limited Local Memory Architectures diff --git a/src/content/members/shail-dave.md b/src/content/members/shail-dave.md new file mode 100644 index 0000000..eb8f4dc --- /dev/null +++ b/src/content/members/shail-dave.md @@ -0,0 +1,14 @@ +--- +name: "Shail Dave" +role: "Alumni" +joinDate: "2024" +website: "https://sites.google.com/view/shail/" +order: 5 +image: "/images/members/shail-dave.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "AR/VR Systems Modeling Engineer at Qualcomm, San Diego, California." +graduated: "Summer 2024" +--- + +An Agile Methodology for Designing Efficient Domain-Specific Architectures diff --git a/src/content/members/shashwat-pandey.md b/src/content/members/shashwat-pandey.md new file mode 100644 index 0000000..3f52887 --- /dev/null +++ b/src/content/members/shashwat-pandey.md @@ -0,0 +1,15 @@ +--- +name: "Shashwat Pandey" +role: "Masters" +joinDate: "2024" +github: "https://github.com/Shashwatpandey4" +linkedin: "https://www.linkedin.com/in/shashwat023/" +resume: "/docs/resumes/shashwat-pandey.pdf" +order: 3 +image: "/images/members/shashwat-pandey.jpg" +researchInterests: ["AI-driven Multi-Level Compilers"] +--- + +I’m an MS Computer Engineering student interested in compilers, large language models (LLMs), and computer vision. + +Previously, I worked at Novo Nordisk and Zocket as a Data Engineer, focusing on building, maintaining, and improving cloud infrastructure and processing data requirements. diff --git a/src/content/members/shreehari-jagadeesha.md b/src/content/members/shreehari-jagadeesha.md new file mode 100644 index 0000000..d0925ab --- /dev/null +++ b/src/content/members/shreehari-jagadeesha.md @@ -0,0 +1,13 @@ +--- +name: "Shreehari Jagadeesha" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/shreehari-j/" +order: 5 +image: "/images/members/shreehari-jagadeesha.jpg" +isAlumni: true +alumniType: "Master’s Graduate" +graduated: "Fall 2023" +--- + +TIPANGLE: A Machine Learning Approach for Accurate Spatial Pan and Tilt Angle Determination of Pan Tilt Traffic Cameras diff --git a/src/content/members/shri-rajendran-radhika.md b/src/content/members/shri-rajendran-radhika.md new file mode 100644 index 0000000..b9a5ca4 --- /dev/null +++ b/src/content/members/shri-rajendran-radhika.md @@ -0,0 +1,14 @@ +--- +name: "Shri Rajendran Radhika" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/shriharirajendran" +order: 5 +image: "/images/members/shri-rajendran-radhika.jpg" +isAlumni: true +currentPosition: "‎Graphics Hardware Engineer at Intel, Chandler, Arizona" +graduated: "Fall 2014" +alumniType: "Master’s Graduate" +--- + +Path Selection Based Branching for Coarse Grained Reconfigurable Arrays diff --git a/src/content/members/soyeong-park.md b/src/content/members/soyeong-park.md new file mode 100644 index 0000000..fa28b71 --- /dev/null +++ b/src/content/members/soyeong-park.md @@ -0,0 +1,12 @@ +--- +name: "Soyeong Park" +role: "Visiting Student" +joinDate: "2024" +website: "https://sites.google.com/view/yohanko/members/students?authuser=0#h.s5t3rgv4rc91" +order: 6 +image: "/images/members/soyeong-park.jpg" +university: "Yonsei University, Wonju, Korea" +duration: "Fall 2024" +--- + +Areas of interest: Machine Learning Reliability diff --git a/src/content/members/sumedh-joshi.md b/src/content/members/sumedh-joshi.md new file mode 100644 index 0000000..80f877f --- /dev/null +++ b/src/content/members/sumedh-joshi.md @@ -0,0 +1,13 @@ +--- +name: "Sumedh Joshi" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/sumedh14/" +order: 5 +image: "/images/members/sumedh-joshi.jpeg" +isAlumni: true +alumniType: "Master’s Graduate" +graduated: "Fall 2024" +--- + +ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors diff --git a/src/content/members/syna-malhan.md b/src/content/members/syna-malhan.md new file mode 100644 index 0000000..3a051a2 --- /dev/null +++ b/src/content/members/syna-malhan.md @@ -0,0 +1,13 @@ +--- +name: "Syna Malhan" +role: "Undergraduate" +joinDate: "2024" +github: "https://github.com/synamalhan" +linkedin: "https://www.linkedin.com/in/synamalhan/" +resume: "/docs/resumes/syna-malhan.pdf" +order: 4 +image: "/images/members/syna-malhan.jpeg" +researchInterests: ["Intelligent Transportation Systems"] +--- + +I’m a Computer Science undergraduate at ASU with a minor in Data Science. My interests lie in Machine Learning, Computer Vision, and Artificial Intelligence, with a focus on building intelligent systems that address real-world challenges. I’m currently part of the Intelligent Transportation Systems research group, where I aim to apply AI techniques to improve mobility, safety, and decision-making in modern transportation. I’m excited by research opportunities that combine deep technical work with real-world impact, and I hope to contribute to solutions that shape the future of smart, connected systems. diff --git a/src/content/members/tushar-rawat.md b/src/content/members/tushar-rawat.md new file mode 100644 index 0000000..90ca47e --- /dev/null +++ b/src/content/members/tushar-rawat.md @@ -0,0 +1,14 @@ +--- +name: "Tushar Rawat" +role: "Alumni" +joinDate: "2024" +linkedin: "https://www.linkedin.com/in/tsrawat" +order: 5 +image: "/images/members/tushar-rawat.jpg" +isAlumni: true +currentPosition: "Software Engineer at Zoox, Foster City, California" +graduated: "Fall 2014" +alumniType: "Master’s Graduate" +--- + +Enabling Multithreaded Applications on Hybrid Shared Memory Many-core Architectures diff --git a/src/content/members/vinayak-sharma.md b/src/content/members/vinayak-sharma.md new file mode 100644 index 0000000..82c9bd8 --- /dev/null +++ b/src/content/members/vinayak-sharma.md @@ -0,0 +1,24 @@ +--- +name: "Vinayak Sharma" +role: "Ph.D." +joinDate: "2024" +order: 2 +image: "/images/members/vinayak-sharma.jpg" +isAlumni: true +alumniType: "Master’s Graduates" +graduated: "Masters, Spring 2024" +github: "https://github.com/ryo-ma/github-profile-trophy" +linkedin: "https://www.linkedin.com/in/vinayak19th/" +resume: "/docs/resumes/vinayak-sharma.pdf" +researchInterests: ["Quantum Machine Learning"] +--- + +Ph.D. Student working on Machine Learning & Quantum Computing. Currently, I’m working on ML algorithms that can improve the performance and functionality of NISQ Quantum computers at@MPS-Lab. I have full-time experience as a Deep Learning Developer at@Myelin Foundry. + +Where I’m looking to go: My current goal is to pursue a PhD in Quantum Machine Learning and contribute to the development of this emerging and interdisciplinary field. + +🌱 I’m currently learning Quantum Computing + +👨💻 You can check out my profile @vinayak19th.github.io + +💬 Ask me about Tensorflow or any ML/DL work diff --git a/src/content/members/whoi-ree-ha.md b/src/content/members/whoi-ree-ha.md new file mode 100644 index 0000000..b18c015 --- /dev/null +++ b/src/content/members/whoi-ree-ha.md @@ -0,0 +1,12 @@ +--- +name: "Whoi Ree Ha" +role: "Visiting Student" +joinDate: "2024" +website: "http://sor.snu.ac.kr/post/445" +order: 6 +image: "/images/members/whoi-ree-ha.jpg" +university: "Seoul National University, Seoul, Korea" +duration: "Summer 2022" +--- + +Areas of interest: Machine Learning Accelerators diff --git a/src/content/members/yohan-ko.md b/src/content/members/yohan-ko.md new file mode 100644 index 0000000..90bc9d3 --- /dev/null +++ b/src/content/members/yohan-ko.md @@ -0,0 +1,13 @@ +--- +name: "Yohan Ko" +role: "Visiting Faculty" +joinDate: "2024" +website: "https://sites.google.com/view/yohanko/members/professor" +order: 7 +image: "/images/members/yohan-ko.jpg" +currentPosition: "Associate Professor, Yonsei University, Seoul, Korea" +university: "Yonsei University, Seoul, Korea" +duration: "Jan 2026, and Feb 2025" +--- + +Areas of interest: Reliability estimation on cycle-accurate simulators, Robust software for common CPU and specific hardwares such as CGRA and VLIW, Context-awareness based on machine learning techniques diff --git a/src/content/members/yooseong-kim.md b/src/content/members/yooseong-kim.md new file mode 100644 index 0000000..0f60b73 --- /dev/null +++ b/src/content/members/yooseong-kim.md @@ -0,0 +1,14 @@ +--- +name: "Yooseong Kim" +role: "Alumni" +joinDate: "2024" +website: "http://www.linkedin.com/in/ykim122" +order: 5 +image: "/images/members/yooseong-kim.jpg" +isAlumni: true +alumniType: "Ph.D. Graduate" +currentPosition: "Software Engineer at Mercedes-Benz Research & Development North America, Sunnyvale, California" +graduated: "Spring 2017" +--- + +WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems diff --git a/src/content/members/youngbin-kim.md b/src/content/members/youngbin-kim.md new file mode 100644 index 0000000..e71c1df --- /dev/null +++ b/src/content/members/youngbin-kim.md @@ -0,0 +1,12 @@ +--- +name: "Youngbin Kim" +role: "Visiting Student" +joinDate: "2024" +website: "http://dclab.yonsei.ac.kr/ybkim/" +order: 6 +image: "/images/members/youngbin-kim.jpg" +university: "Yonsei University, Seoul, Korea" +duration: "Spring 2019, Fall 2015" +--- + +Areas of interest: scratchpad memory management, programmable dataflow accelerators diff --git a/src/content/members/yunheung-paek.md b/src/content/members/yunheung-paek.md new file mode 100644 index 0000000..95afc76 --- /dev/null +++ b/src/content/members/yunheung-paek.md @@ -0,0 +1,12 @@ +--- +name: "Yunheung Paek" +role: "Visiting Faculty" +joinDate: "2024" +website: "https://ee.snu.ac.kr/en/faculty/professor?mode=view&profid=p058" +order: 7 +image: "/images/members/yunheung-paek.jpeg" +currentPosition: "Full Professor, Seoul National University (SNU), Seoul, Korea" +duration: "2010, Summer 2022" +--- + + diff --git a/src/content/news/2011-award-aviral-is-awarded-nsf-career-4.md b/src/content/news/2011-award-aviral-is-awarded-nsf-career-4.md new file mode 100644 index 0000000..c4e4e4e --- /dev/null +++ b/src/content/news/2011-award-aviral-is-awarded-nsf-career-4.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "Award" +description: "Aviral is awarded NSF CAREER award for Compiler Techniques for Power-Efficient Protection Against Soft Errors." +--- + +Aviral is awarded NSF CAREER award for Compiler Techniques for Power-Efficient Protection Against Soft Errors. diff --git a/src/content/news/2011-award-aviral-was-awarded-the-nsf-0.md b/src/content/news/2011-award-aviral-was-awarded-the-nsf-0.md new file mode 100644 index 0000000..ac00adc --- /dev/null +++ b/src/content/news/2011-award-aviral-was-awarded-the-nsf-0.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "Award" +description: "Aviral was awarded the NSF Career Award to support his research on the reliable computing" +--- + +Aviral was awarded the NSF Career Award to support his research on the reliable computing diff --git a/src/content/news/2011-lab-update-advances-in-reliable-computing-draw-0.md b/src/content/news/2011-lab-update-advances-in-reliable-computing-draw-0.md new file mode 100644 index 0000000..c698a8f --- /dev/null +++ b/src/content/news/2011-lab-update-advances-in-reliable-computing-draw-0.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "General" +description: "Advances in reliable computing draw recognition for doctoral student [ASU Full Circle]" +--- + +Advances in reliable computing draw recognition for doctoral student [ASU Full Circle] diff --git a/src/content/news/2011-lab-update-arizona-state-university-intel-5.md b/src/content/news/2011-lab-update-arizona-state-university-intel-5.md new file mode 100644 index 0000000..7ff6067 --- /dev/null +++ b/src/content/news/2011-lab-update-arizona-state-university-intel-5.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "General" +description: "Arizona state university & Intel Corporation collaboration in parallel computing" +--- + +Arizona state university & Intel Corporation collaboration in parallel computing diff --git a/src/content/news/2011-lab-update-aviral-talked-about-compiler-and-1.md b/src/content/news/2011-lab-update-aviral-talked-about-compiler-and-1.md new file mode 100644 index 0000000..309ee60 --- /dev/null +++ b/src/content/news/2011-lab-update-aviral-talked-about-compiler-and-1.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "Event" +description: "Aviral talked about “Compiler and Microarchitectural Techniques for Leakage Power Reduction” at Microsoft Research." +--- + +Aviral talked about “Compiler and Microarchitectural Techniques for Leakage Power Reduction” at Microsoft Research. diff --git a/src/content/news/2011-lab-update-aviral-will-give-a-talk-3.md b/src/content/news/2011-lab-update-aviral-will-give-a-talk-3.md new file mode 100644 index 0000000..c8d9cc4 --- /dev/null +++ b/src/content/news/2011-lab-update-aviral-will-give-a-talk-3.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "Event" +description: "Aviral will give a talk on “Multi-core Challenge: Missing Memory Virtualization” at UT-Austin Computer Architecture Seminar Series." +--- + +Aviral will give a talk on “Multi-core Challenge: Missing Memory Virtualization” at UT-Austin Computer Architecture Seminar Series. diff --git a/src/content/news/2011-lab-update-aviral-will-present-on-multicore-2.md b/src/content/news/2011-lab-update-aviral-will-present-on-multicore-2.md new file mode 100644 index 0000000..4db2494 --- /dev/null +++ b/src/content/news/2011-lab-update-aviral-will-present-on-multicore-2.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "General" +description: "Aviral will present on “Multi-core Challenge: Missing Memory Virtualization” at Purdue University." +--- + +Aviral will present on “Multi-core Challenge: Missing Memory Virtualization” at Purdue University. diff --git a/src/content/news/2011-lab-update-consortium-for-embedded-systems-laying-4.md b/src/content/news/2011-lab-update-consortium-for-embedded-systems-laying-4.md new file mode 100644 index 0000000..fe6e20b --- /dev/null +++ b/src/content/news/2011-lab-update-consortium-for-embedded-systems-laying-4.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "General" +description: "Consortium for embedded systems laying groundwork for global impact [ASU Full Circle]" +--- + +Consortium for embedded systems laying groundwork for global impact [ASU Full Circle] diff --git a/src/content/news/2011-lab-update-intel-corp-1.md b/src/content/news/2011-lab-update-intel-corp-1.md new file mode 100644 index 0000000..ebe3363 --- /dev/null +++ b/src/content/news/2011-lab-update-intel-corp-1.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "General" +description: "Intel Corp. facility opens opportunity for students [The State Press]" +--- + +Intel Corp. facility opens opportunity for students [The State Press] diff --git a/src/content/news/2011-lab-update-jonghee-yoons-paper-spkm-a-3.md b/src/content/news/2011-lab-update-jonghee-yoons-paper-spkm-a-3.md new file mode 100644 index 0000000..c89abb4 --- /dev/null +++ b/src/content/news/2011-lab-update-jonghee-yoons-paper-spkm-a-3.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "Publication" +description: "Jonghee Yoon’s paper, SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures” was the best paper award candidate in ASP-DAC 2008." +--- + +Jonghee Yoon’s paper, SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures” was the best paper award candidate in ASP-DAC 2008. diff --git a/src/content/news/2011-lab-update-reileys-paper-cache-vulnerability-equations-2.md b/src/content/news/2011-lab-update-reileys-paper-cache-vulnerability-equations-2.md new file mode 100644 index 0000000..8e270b5 --- /dev/null +++ b/src/content/news/2011-lab-update-reileys-paper-cache-vulnerability-equations-2.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "Publication" +description: "Reiley’s paper, “Cache Vulnerability Equations for protecting data in embedded processor caches from soft errors”, was the second-highest ranked paper at LCTES 2010." +--- + +Reiley’s paper, “Cache Vulnerability Equations for protecting data in embedded processor caches from soft errors”, was the second-highest ranked paper at LCTES 2010. diff --git a/src/content/news/2011-lab-update-science-foundation-arizona-grant-to-0.md b/src/content/news/2011-lab-update-science-foundation-arizona-grant-to-0.md new file mode 100644 index 0000000..f0c074b --- /dev/null +++ b/src/content/news/2011-lab-update-science-foundation-arizona-grant-to-0.md @@ -0,0 +1,7 @@ +--- +date: "2011" +type: "General" +description: "Science Foundation Arizona grant to ASU/Raytheon research group will fund effort to expand computer capabilities. [ASU Full Circle]" +--- + +Science Foundation Arizona grant to ASU/Raytheon research group will fund effort to expand computer capabilities. [ASU Full Circle] diff --git a/src/content/news/2012-award-aviral-is-awarded-nsf-career-1.md b/src/content/news/2012-award-aviral-is-awarded-nsf-career-1.md new file mode 100644 index 0000000..52ac33c --- /dev/null +++ b/src/content/news/2012-award-aviral-is-awarded-nsf-career-1.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "Award" +description: "Aviral is awarded NSF CAREER award for Compiler Techniques for Power-Efficient Protection Against Soft Errors." +--- + +Aviral is awarded NSF CAREER award for Compiler Techniques for Power-Efficient Protection Against Soft Errors. diff --git a/src/content/news/2012-award-aviral-was-awarded-the-nsf-6.md b/src/content/news/2012-award-aviral-was-awarded-the-nsf-6.md new file mode 100644 index 0000000..142fcaa --- /dev/null +++ b/src/content/news/2012-award-aviral-was-awarded-the-nsf-6.md @@ -0,0 +1,7 @@ +--- +date: "2012" +type: "Award" +description: "Aviral was awarded the NSF Career Award to support his research on the reliable computing" +--- + +Aviral was awarded the NSF Career Award to support his research on the reliable computing diff --git a/src/content/news/2012-lab-update-asu-technology-team-prepares-for-5.md b/src/content/news/2012-lab-update-asu-technology-team-prepares-for-5.md new file mode 100644 index 0000000..3d3c312 --- /dev/null +++ b/src/content/news/2012-lab-update-asu-technology-team-prepares-for-5.md @@ -0,0 +1,7 @@ +--- +date: "2012" +type: "General" +description: "ASU Technology Team Prepares for Shanghai [The State Press]" +--- + +ASU Technology Team Prepares for Shanghai [The State Press] diff --git a/src/content/news/2012-lab-update-aviral-is-selected-for-participation-3.md b/src/content/news/2012-lab-update-aviral-is-selected-for-participation-3.md new file mode 100644 index 0000000..e207fbb --- /dev/null +++ b/src/content/news/2012-lab-update-aviral-is-selected-for-participation-3.md @@ -0,0 +1,7 @@ +--- +date: "2012" +type: "General" +description: "Aviral is selected for participation in 2012 Frontiers of Engineering Education Symposium." +--- + +Aviral is selected for participation in 2012 Frontiers of Engineering Education Symposium. diff --git a/src/content/news/2012-lab-update-aviral-will-give-a-talk-2.md b/src/content/news/2012-lab-update-aviral-will-give-a-talk-2.md new file mode 100644 index 0000000..c8a432d --- /dev/null +++ b/src/content/news/2012-lab-update-aviral-will-give-a-talk-2.md @@ -0,0 +1,7 @@ +--- +date: "2012" +type: "Event" +description: "Aviral will give a talk on “Beyond the Hill of Multicores lies the Valley of Accelerators” at UNIST, Republic of Korea." +--- + +Aviral will give a talk on “Beyond the Hill of Multicores lies the Valley of Accelerators” at UNIST, Republic of Korea. diff --git a/src/content/news/2012-lab-update-aviral-will-present-on-1.md b/src/content/news/2012-lab-update-aviral-will-present-on-1.md new file mode 100644 index 0000000..b0aec84 --- /dev/null +++ b/src/content/news/2012-lab-update-aviral-will-present-on-1.md @@ -0,0 +1,7 @@ +--- +date: "2012" +type: "General" +description: "Aviral will present on “Beyond the Hill of Multi-cores lies the Valley of Accelerators” at IBM Research." +--- + +Aviral will present on “Beyond the Hill of Multi-cores lies the Valley of Accelerators” at IBM Research. diff --git a/src/content/news/2012-lab-update-creative-teaching-approaches-put-spotlight-0.md b/src/content/news/2012-lab-update-creative-teaching-approaches-put-spotlight-0.md new file mode 100644 index 0000000..dafd317 --- /dev/null +++ b/src/content/news/2012-lab-update-creative-teaching-approaches-put-spotlight-0.md @@ -0,0 +1,7 @@ +--- +date: "2012" +type: "General" +description: "Creative teaching approaches put spotlight on ASU engineers [ASU Inner Circle]" +--- + +Creative teaching approaches put spotlight on ASU engineers [ASU Inner Circle] diff --git a/src/content/news/2012-lab-update-our-research-on-reliability-got-4.md b/src/content/news/2012-lab-update-our-research-on-reliability-got-4.md new file mode 100644 index 0000000..574a3dc --- /dev/null +++ b/src/content/news/2012-lab-update-our-research-on-reliability-got-4.md @@ -0,0 +1,7 @@ +--- +date: "2012" +type: "General" +description: "Our research on reliability got featured in ASU Full Circle." +--- + +Our research on reliability got featured in ASU Full Circle. diff --git a/src/content/news/2013-lab-update-aviral-will-present-on-compilermicroarchitecture-1.md b/src/content/news/2013-lab-update-aviral-will-present-on-compilermicroarchitecture-1.md new file mode 100644 index 0000000..401677f --- /dev/null +++ b/src/content/news/2013-lab-update-aviral-will-present-on-compilermicroarchitecture-1.md @@ -0,0 +1,7 @@ +--- +date: "2013" +type: "General" +description: "Aviral will present on “Compiler-Microarchitecture Cooperation for Resilience Against Soft Errors” at Workshop on Compiler Assisted SoC Assembly (CASA 2013)." +--- + +Aviral will present on “Compiler-Microarchitecture Cooperation for Resilience Against Soft Errors” at Workshop on Compiler Assisted SoC Assembly (CASA 2013). diff --git a/src/content/news/2013-lab-update-aviral-will-present-on-the-0.md b/src/content/news/2013-lab-update-aviral-will-present-on-the-0.md new file mode 100644 index 0000000..8c4aba2 --- /dev/null +++ b/src/content/news/2013-lab-update-aviral-will-present-on-the-0.md @@ -0,0 +1,7 @@ +--- +date: "2013" +type: "General" +description: "Aviral will present on “The Rise and Rise of Scratchpad Memories” at Memory Architecture and Organization Workshop 2013." +--- + +Aviral will present on “The Rise and Rise of Scratchpad Memories” at Memory Architecture and Organization Workshop 2013. diff --git a/src/content/news/2013-lab-update-aviral-will-talk-about-compilation-2.md b/src/content/news/2013-lab-update-aviral-will-talk-about-compilation-2.md new file mode 100644 index 0000000..a677985 --- /dev/null +++ b/src/content/news/2013-lab-update-aviral-will-talk-about-compilation-2.md @@ -0,0 +1,7 @@ +--- +date: "2013" +type: "Event" +description: "Aviral will talk about Compilation for SPM-based Manycore Architectures at University of Michigan." +--- + +Aviral will talk about Compilation for SPM-based Manycore Architectures at University of Michigan. diff --git a/src/content/news/2013-lab-update-infinibotics-cosmo-robotic-toy-car-5.md b/src/content/news/2013-lab-update-infinibotics-cosmo-robotic-toy-car-5.md new file mode 100644 index 0000000..eca168f --- /dev/null +++ b/src/content/news/2013-lab-update-infinibotics-cosmo-robotic-toy-car-5.md @@ -0,0 +1,7 @@ +--- +date: "2013" +type: "General" +description: "Infinibotics Cosmo: Robotic toy car meant for edutainment [RobAid]" +--- + +Infinibotics Cosmo: Robotic toy car meant for edutainment [RobAid] diff --git a/src/content/news/2013-lab-update-robot-car-steers-engineering-students-3.md b/src/content/news/2013-lab-update-robot-car-steers-engineering-students-3.md new file mode 100644 index 0000000..be74bc0 --- /dev/null +++ b/src/content/news/2013-lab-update-robot-car-steers-engineering-students-3.md @@ -0,0 +1,7 @@ +--- +date: "2013" +type: "General" +description: "Robot car steers engineering students’ future [The State Press]" +--- + +Robot car steers engineering students’ future [The State Press] diff --git a/src/content/news/2013-lab-update-robotic-car-can-teach-kids-4.md b/src/content/news/2013-lab-update-robotic-car-can-teach-kids-4.md new file mode 100644 index 0000000..ad59b0e --- /dev/null +++ b/src/content/news/2013-lab-update-robotic-car-can-teach-kids-4.md @@ -0,0 +1,7 @@ +--- +date: "2013" +type: "General" +description: "Robotic Car Can Teach Kids Spelling and Math [Robotics Business Review]" +--- + +Robotic Car Can Teach Kids Spelling and Math [Robotics Business Review] diff --git a/src/content/news/2013-lab-update-robotic-toy-car-drives-engineering-6.md b/src/content/news/2013-lab-update-robotic-toy-car-drives-engineering-6.md new file mode 100644 index 0000000..7d198bc --- /dev/null +++ b/src/content/news/2013-lab-update-robotic-toy-car-drives-engineering-6.md @@ -0,0 +1,7 @@ +--- +date: "2013" +type: "General" +description: "Robotic toy car drives engineering students business venture [ASU Now]" +--- + +Robotic toy car drives engineering students business venture [ASU Now] diff --git a/src/content/news/2014-lab-update-aviral-is-coorganizing-workshop-on-2.md b/src/content/news/2014-lab-update-aviral-is-coorganizing-workshop-on-2.md new file mode 100644 index 0000000..2c2c7e9 --- /dev/null +++ b/src/content/news/2014-lab-update-aviral-is-coorganizing-workshop-on-2.md @@ -0,0 +1,7 @@ +--- +date: "2014" +type: "General" +description: "Aviral is co-organizing Workshop on Compiler Assisted SoC Assembly (CASA 2014) at Embedded Systems Week." +--- + +Aviral is co-organizing Workshop on Compiler Assisted SoC Assembly (CASA 2014) at Embedded Systems Week. diff --git a/src/content/news/2014-lab-update-aviral-is-featured-in-an-1.md b/src/content/news/2014-lab-update-aviral-is-featured-in-an-1.md new file mode 100644 index 0000000..251e39b --- /dev/null +++ b/src/content/news/2014-lab-update-aviral-is-featured-in-an-1.md @@ -0,0 +1,7 @@ +--- +date: "2014" +type: "General" +description: "Aviral is featured in an Embedded Computing Design article on Accelerating processing with Coarse Grain Reconfigurable Arrays." +--- + +Aviral is featured in an Embedded Computing Design article on Accelerating processing with Coarse Grain Reconfigurable Arrays. diff --git a/src/content/news/2014-lab-update-aviral-will-present-on-quantitative-0.md b/src/content/news/2014-lab-update-aviral-will-present-on-quantitative-0.md new file mode 100644 index 0000000..34792d8 --- /dev/null +++ b/src/content/news/2014-lab-update-aviral-will-present-on-quantitative-0.md @@ -0,0 +1,7 @@ +--- +date: "2014" +type: "Event" +description: "Aviral will present on “Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors” in ICS Seminar at University of Texas, Austin." +--- + +Aviral will present on “Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors” in ICS Seminar at University of Texas, Austin. diff --git a/src/content/news/2014-lab-update-our-research-on-cgra-accelerators-3.md b/src/content/news/2014-lab-update-our-research-on-cgra-accelerators-3.md new file mode 100644 index 0000000..5075935 --- /dev/null +++ b/src/content/news/2014-lab-update-our-research-on-cgra-accelerators-3.md @@ -0,0 +1,7 @@ +--- +date: "2014" +type: "General" +description: "Our research on CGRA accelerators featured in Embedded Computing Design magazine [e-article] [magazine]." +--- + +Our research on CGRA accelerators featured in Embedded Computing Design magazine [e-article] [magazine]. diff --git a/src/content/news/2015-lab-update-aviral-featured-in-the-video-0.md b/src/content/news/2015-lab-update-aviral-featured-in-the-video-0.md new file mode 100644 index 0000000..142c71c --- /dev/null +++ b/src/content/news/2015-lab-update-aviral-featured-in-the-video-0.md @@ -0,0 +1,7 @@ +--- +date: "2015" +type: "General" +description: "Aviral featured in the video about “An Elevator Pitch: Real People, Real Elevators” by NSF." +--- + +Aviral featured in the video about “An Elevator Pitch: Real People, Real Elevators” by NSF. diff --git a/src/content/news/2015-lab-update-aviral-is-serving-as-a-2.md b/src/content/news/2015-lab-update-aviral-is-serving-as-a-2.md new file mode 100644 index 0000000..7a72062 --- /dev/null +++ b/src/content/news/2015-lab-update-aviral-is-serving-as-a-2.md @@ -0,0 +1,7 @@ +--- +date: "2015" +type: "General" +description: "Aviral is serving as a guest editor of a special issue of ACM Transactions on Embedded Computing Systems (TECS) on Software Controlled Memories." +--- + +Aviral is serving as a guest editor of a special issue of ACM Transactions on Embedded Computing Systems (TECS) on Software Controlled Memories. diff --git a/src/content/news/2015-lab-update-jared-and-reileys-article-on-1.md b/src/content/news/2015-lab-update-jared-and-reileys-article-on-1.md new file mode 100644 index 0000000..a4ab73a --- /dev/null +++ b/src/content/news/2015-lab-update-jared-and-reileys-article-on-1.md @@ -0,0 +1,7 @@ +--- +date: "2015" +type: "Publication" +description: "Jared and Reiley’s article on “A Software Scheme for Multithreading on CGRAs” is accepted to be published in TECS." +--- + +Jared and Reiley’s article on “A Software Scheme for Multithreading on CGRAs” is accepted to be published in TECS. diff --git a/src/content/news/2016-award-jians-paper-on-software-coherence-0.md b/src/content/news/2016-award-jians-paper-on-software-coherence-0.md new file mode 100644 index 0000000..50d7e9d --- /dev/null +++ b/src/content/news/2016-award-jians-paper-on-software-coherence-0.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "Award" +description: "Jian’s paper on “Software Coherence Management on Non-Coherent Cache Multi-cores” received Prof. N. N. Biswas Best Student Paper award at VLSI Design 2016." +--- + +Jian’s paper on “Software Coherence Management on Non-Coherent Cache Multi-cores” received Prof. N. N. Biswas Best Student Paper award at VLSI Design 2016. diff --git a/src/content/news/2016-award-jonghee-yoons-paper-spkm-a-2.md b/src/content/news/2016-award-jonghee-yoons-paper-spkm-a-2.md new file mode 100644 index 0000000..5d13611 --- /dev/null +++ b/src/content/news/2016-award-jonghee-yoons-paper-spkm-a-2.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "Award" +description: "Jonghee Yoon’s paper, SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures” was the best paper award candidate in ASP-DAC 2008." +--- + +Jonghee Yoon’s paper, SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures” was the best paper award candidate in ASP-DAC 2008. diff --git a/src/content/news/2016-lab-update-a-paper-on-languages-must-2.md b/src/content/news/2016-lab-update-a-paper-on-languages-must-2.md new file mode 100644 index 0000000..1354061 --- /dev/null +++ b/src/content/news/2016-lab-update-a-paper-on-languages-must-2.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "Publication" +description: "A paper on “Languages Must Expose Memory Heterogeneity” is accepted to appear at The International Symposium on Memory Systems (MEMSYS 2016)." +--- + +A paper on “Languages Must Expose Memory Heterogeneity” is accepted to appear at The International Symposium on Memory Systems (MEMSYS 2016). diff --git a/src/content/news/2016-lab-update-arizona-universities-drawing-in-technology-3.md b/src/content/news/2016-lab-update-arizona-universities-drawing-in-technology-3.md new file mode 100644 index 0000000..e83a46a --- /dev/null +++ b/src/content/news/2016-lab-update-arizona-universities-drawing-in-technology-3.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "General" +description: "Arizona universities drawing in technology companies [KTAR News]" +--- + +Arizona universities drawing in technology companies [KTAR News] diff --git a/src/content/news/2016-lab-update-aviral-is-serving-as-associate-0.md b/src/content/news/2016-lab-update-aviral-is-serving-as-associate-0.md new file mode 100644 index 0000000..b3a5932 --- /dev/null +++ b/src/content/news/2016-lab-update-aviral-is-serving-as-associate-0.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "General" +description: "Aviral is serving as associate editor of Transactions on Multi Scale Computing Systems (TMSCS)." +--- + +Aviral is serving as associate editor of Transactions on Multi Scale Computing Systems (TMSCS). diff --git a/src/content/news/2016-lab-update-aviral-is-serving-as-associate-10.md b/src/content/news/2016-lab-update-aviral-is-serving-as-associate-10.md new file mode 100644 index 0000000..de560ec --- /dev/null +++ b/src/content/news/2016-lab-update-aviral-is-serving-as-associate-10.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "General" +description: "Aviral is serving as associate editor of Transactions on Embedded Computing Systems (TECS)." +--- + +Aviral is serving as associate editor of Transactions on Embedded Computing Systems (TECS). diff --git a/src/content/news/2016-lab-update-expect-the-unexpected-autonomous-car-4.md b/src/content/news/2016-lab-update-expect-the-unexpected-autonomous-car-4.md new file mode 100644 index 0000000..be49ebb --- /dev/null +++ b/src/content/news/2016-lab-update-expect-the-unexpected-autonomous-car-4.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "General" +description: "Expect the Unexpected: Autonomous car project prepares engineers for industry challenges [ASU Full Circle]" +--- + +Expect the Unexpected: Autonomous car project prepares engineers for industry challenges [ASU Full Circle] diff --git a/src/content/news/2016-lab-update-jians-paper-on-software-coherence-9.md b/src/content/news/2016-lab-update-jians-paper-on-software-coherence-9.md new file mode 100644 index 0000000..88dec81 --- /dev/null +++ b/src/content/news/2016-lab-update-jians-paper-on-software-coherence-9.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "Publication" +description: "Jian’s paper on “Software Coherence Management on Non-Coherent Cache Multi-cores” received Prof. N. N. Biswas Best Student Paper award at VLSI Design 2016." +--- + +Jian’s paper on “Software Coherence Management on Non-Coherent Cache Multi-cores” received Prof. N. N. Biswas Best Student Paper award at VLSI Design 2016. diff --git a/src/content/news/2016-lab-update-moslems-paper-on-zdc-a-8.md b/src/content/news/2016-lab-update-moslems-paper-on-zdc-a-8.md new file mode 100644 index 0000000..8a73d46 --- /dev/null +++ b/src/content/news/2016-lab-update-moslems-paper-on-zdc-a-8.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "Publication" +description: "Moslem’s paper on “ZDC: A Compiler technique for Zero Silent Data Corruption” is accepted for publication at DAC 2016." +--- + +Moslem’s paper on “ZDC: A Compiler technique for Zero Silent Data Corruption” is accepted for publication at DAC 2016. diff --git a/src/content/news/2016-lab-update-reileys-paper-on-systematic-methodology-1.md b/src/content/news/2016-lab-update-reileys-paper-on-systematic-methodology-1.md new file mode 100644 index 0000000..7fe1769 --- /dev/null +++ b/src/content/news/2016-lab-update-reileys-paper-on-systematic-methodology-1.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "Publication" +description: "Reiley’s paper on “Systematic Methodology for the Quantitative Analysis of Pipeline Register Reliability in Embedded Systems” is accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems." +--- + +Reiley’s paper on “Systematic Methodology for the Quantitative Analysis of Pipeline Register Reliability in Embedded Systems” is accepted for publication in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. diff --git a/src/content/news/2016-lab-update-robotic-autonomous-cars-teach-whole-7.md b/src/content/news/2016-lab-update-robotic-autonomous-cars-teach-whole-7.md new file mode 100644 index 0000000..32da9d1 --- /dev/null +++ b/src/content/news/2016-lab-update-robotic-autonomous-cars-teach-whole-7.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "General" +description: "Robotic autonomous cars teach whole system design [ASU Full Circle]  [Fulton Magazine]" +--- + +Robotic autonomous cars teach whole system design [ASU Full Circle]  [Fulton Magazine] diff --git a/src/content/news/2016-lab-update-robotics-from-a-to-z-6.md b/src/content/news/2016-lab-update-robotics-from-a-to-z-6.md new file mode 100644 index 0000000..1ae54ba --- /dev/null +++ b/src/content/news/2016-lab-update-robotics-from-a-to-z-6.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "General" +description: "Robotics from A to Z [The State Press]" +--- + +Robotics from A to Z [The State Press] diff --git a/src/content/news/2016-lab-update-shail-and-mohammadreza-received-a-5.md b/src/content/news/2016-lab-update-shail-and-mohammadreza-received-a-5.md new file mode 100644 index 0000000..27a065d --- /dev/null +++ b/src/content/news/2016-lab-update-shail-and-mohammadreza-received-a-5.md @@ -0,0 +1,7 @@ +--- +date: "2016" +type: "General" +description: "Shail and MohammadReza received A. Richard Newton Young Student Fellowship at 53rd Design Automation Conference (DAC 2016)." +--- + +Shail and MohammadReza received A. Richard Newton Young Student Fellowship at 53rd Design Automation Conference (DAC 2016). diff --git a/src/content/news/2017-award-edward-and-mohammad-s-paper-0.md b/src/content/news/2017-award-edward-and-mohammad-s-paper-0.md new file mode 100644 index 0000000..fcc9312 --- /dev/null +++ b/src/content/news/2017-award-edward-and-mohammad-s-paper-0.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Award" +description: "Edward and Mohammad‘s paper on “Crossroads – Time-Sensitive Autonomous Intersection Management” is the Best paper candidate at Design Automation Conference 2017. Congratulations!" +--- + +Edward and Mohammad‘s paper on “Crossroads – Time-Sensitive Autonomous Intersection Management” is the Best paper candidate at Design Automation Conference 2017. Congratulations! diff --git a/src/content/news/2017-award-moslem-received-the-best-poster-1.md b/src/content/news/2017-award-moslem-received-the-best-poster-1.md new file mode 100644 index 0000000..1bd9b07 --- /dev/null +++ b/src/content/news/2017-award-moslem-received-the-best-poster-1.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Award" +description: "Moslem received the best poster award at the Ph.D. forum, DAC 2017 for his thesis on “Software Schemes to Tolerate Hardware Faults for Safety-Critical Applications”." +--- + +Moslem received the best poster award at the Ph.D. forum, DAC 2017 for his thesis on “Software Schemes to Tolerate Hardware Faults for Safety-Critical Applications”. diff --git a/src/content/news/2017-award-yooseong-received-outstanding-computer-science-2.md b/src/content/news/2017-award-yooseong-received-outstanding-computer-science-2.md new file mode 100644 index 0000000..c1d1520 --- /dev/null +++ b/src/content/news/2017-award-yooseong-received-outstanding-computer-science-2.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Award" +description: "Yooseong received “Outstanding Computer Science Graduating Ph.D. Student of the Year” award for WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems in SCIDSE, ASU in 2017." +--- + +Yooseong received “Outstanding Computer Science Graduating Ph.D. Student of the Year” award for WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems in SCIDSE, ASU in 2017. diff --git a/src/content/news/2017-lab-update-aviral-and-jian-coauthored-a-2.md b/src/content/news/2017-lab-update-aviral-and-jian-coauthored-a-2.md new file mode 100644 index 0000000..4a203da --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-and-jian-coauthored-a-2.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral and Jian co-authored a book chapter on “Hardware-Aware Compilation“. (Book: Handbook of Hardware/Software Codesign, Springer.)" +--- + +Aviral and Jian co-authored a book chapter on “Hardware-Aware Compilation“. (Book: Handbook of Hardware/Software Codesign, Springer.) diff --git a/src/content/news/2017-lab-update-aviral-is-a-panelist-on-6.md b/src/content/news/2017-lab-update-aviral-is-a-panelist-on-6.md new file mode 100644 index 0000000..12f153e --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-is-a-panelist-on-6.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral is a panelist on Autonomous driving series that will explore roadway infrastructure in the age of driverless cars." +--- + +Aviral is a panelist on Autonomous driving series that will explore roadway infrastructure in the age of driverless cars. diff --git a/src/content/news/2017-lab-update-aviral-is-organizing-fifth-international-10.md b/src/content/news/2017-lab-update-aviral-is-organizing-fifth-international-10.md new file mode 100644 index 0000000..2a11914 --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-is-organizing-fifth-international-10.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral is organizing Fifth International Workshop on Cross-layer Resiliency (ICWR) 2017." +--- + +Aviral is organizing Fifth International Workshop on Cross-layer Resiliency (ICWR) 2017. diff --git a/src/content/news/2017-lab-update-aviral-is-organizing-the-acmieee-14.md b/src/content/news/2017-lab-update-aviral-is-organizing-the-acmieee-14.md new file mode 100644 index 0000000..93b7a8f --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-is-organizing-the-acmieee-14.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral is organizing the ACM/IEEE Early Career workshop at DAC 2017." +--- + +Aviral is organizing the ACM/IEEE Early Career workshop at DAC 2017. diff --git a/src/content/news/2017-lab-update-aviral-is-serving-as-a-16.md b/src/content/news/2017-lab-update-aviral-is-serving-as-a-16.md new file mode 100644 index 0000000..f7a2001 --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-is-serving-as-a-16.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral is serving as a guest editor of a special issue of Transactions on Multi Scale Computing Systems (TMSCS) on Accelerated Computing." +--- + +Aviral is serving as a guest editor of a special issue of Transactions on Multi Scale Computing Systems (TMSCS) on Accelerated Computing. diff --git a/src/content/news/2017-lab-update-aviral-is-serving-as-program-20.md b/src/content/news/2017-lab-update-aviral-is-serving-as-program-20.md new file mode 100644 index 0000000..65cd6a0 --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-is-serving-as-program-20.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral is serving as Program Committee chair of CODES+ISSS." +--- + +Aviral is serving as Program Committee chair of CODES+ISSS. diff --git a/src/content/news/2017-lab-update-aviral-is-serving-as-program-4.md b/src/content/news/2017-lab-update-aviral-is-serving-as-program-4.md new file mode 100644 index 0000000..57dde10 --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-is-serving-as-program-4.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral is serving as Program Committee chair of CODES+ISSS 2018." +--- + +Aviral is serving as Program Committee chair of CODES+ISSS 2018. diff --git a/src/content/news/2017-lab-update-aviral-joins-a-panel-discussion-17.md b/src/content/news/2017-lab-update-aviral-joins-a-panel-discussion-17.md new file mode 100644 index 0000000..7619b55 --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-joins-a-panel-discussion-17.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral joins a Panel Discussion on “Autonomous Vehicles: Is our Infrastructure Ready?” [Event at Squire Patton Boggs]" +--- + +Aviral joins a Panel Discussion on “Autonomous Vehicles: Is our Infrastructure Ready?” [Event at Squire Patton Boggs] diff --git a/src/content/news/2017-lab-update-aviral-will-give-a-talk-9.md b/src/content/news/2017-lab-update-aviral-will-give-a-talk-9.md new file mode 100644 index 0000000..a88ac27 --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-will-give-a-talk-9.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Event" +description: "Aviral will give a talk on “Software Techniques for Soft Errors” at UNIST, Republic of Korea." +--- + +Aviral will give a talk on “Software Techniques for Soft Errors” at UNIST, Republic of Korea. diff --git a/src/content/news/2017-lab-update-aviral-will-give-keynote-on-0.md b/src/content/news/2017-lab-update-aviral-will-give-keynote-on-0.md new file mode 100644 index 0000000..7e8d2dc --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-will-give-keynote-on-0.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral will give Keynote on “Time in Cyber-Physical Systems” at IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS)." +--- + +Aviral will give Keynote on “Time in Cyber-Physical Systems” at IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS). diff --git a/src/content/news/2017-lab-update-aviral-will-present-on-scaling-7.md b/src/content/news/2017-lab-update-aviral-will-present-on-scaling-7.md new file mode 100644 index 0000000..a1b11a8 --- /dev/null +++ b/src/content/news/2017-lab-update-aviral-will-present-on-scaling-7.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Aviral will present on Scaling the Real-time Capabilities of Powertrain Controllers in Automotive Systems at NSF CSR PI meeting 2017." +--- + +Aviral will present on Scaling the Real-time Capabilities of Powertrain Controllers in Automotive Systems at NSF CSR PI meeting 2017. diff --git a/src/content/news/2017-lab-update-edward-and-mohammad-s-paper-18.md b/src/content/news/2017-lab-update-edward-and-mohammad-s-paper-18.md new file mode 100644 index 0000000..101dd50 --- /dev/null +++ b/src/content/news/2017-lab-update-edward-and-mohammad-s-paper-18.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Publication" +description: "Edward and Mohammad‘s paper on “Crossroads – Time-Sensitive Autonomous Intersection Management” is the Best paper candidate at Design Automation Conference 2017. Congratulations!" +--- + +Edward and Mohammad‘s paper on “Crossroads – Time-Sensitive Autonomous Intersection Management” is the Best paper candidate at Design Automation Conference 2017. Congratulations! diff --git a/src/content/news/2017-lab-update-edward-and-mohammads-paper-on-3.md b/src/content/news/2017-lab-update-edward-and-mohammads-paper-on-3.md new file mode 100644 index 0000000..e2feed4 --- /dev/null +++ b/src/content/news/2017-lab-update-edward-and-mohammads-paper-on-3.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Publication" +description: "Edward and Mohammad’s paper on “Crossroads – Time-Sensitive Autonomous Intersection Management” was the Best paper candidate at Design Automation Conference 2017." +--- + +Edward and Mohammad’s paper on “Crossroads – Time-Sensitive Autonomous Intersection Management” was the Best paper candidate at Design Automation Conference 2017. diff --git a/src/content/news/2017-lab-update-jian-successfully-defended-his-ph-5.md b/src/content/news/2017-lab-update-jian-successfully-defended-his-ph-5.md new file mode 100644 index 0000000..8358d70 --- /dev/null +++ b/src/content/news/2017-lab-update-jian-successfully-defended-his-ph-5.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Jian successfully defended his Ph.D. dissertation — Scratchpad Management in Software Managed Manycore Architectures. Congratulations, Dr. Jian Cai!" +--- + +Jian successfully defended his Ph.D. dissertation — Scratchpad Management in Software Managed Manycore Architectures. Congratulations, Dr. Jian Cai! diff --git a/src/content/news/2017-lab-update-mohammad-received-a-12.md b/src/content/news/2017-lab-update-mohammad-received-a-12.md new file mode 100644 index 0000000..e40cf6a --- /dev/null +++ b/src/content/news/2017-lab-update-mohammad-received-a-12.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Mohammad received A. Richard Newton Young Student Fellowship at 54th Design Automation Conference (DAC 2017)." +--- + +Mohammad received A. Richard Newton Young Student Fellowship at 54th Design Automation Conference (DAC 2017). diff --git a/src/content/news/2017-lab-update-mohammadreza-and-mohammad-s-paper-13.md b/src/content/news/2017-lab-update-mohammadreza-and-mohammad-s-paper-13.md new file mode 100644 index 0000000..2784b56 --- /dev/null +++ b/src/content/news/2017-lab-update-mohammadreza-and-mohammad-s-paper-13.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Publication" +description: "MohammadReza and Mohammad‘s paper on “Timestamp Temporal Logic (TTL) for Time Testing of Cyber-Physical Systems” is accepted for publication at EMSOFT 2017. Congratulations!" +--- + +MohammadReza and Mohammad‘s paper on “Timestamp Temporal Logic (TTL) for Time Testing of Cyber-Physical Systems” is accepted for publication at EMSOFT 2017. Congratulations! diff --git a/src/content/news/2017-lab-update-moslem-and-dheerajs-paper-on-8.md b/src/content/news/2017-lab-update-moslem-and-dheerajs-paper-on-8.md new file mode 100644 index 0000000..09cecd6 --- /dev/null +++ b/src/content/news/2017-lab-update-moslem-and-dheerajs-paper-on-8.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Publication" +description: "Moslem and Dheeraj’s paper on “NEMESIS: A Software Approach for Computing in Presence of Soft Errors” is accepted for publication at ICCAD 2017. Congratulations!" +--- + +Moslem and Dheeraj’s paper on “NEMESIS: A Software Approach for Computing in Presence of Soft Errors” is accepted for publication at ICCAD 2017. Congratulations! diff --git a/src/content/news/2017-lab-update-moslem-shail-and-maheshs-papers-1.md b/src/content/news/2017-lab-update-moslem-shail-and-maheshs-papers-1.md new file mode 100644 index 0000000..c4641d0 --- /dev/null +++ b/src/content/news/2017-lab-update-moslem-shail-and-maheshs-papers-1.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Publication" +description: "Moslem, Shail and Mahesh’s papers are accepted for publication at DATE 2018." +--- + +Moslem, Shail and Mahesh’s papers are accepted for publication at DATE 2018. diff --git a/src/content/news/2017-lab-update-moslems-paper-on-an-integrated-19.md b/src/content/news/2017-lab-update-moslems-paper-on-an-integrated-19.md new file mode 100644 index 0000000..853b1de --- /dev/null +++ b/src/content/news/2017-lab-update-moslems-paper-on-an-integrated-19.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "Publication" +description: "Moslem’s paper on “An Integrated safe and fast recovery scheme from soft errors” is accepted for publication at DAC 2017." +--- + +Moslem’s paper on “An Integrated safe and fast recovery scheme from soft errors” is accepted for publication at DAC 2017. diff --git a/src/content/news/2017-lab-update-yooseong-defended-his-thesis-on-21.md b/src/content/news/2017-lab-update-yooseong-defended-his-thesis-on-21.md new file mode 100644 index 0000000..eb9d137 --- /dev/null +++ b/src/content/news/2017-lab-update-yooseong-defended-his-thesis-on-21.md @@ -0,0 +1,7 @@ +--- +date: "2017" +type: "General" +description: "Yooseong defended his thesis  on “WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems” successfully. Congratulations!" +--- + +Yooseong defended his thesis  on “WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems” successfully. Congratulations! diff --git a/src/content/news/2018-award-shail-received-outstanding-computer-engineering-0.md b/src/content/news/2018-award-shail-received-outstanding-computer-engineering-0.md new file mode 100644 index 0000000..7b4e460 --- /dev/null +++ b/src/content/news/2018-award-shail-received-outstanding-computer-engineering-0.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Award" +description: "Shail received “Outstanding Computer Engineering TA Award” from SCIDSE, ASU in 2018." +--- + +Shail received “Outstanding Computer Engineering TA Award” from SCIDSE, ASU in 2018. diff --git a/src/content/news/2018-lab-update-asu-researchers-partner-with-local-4.md b/src/content/news/2018-lab-update-asu-researchers-partner-with-local-4.md new file mode 100644 index 0000000..f86e527 --- /dev/null +++ b/src/content/news/2018-lab-update-asu-researchers-partner-with-local-4.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "ASU researchers partner with Local Motors for Electric AVs In-Wheel Motor Design." +--- + +ASU researchers partner with Local Motors for Electric AVs In-Wheel Motor Design. diff --git a/src/content/news/2018-lab-update-aviral-is-featured-in-a-3.md b/src/content/news/2018-lab-update-aviral-is-featured-in-a-3.md new file mode 100644 index 0000000..8d42d3f --- /dev/null +++ b/src/content/news/2018-lab-update-aviral-is-featured-in-a-3.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "Aviral is featured in a NewsWise article, asking ‘Why we would try to simulate human driving in AVs, when human driving is inherently flawed?’" +--- + +Aviral is featured in a NewsWise article, asking ‘Why we would try to simulate human driving in AVs, when human driving is inherently flawed?’ diff --git a/src/content/news/2018-lab-update-aviral-is-organizing-acmieee-early-11.md b/src/content/news/2018-lab-update-aviral-is-organizing-acmieee-early-11.md new file mode 100644 index 0000000..0aa463a --- /dev/null +++ b/src/content/news/2018-lab-update-aviral-is-organizing-acmieee-early-11.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "Aviral is organizing ACM/IEEE Early Career Workshop at DAC 2018." +--- + +Aviral is organizing ACM/IEEE Early Career Workshop at DAC 2018. diff --git a/src/content/news/2018-lab-update-aviral-is-serving-as-a-1.md b/src/content/news/2018-lab-update-aviral-is-serving-as-a-1.md new file mode 100644 index 0000000..030a510 --- /dev/null +++ b/src/content/news/2018-lab-update-aviral-is-serving-as-a-1.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "Aviral is serving as a guest editor of a special issue of IET Computers & Digital Techniques on Energy-efficient Computing for Embedded and IoT Devices." +--- + +Aviral is serving as a guest editor of a special issue of IET Computers & Digital Techniques on Energy-efficient Computing for Embedded and IoT Devices. diff --git a/src/content/news/2018-lab-update-aviral-is-serving-as-an-19.md b/src/content/news/2018-lab-update-aviral-is-serving-as-an-19.md new file mode 100644 index 0000000..a58a54e --- /dev/null +++ b/src/content/news/2018-lab-update-aviral-is-serving-as-an-19.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "Aviral is serving as an associate editor of IEEE Transactions on Computer-Aided Design of integrated circuits and systems (TCAD)." +--- + +Aviral is serving as an associate editor of IEEE Transactions on Computer-Aided Design of integrated circuits and systems (TCAD). diff --git a/src/content/news/2018-lab-update-aviral-talks-about-autonomous-vehicles-14.md b/src/content/news/2018-lab-update-aviral-talks-about-autonomous-vehicles-14.md new file mode 100644 index 0000000..632f8c7 --- /dev/null +++ b/src/content/news/2018-lab-update-aviral-talks-about-autonomous-vehicles-14.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Event" +description: "Aviral talks about Autonomous vehicles traveling wrong road to safety [ASU Now] [science@ASU] [Office of University Initiatives, ASU] [Claims Journal]" +--- + +Aviral talks about Autonomous vehicles traveling wrong road to safety [ASU Now] [science@ASU] [Office of University Initiatives, ASU] [Claims Journal] diff --git a/src/content/news/2018-lab-update-aviral-will-give-a-talk-18.md b/src/content/news/2018-lab-update-aviral-will-give-a-talk-18.md new file mode 100644 index 0000000..df930a6 --- /dev/null +++ b/src/content/news/2018-lab-update-aviral-will-give-a-talk-18.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Event" +description: "Aviral will give a talk on “Can Software Techniques Protect from Soft Errors?” at University of Michigan, Ann Arbor." +--- + +Aviral will give a talk on “Can Software Techniques Protect from Soft Errors?” at University of Michigan, Ann Arbor. diff --git a/src/content/news/2018-lab-update-aviral-will-present-on-coarsegrained-2.md b/src/content/news/2018-lab-update-aviral-will-present-on-coarsegrained-2.md new file mode 100644 index 0000000..d96a5a1 --- /dev/null +++ b/src/content/news/2018-lab-update-aviral-will-present-on-coarsegrained-2.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "Aviral will present on “Coarse-Grained Reconfigurable Arrays for Accelerating Beyond GPUs” at Future Chips Forum 2018, Tsinghua University." +--- + +Aviral will present on “Coarse-Grained Reconfigurable Arrays for Accelerating Beyond GPUs” at Future Chips Forum 2018, Tsinghua University. diff --git a/src/content/news/2018-lab-update-aviral-will-present-on-energy-8.md b/src/content/news/2018-lab-update-aviral-will-present-on-energy-8.md new file mode 100644 index 0000000..f5fce8f --- /dev/null +++ b/src/content/news/2018-lab-update-aviral-will-present-on-energy-8.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Event" +description: "Aviral will present on Energy efficient acceleration of residual neural networks using CGRA at ARM Research Summit 2018. [Talk] [Slides] [insideHPC]" +--- + +Aviral will present on Energy efficient acceleration of residual neural networks using CGRA at ARM Research Summit 2018. [Talk] [Slides] [insideHPC] diff --git a/src/content/news/2018-lab-update-human-influence-makes-autonomous-vehicles-13.md b/src/content/news/2018-lab-update-human-influence-makes-autonomous-vehicles-13.md new file mode 100644 index 0000000..599e36f --- /dev/null +++ b/src/content/news/2018-lab-update-human-influence-makes-autonomous-vehicles-13.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "Human Influence makes Autonomous Vehicles Programming Unsafe [Insurance Journal] [NewsWise]" +--- + +Human Influence makes Autonomous Vehicles Programming Unsafe [Insurance Journal] [NewsWise] diff --git a/src/content/news/2018-lab-update-mohammad-and-mohammadreza-s-paper-6.md b/src/content/news/2018-lab-update-mohammad-and-mohammadreza-s-paper-6.md new file mode 100644 index 0000000..fb40009 --- /dev/null +++ b/src/content/news/2018-lab-update-mohammad-and-mohammadreza-s-paper-6.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Publication" +description: "Mohammad and MohammadReza‘s paper on “RIM: Robust Intersection Management for Connected Autonomous Vehicles” is accepted for publication at RTSS 2018. Congratulations!" +--- + +Mohammad and MohammadReza‘s paper on “RIM: Robust Intersection Management for Connected Autonomous Vehicles” is accepted for publication at RTSS 2018. Congratulations! diff --git a/src/content/news/2018-lab-update-mohammadreza-s-paper-on-an-15.md b/src/content/news/2018-lab-update-mohammadreza-s-paper-on-an-15.md new file mode 100644 index 0000000..739064a --- /dev/null +++ b/src/content/news/2018-lab-update-mohammadreza-s-paper-on-an-15.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Publication" +description: "MohammadReza‘s paper on “An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems” is accepted for publication at DAC 2018. Congratulations!" +--- + +MohammadReza‘s paper on “An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems” is accepted for publication at DAC 2018. Congratulations! diff --git a/src/content/news/2018-lab-update-moslem-and-hwisoo-s-paper-0.md b/src/content/news/2018-lab-update-moslem-and-hwisoo-s-paper-0.md new file mode 100644 index 0000000..fcf2d03 --- /dev/null +++ b/src/content/news/2018-lab-update-moslem-and-hwisoo-s-paper-0.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Publication" +description: "Moslem and Hwisoo‘s paper on “Exploring Software Redundant Multi-threading for Soft/Hard Error Detection and Recovery” is accepted for publication at DATE 2019." +--- + +Moslem and Hwisoo‘s paper on “Exploring Software Redundant Multi-threading for Soft/Hard Error Detection and Recovery” is accepted for publication at DATE 2019. diff --git a/src/content/news/2018-lab-update-moslems-paper-on-a-compiler-17.md b/src/content/news/2018-lab-update-moslems-paper-on-a-compiler-17.md new file mode 100644 index 0000000..7c4fa49 --- /dev/null +++ b/src/content/news/2018-lab-update-moslems-paper-on-a-compiler-17.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Publication" +description: "Moslem’s paper on “A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments” is accepted to appear in IEEE Transactions on Reliability." +--- + +Moslem’s paper on “A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments” is accepted to appear in IEEE Transactions on Reliability. diff --git a/src/content/news/2018-lab-update-recent-editorial-of-acm-transactions-7.md b/src/content/news/2018-lab-update-recent-editorial-of-acm-transactions-7.md new file mode 100644 index 0000000..6e4e00d --- /dev/null +++ b/src/content/news/2018-lab-update-recent-editorial-of-acm-transactions-7.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "Recent editorial of ACM Transactions on Embedded Computing Systems (TECS) nicely summarizes the lessons learned from ACM/IEEE Early Career Workshop, which was co-organized by Aviral at DAC 2018." +--- + +Recent editorial of ACM Transactions on Embedded Computing Systems (TECS) nicely summarizes the lessons learned from ACM/IEEE Early Career Workshop, which was co-organized by Aviral at DAC 2018. diff --git a/src/content/news/2018-lab-update-shail-s-paper-on-ramp-16.md b/src/content/news/2018-lab-update-shail-s-paper-on-ramp-16.md new file mode 100644 index 0000000..e045537 --- /dev/null +++ b/src/content/news/2018-lab-update-shail-s-paper-on-ramp-16.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Publication" +description: "Shail‘s paper on “RAMP: Resource-Aware Mapping for CGRAs” is accepted for publication at 55th Annual Design Automation Conference (DAC 2018)." +--- + +Shail‘s paper on “RAMP: Resource-Aware Mapping for CGRAs” is accepted for publication at 55th Annual Design Automation Conference (DAC 2018). diff --git a/src/content/news/2018-lab-update-shail-will-present-our-paper-10.md b/src/content/news/2018-lab-update-shail-will-present-our-paper-10.md new file mode 100644 index 0000000..e26eb77 --- /dev/null +++ b/src/content/news/2018-lab-update-shail-will-present-our-paper-10.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Publication" +description: "Shail will present our paper “RAMP: Resource-Aware Mapping for CGRAs” @ DAC 2018, in the session The Art of Mapping for Accelerators, one of the sessions recommended from the industry experts." +--- + +Shail will present our paper “RAMP: Resource-Aware Mapping for CGRAs” @ DAC 2018, in the session The Art of Mapping for Accelerators, one of the sessions recommended from the industry experts. diff --git a/src/content/news/2018-lab-update-the-show-avirals-interview-on-9.md b/src/content/news/2018-lab-update-the-show-avirals-interview-on-9.md new file mode 100644 index 0000000..578e20e --- /dev/null +++ b/src/content/news/2018-lab-update-the-show-avirals-interview-on-9.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "General" +description: "The Show: Aviral’s interview on Should Autonomous Car Makers Slow Down Testing?" +--- + +The Show: Aviral’s interview on Should Autonomous Car Makers Slow Down Testing? diff --git a/src/content/news/2018-lab-update-yooseong-mohammad-jing-and-jinnpeans-5.md b/src/content/news/2018-lab-update-yooseong-mohammad-jing-and-jinnpeans-5.md new file mode 100644 index 0000000..554d7f6 --- /dev/null +++ b/src/content/news/2018-lab-update-yooseong-mohammad-jing-and-jinnpeans-5.md @@ -0,0 +1,7 @@ +--- +date: "2018" +type: "Publication" +description: "Yooseong, Mohammad, Jing and Jinn-Pean’s papers are accepted to appear at International Conference on VLSI Design and Embedded Systems 2019." +--- + +Yooseong, Mohammad, Jing and Jinn-Pean’s papers are accepted to appear at International Conference on VLSI Design and Embedded Systems 2019. diff --git a/src/content/news/2019-lab-update-abhishek-and-reileys-article-on-16.md b/src/content/news/2019-lab-update-abhishek-and-reileys-article-on-16.md new file mode 100644 index 0000000..66492e9 --- /dev/null +++ b/src/content/news/2019-lab-update-abhishek-and-reileys-article-on-16.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Publication" +description: "Abhishek and Reiley’s article on “Control Flow Checking or Not? (for Soft Errors)” is accepted for publication in ACM Transactions on Embedded Computing Systems (TECS)." +--- + +Abhishek and Reiley’s article on “Control Flow Checking or Not? (for Soft Errors)” is accepted for publication in ACM Transactions on Embedded Computing Systems (TECS). diff --git a/src/content/news/2019-lab-update-aviral-is-on-the-panel-5.md b/src/content/news/2019-lab-update-aviral-is-on-the-panel-5.md new file mode 100644 index 0000000..d327cf0 --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-is-on-the-panel-5.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Aviral is on the panel that will discuss  “Teaching New Technologies in Computer Architecture” at the Workshop on Computer Architecture Education, Held in conjunction with the 46th International Symposium on Computer Architecture (ISCA 2019)." +--- + +Aviral is on the panel that will discuss  “Teaching New Technologies in Computer Architecture” at the Workshop on Computer Architecture Education, Held in conjunction with the 46th International Symposium on Computer Architecture (ISCA 2019). diff --git a/src/content/news/2019-lab-update-aviral-is-serving-as-a-1.md b/src/content/news/2019-lab-update-aviral-is-serving-as-a-1.md new file mode 100644 index 0000000..0ca12c6 --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-is-serving-as-a-1.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Aviral is serving as a guest editor of a special issue of ACM Transactions on Cyber-Physical Systems on Time for CPS. [TCPS Special Issue on ACM Digital Library]" +--- + +Aviral is serving as a guest editor of a special issue of ACM Transactions on Cyber-Physical Systems on Time for CPS. [TCPS Special Issue on ACM Digital Library] diff --git a/src/content/news/2019-lab-update-aviral-is-serving-as-a-10.md b/src/content/news/2019-lab-update-aviral-is-serving-as-a-10.md new file mode 100644 index 0000000..d676ad0 --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-is-serving-as-a-10.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Aviral is serving as a guest editor of a special issue of ACM Transactions on Embedded Computing Systems on Languages Compilers Tools and Theory of Embedded Systems. [TECS Special Issue on ACM Digital Library]" +--- + +Aviral is serving as a guest editor of a special issue of ACM Transactions on Embedded Computing Systems on Languages Compilers Tools and Theory of Embedded Systems. [TECS Special Issue on ACM Digital Library] diff --git a/src/content/news/2019-lab-update-aviral-is-serving-as-a-18.md b/src/content/news/2019-lab-update-aviral-is-serving-as-a-18.md new file mode 100644 index 0000000..88168b6 --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-is-serving-as-a-18.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Aviral is serving as a guest editor of a special issue of ACM Transactions on Cyber-Physical Systems on Time for CPS." +--- + +Aviral is serving as a guest editor of a special issue of ACM Transactions on Cyber-Physical Systems on Time for CPS. diff --git a/src/content/news/2019-lab-update-aviral-is-serving-as-a-20.md b/src/content/news/2019-lab-update-aviral-is-serving-as-a-20.md new file mode 100644 index 0000000..020ce60 --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-is-serving-as-a-20.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Aviral is serving as a Program Committee Chair of LCTES 2019." +--- + +Aviral is serving as a Program Committee Chair of LCTES 2019. diff --git a/src/content/news/2019-lab-update-aviral-presented-at-asu-transportation-14.md b/src/content/news/2019-lab-update-aviral-presented-at-asu-transportation-14.md new file mode 100644 index 0000000..0cb4bf9 --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-presented-at-asu-transportation-14.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Event" +description: "Aviral presented at ASU Transportation Seminar on “Time in cyber-physical systems“. [Talk]" +--- + +Aviral presented at ASU Transportation Seminar on “Time in cyber-physical systems“. [Talk] diff --git a/src/content/news/2019-lab-update-aviral-presented-on-programmable-8.md b/src/content/news/2019-lab-update-aviral-presented-on-programmable-8.md new file mode 100644 index 0000000..5a106b1 --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-presented-on-programmable-8.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Aviral presented on “Programmable Test Track for AVs” at a workshop on Consensus Safety Measurement Methodologies for ADS-Equipped Vehicles co-organized by NIST. [Webcast] [Workshop Report]" +--- + +Aviral presented on “Programmable Test Track for AVs” at a workshop on Consensus Safety Measurement Methodologies for ADS-Equipped Vehicles co-organized by NIST. [Webcast] [Workshop Report] diff --git a/src/content/news/2019-lab-update-aviral-talks-about-digital-license-15.md b/src/content/news/2019-lab-update-aviral-talks-about-digital-license-15.md new file mode 100644 index 0000000..9ff0f59 --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-talks-about-digital-license-15.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Event" +description: "Aviral talks about Digital license plates that cost whopping $499 now an option for Arizona drivers [Fox News]" +--- + +Aviral talks about Digital license plates that cost whopping $499 now an option for Arizona drivers [Fox News] diff --git a/src/content/news/2019-lab-update-aviral-will-give-a-talk-11.md b/src/content/news/2019-lab-update-aviral-will-give-a-talk-11.md new file mode 100644 index 0000000..0d4d21f --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-will-give-a-talk-11.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Event" +description: "Aviral will give a talk on “Software Schemes for Resilience Against Soft Errors” at Karlsruhe Institute of Technology (KIT)." +--- + +Aviral will give a talk on “Software Schemes for Resilience Against Soft Errors” at Karlsruhe Institute of Technology (KIT). diff --git a/src/content/news/2019-lab-update-aviral-will-join-the-panel-17.md b/src/content/news/2019-lab-update-aviral-will-join-the-panel-17.md new file mode 100644 index 0000000..f10732f --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-will-join-the-panel-17.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Aviral will join the panel that will discuss about “Academia-Industry Collaboration: Challenges in the Research Pipeline” at International Conference on VLSI Design and Embedded Systems 2019." +--- + +Aviral will join the panel that will discuss about “Academia-Industry Collaboration: Challenges in the Research Pipeline” at International Conference on VLSI Design and Embedded Systems 2019. diff --git a/src/content/news/2019-lab-update-aviral-will-present-on-programmable-7.md b/src/content/news/2019-lab-update-aviral-will-present-on-programmable-7.md new file mode 100644 index 0000000..b057fba --- /dev/null +++ b/src/content/news/2019-lab-update-aviral-will-present-on-programmable-7.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Aviral will present on programmable dataflow accelerators at workshop on Renegotiating the Levels of Abstraction for the Post Moore’s Law Era, ARM Research Summit 2019. [Slides]" +--- + +Aviral will present on programmable dataflow accelerators at workshop on Renegotiating the Levels of Abstraction for the Post Moore’s Law Era, ARM Research Summit 2019. [Slides] diff --git a/src/content/news/2019-lab-update-dmazerunner-framework-for-optimizing-dataflow-2.md b/src/content/news/2019-lab-update-dmazerunner-framework-for-optimizing-dataflow-2.md new file mode 100644 index 0000000..ffd1932 --- /dev/null +++ b/src/content/news/2019-lab-update-dmazerunner-framework-for-optimizing-dataflow-2.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "dMazeRunner framework for optimizing dataflow acceleration of machine learning models on coarse-grained programmable accelerators is released (alpha)!" +--- + +dMazeRunner framework for optimizing dataflow acceleration of machine learning models on coarse-grained programmable accelerators is released (alpha)! diff --git a/src/content/news/2019-lab-update-mohammad-s-article-on-crossroads-4.md b/src/content/news/2019-lab-update-mohammad-s-article-on-crossroads-4.md new file mode 100644 index 0000000..2226a37 --- /dev/null +++ b/src/content/news/2019-lab-update-mohammad-s-article-on-crossroads-4.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Publication" +description: "Mohammad‘s article on “Crossroads+: A Time-Aware Approach for Intersection Management of Connected Autonomous Vehicles” is accepted for publication in ACM Transactions on Cyber-Physical Systems (TCPS)." +--- + +Mohammad‘s article on “Crossroads+: A Time-Aware Approach for Intersection Management of Connected Autonomous Vehicles” is accepted for publication in ACM Transactions on Cyber-Physical Systems (TCPS). diff --git a/src/content/news/2019-lab-update-moslem-successfully-defended-his-ph-19.md b/src/content/news/2019-lab-update-moslem-successfully-defended-his-ph-19.md new file mode 100644 index 0000000..be48b88 --- /dev/null +++ b/src/content/news/2019-lab-update-moslem-successfully-defended-his-ph-19.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Moslem successfully defended his Ph.D. dissertation — Software Techniques For Dependable Execution. Congratulations, Dr. Moslem Didehban!" +--- + +Moslem successfully defended his Ph.D. dissertation — Software Techniques For Dependable Execution. Congratulations, Dr. Moslem Didehban! diff --git a/src/content/news/2019-lab-update-our-collaborative-paper-titled-encoding-3.md b/src/content/news/2019-lab-update-our-collaborative-paper-titled-encoding-3.md new file mode 100644 index 0000000..0f4d58b --- /dev/null +++ b/src/content/news/2019-lab-update-our-collaborative-paper-titled-encoding-3.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Publication" +description: "Our collaborative paper titled “Encoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic” received the best paper honorable mention at the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2019)." +--- + +Our collaborative paper titled “Encoding and monitoring responsibility sensitive safety rules for automated vehicles in signal temporal logic” received the best paper honorable mention at the 17th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2019). diff --git a/src/content/news/2019-lab-update-our-paper-titled-software-approaches-13.md b/src/content/news/2019-lab-update-our-paper-titled-software-approaches-13.md new file mode 100644 index 0000000..ad1641b --- /dev/null +++ b/src/content/news/2019-lab-update-our-paper-titled-software-approaches-13.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Publication" +description: "Our paper titled “Software Approaches for In-time Resilience” (invited) will appear at the 56th annual design automation conference (DAC 2019)." +--- + +Our paper titled “Software Approaches for In-time Resilience” (invited) will appear at the 56th annual design automation conference (DAC 2019). diff --git a/src/content/news/2019-lab-update-our-paper-titled-static-function-6.md b/src/content/news/2019-lab-update-our-paper-titled-static-function-6.md new file mode 100644 index 0000000..d606457 --- /dev/null +++ b/src/content/news/2019-lab-update-our-paper-titled-static-function-6.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Publication" +description: "Our paper titled “Static Function Prefetching for Efficient Code Management on Scratchpad Memory” is accepted to appear at 37th IEEE International Conference on Computer Design (ICCD 2019)." +--- + +Our paper titled “Static Function Prefetching for Efficient Code Management on Scratchpad Memory” is accepted to appear at 37th IEEE International Conference on Computer Design (ICCD 2019). diff --git a/src/content/news/2019-lab-update-our-research-on-resilient-computing-0.md b/src/content/news/2019-lab-update-our-research-on-resilient-computing-0.md new file mode 100644 index 0000000..6117c3d --- /dev/null +++ b/src/content/news/2019-lab-update-our-research-on-resilient-computing-0.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Our research on resilient computing got featured on the front-page of Ira A. Fulton Schools of Engineering. [Full Article on A soft approach to a hard problem in autonomous vehicles]" +--- + +Our research on resilient computing got featured on the front-page of Ira A. Fulton Schools of Engineering. [Full Article on A soft approach to a hard problem in autonomous vehicles] diff --git a/src/content/news/2019-lab-update-rachel-successfully-defended-her-masters-12.md b/src/content/news/2019-lab-update-rachel-successfully-defended-her-masters-12.md new file mode 100644 index 0000000..efe2bb0 --- /dev/null +++ b/src/content/news/2019-lab-update-rachel-successfully-defended-her-masters-12.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "General" +description: "Rachel successfully defended her master’s thesis — R2IM: Reliable and Robust Intersection Manager Robust to Rogue Vehicles. Congratulations!" +--- + +Rachel successfully defended her master’s thesis — R2IM: Reliable and Robust Intersection Manager Robust to Rogue Vehicles. Congratulations! diff --git a/src/content/news/2019-lab-update-shail-s-paper-titled-dmazerunner-9.md b/src/content/news/2019-lab-update-shail-s-paper-titled-dmazerunner-9.md new file mode 100644 index 0000000..b66866e --- /dev/null +++ b/src/content/news/2019-lab-update-shail-s-paper-titled-dmazerunner-9.md @@ -0,0 +1,7 @@ +--- +date: "2019" +type: "Publication" +description: "Shail‘s paper titled “dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators” is accepted to appear at International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2019) which is affiliated with Embedded Systems Week (ESWEEK)." +--- + +Shail‘s paper titled “dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators” is accepted to appear at International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2019) which is affiliated with Embedded Systems Week (ESWEEK). diff --git a/src/content/news/2020-lab-update-acm-sigbed-blogpost-about-41st-0.md b/src/content/news/2020-lab-update-acm-sigbed-blogpost-about-41st-0.md new file mode 100644 index 0000000..a34fa8f --- /dev/null +++ b/src/content/news/2020-lab-update-acm-sigbed-blogpost-about-41st-0.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "General" +description: "ACM SIGBED Blogpost about 41st IEEE Real-Time Systems Symposium (RTSS 2020), which will be held virtually December 1–4, 2020. Consider attending!" +--- + +ACM SIGBED Blogpost about 41st IEEE Real-Time Systems Symposium (RTSS 2020), which will be held virtually December 1–4, 2020. Consider attending! diff --git a/src/content/news/2020-lab-update-aviral-is-inducted-into-the-1.md b/src/content/news/2020-lab-update-aviral-is-inducted-into-the-1.md new file mode 100644 index 0000000..97db398 --- /dev/null +++ b/src/content/news/2020-lab-update-aviral-is-inducted-into-the-1.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "General" +description: "Aviral is inducted into the National Academy of Inventors, ASU Chapter." +--- + +Aviral is inducted into the National Academy of Inventors, ASU Chapter. diff --git a/src/content/news/2020-lab-update-aviral-is-serving-as-chair-9.md b/src/content/news/2020-lab-update-aviral-is-serving-as-chair-9.md new file mode 100644 index 0000000..da3d1bc --- /dev/null +++ b/src/content/news/2020-lab-update-aviral-is-serving-as-chair-9.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Publication" +description: "Aviral is serving as chair of the Design and Application track for 41st IEEE Real-Time Systems Symposium (RTSS 2020) [Call for papers]." +--- + +Aviral is serving as chair of the Design and Application track for 41st IEEE Real-Time Systems Symposium (RTSS 2020) [Call for papers]. diff --git a/src/content/news/2020-lab-update-aviral-is-serving-as-the-11.md b/src/content/news/2020-lab-update-aviral-is-serving-as-the-11.md new file mode 100644 index 0000000..bfe5b94 --- /dev/null +++ b/src/content/news/2020-lab-update-aviral-is-serving-as-the-11.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "General" +description: "Aviral is serving as the deputy editor-in-chief of IEEE Embedded Systems Letters." +--- + +Aviral is serving as the deputy editor-in-chief of IEEE Embedded Systems Letters. diff --git a/src/content/news/2020-lab-update-aviral-is-serving-as-the-8.md b/src/content/news/2020-lab-update-aviral-is-serving-as-the-8.md new file mode 100644 index 0000000..691d065 --- /dev/null +++ b/src/content/news/2020-lab-update-aviral-is-serving-as-the-8.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Publication" +description: "Aviral is serving as the virtual conference chair of Embedded Systems Week 2020 (ESWEEK 2020) [Call for papers]." +--- + +Aviral is serving as the virtual conference chair of Embedded Systems Week 2020 (ESWEEK 2020) [Call for papers]. diff --git a/src/content/news/2020-lab-update-aviral-will-present-on-13.md b/src/content/news/2020-lab-update-aviral-will-present-on-13.md new file mode 100644 index 0000000..642528c --- /dev/null +++ b/src/content/news/2020-lab-update-aviral-will-present-on-13.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Event" +description: "Aviral will present on “Make Programming Simple Again – Resilience” at the Computer Science Seminar Series of Donald Bren School of Information and Computer Sciences, University of California, Irvine." +--- + +Aviral will present on “Make Programming Simple Again – Resilience” at the Computer Science Seminar Series of Donald Bren School of Information and Computer Sciences, University of California, Irvine. diff --git a/src/content/news/2020-lab-update-mahesh-s-article-crimson-computeintensive-2.md b/src/content/news/2020-lab-update-mahesh-s-article-crimson-computeintensive-2.md new file mode 100644 index 0000000..a1b96e1 --- /dev/null +++ b/src/content/news/2020-lab-update-mahesh-s-article-crimson-computeintensive-2.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Publication" +description: "Mahesh‘s article “CRIMSON: Compute-intensive loop acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs” is accepted for publication in  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)." +--- + +Mahesh‘s article “CRIMSON: Compute-intensive loop acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs” is accepted for publication in  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). diff --git a/src/content/news/2020-lab-update-mahesh-s-paper-on-scaling-12.md b/src/content/news/2020-lab-update-mahesh-s-paper-on-scaling-12.md new file mode 100644 index 0000000..21f4ea0 --- /dev/null +++ b/src/content/news/2020-lab-update-mahesh-s-paper-on-scaling-12.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Publication" +description: "Mahesh‘s paper on “Scaling of Union of Intersections for Inference of Granger Causal Networks from Observational Data” is accepted to appear at 34th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2020)." +--- + +Mahesh‘s paper on “Scaling of Union of Intersections for Inference of Granger Causal Networks from Observational Data” is accepted to appear at 34th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2020). diff --git a/src/content/news/2020-lab-update-mohammad-s-article-on-a-5.md b/src/content/news/2020-lab-update-mohammad-s-article-on-a-5.md new file mode 100644 index 0000000..be313b3 --- /dev/null +++ b/src/content/news/2020-lab-update-mohammad-s-article-on-a-5.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Publication" +description: "Mohammad‘s article on “A Survey on Intersection Management of Connected Autonomous Vehicles” is accepted for publication in ACM Transactions on Cyber-Physical Systems (TCPS)." +--- + +Mohammad‘s article on “A Survey on Intersection Management of Connected Autonomous Vehicles” is accepted for publication in ACM Transactions on Cyber-Physical Systems (TCPS). diff --git a/src/content/news/2020-lab-update-mohammad-s-paper-r2im-robust-7.md b/src/content/news/2020-lab-update-mohammad-s-paper-r2im-robust-7.md new file mode 100644 index 0000000..feb8da6 --- /dev/null +++ b/src/content/news/2020-lab-update-mohammad-s-paper-r2im-robust-7.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Publication" +description: "Mohammad‘s paper “R2IM Robust and Resilient Intersection Management of Connected Autonomous Vehicles” is accepted for presentation at the 23rd Intelligent Transportation Systems Conference (IEEE ITSC 2020)." +--- + +Mohammad‘s paper “R2IM Robust and Resilient Intersection Management of Connected Autonomous Vehicles” is accepted for presentation at the 23rd Intelligent Transportation Systems Conference (IEEE ITSC 2020). diff --git a/src/content/news/2020-lab-update-our-book-chapter-on-3.md b/src/content/news/2020-lab-update-our-book-chapter-on-3.md new file mode 100644 index 0000000..5e70af2 --- /dev/null +++ b/src/content/news/2020-lab-update-our-book-chapter-on-3.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Publication" +description: "Our book chapter on “Design techniques to improve the resilience of computing systems: architectural layer” is published. (Book: Cross-Layer Reliability of Computing Systems, IET, 2020.)" +--- + +Our book chapter on “Design techniques to improve the resilience of computing systems: architectural layer” is published. (Book: Cross-Layer Reliability of Computing Systems, IET, 2020.) diff --git a/src/content/news/2020-lab-update-our-research-on-resilient-and-4.md b/src/content/news/2020-lab-update-our-research-on-resilient-and-4.md new file mode 100644 index 0000000..fa89685 --- /dev/null +++ b/src/content/news/2020-lab-update-our-research-on-resilient-and-4.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "General" +description: "Our research on resilient and robust intersection management is featured in ASU full circle news: Smart transportation systems need to reckon with rogues." +--- + +Our research on resilient and robust intersection management is featured in ASU full circle news: Smart transportation systems need to reckon with rogues. diff --git a/src/content/news/2020-lab-update-preprint-of-our-comprehensive-survey-6.md b/src/content/news/2020-lab-update-preprint-of-our-comprehensive-survey-6.md new file mode 100644 index 0000000..47ab1cd --- /dev/null +++ b/src/content/news/2020-lab-update-preprint-of-our-comprehensive-survey-6.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "General" +description: "Preprint of our comprehensive survey titled “Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights” is now available [arXiv]." +--- + +Preprint of our comprehensive survey titled “Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights” is now available [arXiv]. diff --git a/src/content/news/2020-lab-update-shail-s-paper-titled-dmazerunner-10.md b/src/content/news/2020-lab-update-shail-s-paper-titled-dmazerunner-10.md new file mode 100644 index 0000000..ffe441b --- /dev/null +++ b/src/content/news/2020-lab-update-shail-s-paper-titled-dmazerunner-10.md @@ -0,0 +1,7 @@ +--- +date: "2020" +type: "Publication" +description: "Shail‘s paper titled “dMazeRunner: Optimizing Convolutions on Dataflow Accelerators” is accepted to appear in the session on Array-based Architectures for Energy-efficient Signal Processing Systems at the 45th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2020). [Talk] [Framework]" +--- + +Shail‘s paper titled “dMazeRunner: Optimizing Convolutions on Dataflow Accelerators” is accepted to appear in the session on Array-based Architectures for Energy-efficient Signal Processing Systems at the 45th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2020). [Talk] [Framework] diff --git a/src/content/news/2021-award-dr-Mohammad-received-0.md b/src/content/news/2021-award-dr-Mohammad-received-0.md new file mode 100644 index 0000000..8d1767c --- /dev/null +++ b/src/content/news/2021-award-dr-Mohammad-received-0.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "Award" +description: "Dr. Mohammad received Dean’s Dissertation Award from the Ira. A. Fulton Schools of Engineering. Congratulations!!" +--- + +Dr. Mohammad received Dean’s Dissertation Award from the Ira. A. Fulton Schools of Engineering. Congratulations!! diff --git a/src/content/news/2021-award-our-collaborative-work-for-timesensitive-1.md b/src/content/news/2021-award-our-collaborative-work-for-timesensitive-1.md new file mode 100644 index 0000000..d5dc542 --- /dev/null +++ b/src/content/news/2021-award-our-collaborative-work-for-timesensitive-1.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "Award" +description: "Our collaborative work for time-sensitive programming won second place in the 2021 CPS IoT-Week Student Design Competition (“Networked Computing on the Edge”). Talk: “Ticktalk: One Program to Rule the Intersection”. Congratulations Edward!" +--- + +Our collaborative work for time-sensitive programming won second place in the 2021 CPS IoT-Week Student Design Competition (“Networked Computing on the Edge”). Talk: “Ticktalk: One Program to Rule the Intersection”. Congratulations Edward! diff --git a/src/content/news/2021-lab-update-aviral-provides-his-opinions-in-5.md b/src/content/news/2021-lab-update-aviral-provides-his-opinions-in-5.md new file mode 100644 index 0000000..b97bf66 --- /dev/null +++ b/src/content/news/2021-lab-update-aviral-provides-his-opinions-in-5.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Aviral provides his opinions in ASU’s Essential reading: Books to expand your perspective." +--- + +Aviral provides his opinions in ASU’s Essential reading: Books to expand your perspective. diff --git a/src/content/news/2021-lab-update-aviral-served-as-an-expert-9.md b/src/content/news/2021-lab-update-aviral-served-as-an-expert-9.md new file mode 100644 index 0000000..f4bfe4f --- /dev/null +++ b/src/content/news/2021-lab-update-aviral-served-as-an-expert-9.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Aviral served as an expert coordinator for the First IoT Expert Curiosity University T-Mobile Cohort." +--- + +Aviral served as an expert coordinator for the First IoT Expert Curiosity University T-Mobile Cohort. diff --git a/src/content/news/2021-lab-update-aviral-serves-as-the-surveytutorials-1.md b/src/content/news/2021-lab-update-aviral-serves-as-the-surveytutorials-1.md new file mode 100644 index 0000000..2197f32 --- /dev/null +++ b/src/content/news/2021-lab-update-aviral-serves-as-the-surveytutorials-1.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Aviral serves as the survey/tutorials editor for ACM Transactions of Embedded Computing Systems (TECS). Considering submitting!" +--- + +Aviral serves as the survey/tutorials editor for ACM Transactions of Embedded Computing Systems (TECS). Considering submitting! diff --git a/src/content/news/2021-lab-update-aviral-serves-as-vice-general-7.md b/src/content/news/2021-lab-update-aviral-serves-as-vice-general-7.md new file mode 100644 index 0000000..dc267fa --- /dev/null +++ b/src/content/news/2021-lab-update-aviral-serves-as-vice-general-7.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Aviral serves as vice general chair of Embedded Systems Week (ESWEEK), 2021. Check out the exciting program and join us virtually during October 08-15!" +--- + +Aviral serves as vice general chair of Embedded Systems Week (ESWEEK), 2021. Check out the exciting program and join us virtually during October 08-15! diff --git a/src/content/news/2021-lab-update-aviral-serves-on-the-steering-19.md b/src/content/news/2021-lab-update-aviral-serves-on-the-steering-19.md new file mode 100644 index 0000000..73d01dc --- /dev/null +++ b/src/content/news/2021-lab-update-aviral-serves-on-the-steering-19.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Aviral serves on the Steering Committee of the ACM Languages, Compilers, Tools and Theory of Embedded Systems (LCTES)." +--- + +Aviral serves on the Steering Committee of the ACM Languages, Compilers, Tools and Theory of Embedded Systems (LCTES). diff --git a/src/content/news/2021-lab-update-aviral-will-give-a-keynote-4.md b/src/content/news/2021-lab-update-aviral-will-give-a-keynote-4.md new file mode 100644 index 0000000..c41d19f --- /dev/null +++ b/src/content/news/2021-lab-update-aviral-will-give-a-keynote-4.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Aviral will give a keynote on “Towards Connected and Safe Autonomous Vehicle” at the 25th International Symposium on VLSI Design and Test (VDAT)." +--- + +Aviral will give a keynote on “Towards Connected and Safe Autonomous Vehicle” at the 25th International Symposium on VLSI Design and Test (VDAT). diff --git a/src/content/news/2021-lab-update-hwisoo-and-moslems-paper-titled-18.md b/src/content/news/2021-lab-update-hwisoo-and-moslems-paper-titled-18.md new file mode 100644 index 0000000..e425a86 --- /dev/null +++ b/src/content/news/2021-lab-update-hwisoo-and-moslems-paper-titled-18.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "Publication" +description: "Hwisoo and Moslem’s paper titled “CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults” is accepted to appear at Design, Automation and Test in Europe Conference (DATE)." +--- + +Hwisoo and Moslem’s paper titled “CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults” is accepted to appear at Design, Automation and Test in Europe Conference (DATE). diff --git a/src/content/news/2021-lab-update-looking-for-some-summer-reading-15.md b/src/content/news/2021-lab-update-looking-for-some-summer-reading-15.md new file mode 100644 index 0000000..a4071fe --- /dev/null +++ b/src/content/news/2021-lab-update-looking-for-some-summer-reading-15.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Looking for some summer reading? Check out annual recommendations from ASU faculty, including our own Aviral Shrivastava." +--- + +Looking for some summer reading? Check out annual recommendations from ASU faculty, including our own Aviral Shrivastava. diff --git a/src/content/news/2021-lab-update-mahesh-successfully-defended-his-ph-3.md b/src/content/news/2021-lab-update-mahesh-successfully-defended-his-ph-3.md new file mode 100644 index 0000000..7d414e7 --- /dev/null +++ b/src/content/news/2021-lab-update-mahesh-successfully-defended-his-ph-3.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Mahesh successfully defended his Ph.D. dissertation — “Compiler Design for Accelerating Applications on Coarse-Grained Reconfigurable Architectures”. Congratulations, Dr. Balasubramanian!" +--- + +Mahesh successfully defended his Ph.D. dissertation — “Compiler Design for Accelerating Applications on Coarse-Grained Reconfigurable Architectures”. Congratulations, Dr. Balasubramanian! diff --git a/src/content/news/2021-lab-update-mohammad-successfully-defended-his-ph-13.md b/src/content/news/2021-lab-update-mohammad-successfully-defended-his-ph-13.md new file mode 100644 index 0000000..4b38e1a --- /dev/null +++ b/src/content/news/2021-lab-update-mohammad-successfully-defended-his-ph-13.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Mohammad successfully defended his Ph.D. dissertation — “Safe and Robust Cooperative Algorithm for Connected Autonomous Vehicles”. Congratulations, Dr. Khayatian!" +--- + +Mohammad successfully defended his Ph.D. dissertation — “Safe and Robust Cooperative Algorithm for Connected Autonomous Vehicles”. Congratulations, Dr. Khayatian! diff --git a/src/content/news/2021-lab-update-mohammadreza-successfully-defended-his-ph-11.md b/src/content/news/2021-lab-update-mohammadreza-successfully-defended-his-ph-11.md new file mode 100644 index 0000000..7df3462 --- /dev/null +++ b/src/content/news/2021-lab-update-mohammadreza-successfully-defended-his-ph-11.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Mohammadreza successfully defended his Ph.D. dissertation — “A Methodology and Formalism to Handle Timing Uncertainties in Cyber-Physical Systems”. Congratulations, Dr. Mohammadreza!" +--- + +Mohammadreza successfully defended his Ph.D. dissertation — “A Methodology and Formalism to Handle Timing Uncertainties in Cyber-Physical Systems”. Congratulations, Dr. Mohammadreza! diff --git a/src/content/news/2021-lab-update-mohammads-paper-on-cooperative-driving-16.md b/src/content/news/2021-lab-update-mohammads-paper-on-cooperative-driving-16.md new file mode 100644 index 0000000..a5ff478 --- /dev/null +++ b/src/content/news/2021-lab-update-mohammads-paper-on-cooperative-driving-16.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "Publication" +description: "Mohammad’s paper on “Cooperative Driving of Connected Autonomous Vehicles in Smart Cities using Responsibility-Sensitive Safety Rules” is accepted for publication in International Conference on Cyber-Physical Systems (ICCPS)." +--- + +Mohammad’s paper on “Cooperative Driving of Connected Autonomous Vehicles in Smart Cities using Responsibility-Sensitive Safety Rules” is accepted for publication in International Conference on Cyber-Physical Systems (ICCPS). diff --git a/src/content/news/2021-lab-update-our-collaborative-paper-comprehensive-failure-2.md b/src/content/news/2021-lab-update-our-collaborative-paper-comprehensive-failure-2.md new file mode 100644 index 0000000..ee6cd59 --- /dev/null +++ b/src/content/news/2021-lab-update-our-collaborative-paper-comprehensive-failure-2.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "Publication" +description: "Our collaborative paper “Comprehensive Failure Analysis against Soft Errors from Hardware and Software Perspectives” is accepted to appear at the 39th IEEE International Conference on Computer Design (ICCD 2021)." +--- + +Our collaborative paper “Comprehensive Failure Analysis against Soft Errors from Hardware and Software Perspectives” is accepted to appear at the 39th IEEE International Conference on Computer Design (ICCD 2021). diff --git a/src/content/news/2021-lab-update-our-collaborative-paper-spx64-a-20.md b/src/content/news/2021-lab-update-our-collaborative-paper-spx64-a-20.md new file mode 100644 index 0000000..af1a2b9 --- /dev/null +++ b/src/content/news/2021-lab-update-our-collaborative-paper-spx64-a-20.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "Publication" +description: "Our collaborative paper “SPX64: A Scratchpad Memory for General-Purpose Microprocessors” is accepted for publication in ACM Transactions on Architecture and Code Optimization (TACO) (to be presented at HiPEAC)." +--- + +Our collaborative paper “SPX64: A Scratchpad Memory for General-Purpose Microprocessors” is accepted for publication in ACM Transactions on Architecture and Code Optimization (TACO) (to be presented at HiPEAC). diff --git a/src/content/news/2021-lab-update-our-collaborative-work-on-a-8.md b/src/content/news/2021-lab-update-our-collaborative-work-on-a-8.md new file mode 100644 index 0000000..9ab1174 --- /dev/null +++ b/src/content/news/2021-lab-update-our-collaborative-work-on-a-8.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Our collaborative work on “A Framework and DSL for Distributed, Energy-constrained, and Time-sensitive Applications” appears at Workshop on Implementation, Compilation, Optimization of OO Languages, Programs and Systems at ECOOP and ISSTA." +--- + +Our collaborative work on “A Framework and DSL for Distributed, Energy-constrained, and Time-sensitive Applications” appears at Workshop on Implementation, Compilation, Optimization of OO Languages, Programs and Systems at ECOOP and ISSTA. diff --git a/src/content/news/2021-lab-update-our-research-on-connected-autonomous-14.md b/src/content/news/2021-lab-update-our-research-on-connected-autonomous-14.md new file mode 100644 index 0000000..c50fd2f --- /dev/null +++ b/src/content/news/2021-lab-update-our-research-on-connected-autonomous-14.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "General" +description: "Our research on connected autonomous vehicles was presented at 2021 STEM EXPO Week from the Science Olympiad. [Video]" +--- + +Our research on connected autonomous vehicles was presented at 2021 STEM EXPO Week from the Science Olympiad. [Video] diff --git a/src/content/news/2021-lab-update-our-survey-paper-on-accelerating-6.md b/src/content/news/2021-lab-update-our-survey-paper-on-accelerating-6.md new file mode 100644 index 0000000..0d8c98f --- /dev/null +++ b/src/content/news/2021-lab-update-our-survey-paper-on-accelerating-6.md @@ -0,0 +1,7 @@ +--- +date: "2021" +type: "Publication" +description: "Our survey paper on accelerating sparse and compact ML/DNN models is accepted for publication in the Proceedings of the IEEE — flagship publication of the IEEE. Congratulations Shail!!" +--- + +Our survey paper on accelerating sparse and compact ML/DNN models is accepted for publication in the Proceedings of the IEEE — flagship publication of the IEEE. Congratulations Shail!! diff --git a/src/content/news/2022-award-edward-was-selected-as-arcs-1.md b/src/content/news/2022-award-edward-was-selected-as-arcs-1.md new file mode 100644 index 0000000..ec05c46 --- /dev/null +++ b/src/content/news/2022-award-edward-was-selected-as-arcs-1.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Award" +description: "Edward was selected as ARCS (The Achievement Rewards for College Scientists) scholar for the year 2022-2023." +--- + +Edward was selected as ARCS (The Achievement Rewards for College Scientists) scholar for the year 2022-2023. diff --git a/src/content/news/2022-award-mohammad-and-mohammadrezas-patent-on-5.md b/src/content/news/2022-award-mohammad-and-mohammadrezas-patent-on-5.md new file mode 100644 index 0000000..f94f4fe --- /dev/null +++ b/src/content/news/2022-award-mohammad-and-mohammadrezas-patent-on-5.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Award" +description: "Mohammad and MohammadReza’s patent on “Systems and Methods for Intersection Management for Connected Autonomous Vehicles” is granted by US PTO. Congratulations!" +--- + +Mohammad and MohammadReza’s patent on “Systems and Methods for Intersection Management for Connected Autonomous Vehicles” is granted by US PTO. Congratulations! diff --git a/src/content/news/2022-award-moslem-received-the-best-poster-2.md b/src/content/news/2022-award-moslem-received-the-best-poster-2.md new file mode 100644 index 0000000..82eee40 --- /dev/null +++ b/src/content/news/2022-award-moslem-received-the-best-poster-2.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Award" +description: "Moslem received the best poster award at the Ph.D. forum, DAC 2017 for his thesis on “Software Schemes to Tolerate Hardware Faults for Safety-Critical Applications”." +--- + +Moslem received the best poster award at the Ph.D. forum, DAC 2017 for his thesis on “Software Schemes to Tolerate Hardware Faults for Safety-Critical Applications”. diff --git a/src/content/news/2022-award-shail-is-awarded-the-meritbased-3.md b/src/content/news/2022-award-shail-is-awarded-the-meritbased-3.md new file mode 100644 index 0000000..da93741 --- /dev/null +++ b/src/content/news/2022-award-shail-is-awarded-the-meritbased-3.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Award" +description: "Shail is awarded the merit-based Completion Fellowship from Arizona State University. Congratulations!" +--- + +Shail is awarded the merit-based Completion Fellowship from Arizona State University. Congratulations! diff --git a/src/content/news/2022-award-shail-receives-the-competitive-outstanding-4.md b/src/content/news/2022-award-shail-receives-the-competitive-outstanding-4.md new file mode 100644 index 0000000..a62b16c --- /dev/null +++ b/src/content/news/2022-award-shail-receives-the-competitive-outstanding-4.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Award" +description: "Shail receives the competitive “Outstanding Research Award” from ASU Graduate and Professional Students Association (for the 2021-2022 term). Congratulations!" +--- + +Shail receives the competitive “Outstanding Research Award” from ASU Graduate and Professional Students Association (for the 2021-2022 term). Congratulations! diff --git a/src/content/news/2022-award-shail-wins-silver-medal-at-0.md b/src/content/news/2022-award-shail-wins-silver-medal-at-0.md new file mode 100644 index 0000000..1719286 --- /dev/null +++ b/src/content/news/2022-award-shail-wins-silver-medal-at-0.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Award" +description: "Shail wins Silver Medal at ACM Student Research Competition (SRC), hosted by ACM SIGBED (Special Interest Group on Embedded Systems). Congratulations!" +--- + +Shail wins Silver Medal at ACM Student Research Competition (SRC), hosted by ACM SIGBED (Special Interest Group on Embedded Systems). Congratulations! diff --git a/src/content/news/2022-lab-update-aviral-and-shail-are-invited-26.md b/src/content/news/2022-lab-update-aviral-and-shail-are-invited-26.md new file mode 100644 index 0000000..05b9f18 --- /dev/null +++ b/src/content/news/2022-lab-update-aviral-and-shail-are-invited-26.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Publication" +description: "Aviral and Shail are invited to organize a special session on “Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems” at 40th IEEE VLSI and Test Symposium (VTS 2022). [Paper] [Slides]" +--- + +Aviral and Shail are invited to organize a special session on “Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems” at 40th IEEE VLSI and Test Symposium (VTS 2022). [Paper] [Slides] diff --git a/src/content/news/2022-lab-update-aviral-is-featured-in-the-14.md b/src/content/news/2022-lab-update-aviral-is-featured-in-the-14.md new file mode 100644 index 0000000..1167477 --- /dev/null +++ b/src/content/news/2022-lab-update-aviral-is-featured-in-the-14.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Aviral is featured in the Cronkite News article Digital license plate messages let drivers express themselves." +--- + +Aviral is featured in the Cronkite News article Digital license plate messages let drivers express themselves. diff --git a/src/content/news/2022-lab-update-aviral-serves-as-a-guest-22.md b/src/content/news/2022-lab-update-aviral-serves-as-a-guest-22.md new file mode 100644 index 0000000..ae5913b --- /dev/null +++ b/src/content/news/2022-lab-update-aviral-serves-as-a-guest-22.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Aviral serves as a guest editor of a special issue of Springer Real-Time Systems on Practical and Robust Design of Real-Time Systems." +--- + +Aviral serves as a guest editor of a special issue of Springer Real-Time Systems on Practical and Robust Design of Real-Time Systems. diff --git a/src/content/news/2022-lab-update-aviral-serves-as-the-general-17.md b/src/content/news/2022-lab-update-aviral-serves-as-the-general-17.md new file mode 100644 index 0000000..aa12a35 --- /dev/null +++ b/src/content/news/2022-lab-update-aviral-serves-as-the-general-17.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Event" +description: "Aviral serves as the general chair of ACM/IEEE Embedded Systems Week (ESWEEK) 2022, which is a hybrid conference with Shanghai and Phoenix as on-site locations. Consider participating! [Student Activities] [Education Classes] [Plenary Talks] [Workshops] [Tutorials] [LinkedIn] [Twitter] [YouTube] (Need-based student travel grants and fee waivers available.)" +--- + +Aviral serves as the general chair of ACM/IEEE Embedded Systems Week (ESWEEK) 2022, which is a hybrid conference with Shanghai and Phoenix as on-site locations. Consider participating! [Student Activities] [Education Classes] [Plenary Talks] [Workshops] [Tutorials] [LinkedIn] [Twitter] [YouTube] (Need-based student travel grants and fee waivers available.) diff --git a/src/content/news/2022-lab-update-aviral-serves-as-the-general-30.md b/src/content/news/2022-lab-update-aviral-serves-as-the-general-30.md new file mode 100644 index 0000000..8da544e --- /dev/null +++ b/src/content/news/2022-lab-update-aviral-serves-as-the-general-30.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Publication" +description: "Aviral serves as the general chair of ACM/IEEE Embedded Systems Week (ESWEEK) 2022, which will be organized as a hybrid conference with Shanghai as an on-site location. Consider submitting your best work! [Call for Papers] [LinkedIn] [Twitter] [YouTube]" +--- + +Aviral serves as the general chair of ACM/IEEE Embedded Systems Week (ESWEEK) 2022, which will be organized as a hybrid conference with Shanghai as an on-site location. Consider submitting your best work! [Call for Papers] [LinkedIn] [Twitter] [YouTube] diff --git a/src/content/news/2022-lab-update-aviral-serves-as-the-graduate-19.md b/src/content/news/2022-lab-update-aviral-serves-as-the-graduate-19.md new file mode 100644 index 0000000..6041bac --- /dev/null +++ b/src/content/news/2022-lab-update-aviral-serves-as-the-graduate-19.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Aviral serves as the Graduate Program Chair, Computer Science and Engineering." +--- + +Aviral serves as the Graduate Program Chair, Computer Science and Engineering. diff --git a/src/content/news/2022-lab-update-aviral-was-featured-in-news-1.md b/src/content/news/2022-lab-update-aviral-was-featured-in-news-1.md new file mode 100644 index 0000000..80b220a --- /dev/null +++ b/src/content/news/2022-lab-update-aviral-was-featured-in-news-1.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Aviral was featured in news articles on “High school students learn about artificial intelligence and related career paths“, which was covered by various news media in Arizona." +--- + +Aviral was featured in news articles on “High school students learn about artificial intelligence and related career paths“, which was covered by various news media in Arizona. diff --git a/src/content/news/2022-lab-update-aviral-will-give-a-keynote-7.md b/src/content/news/2022-lab-update-aviral-will-give-a-keynote-7.md new file mode 100644 index 0000000..eae5a3f --- /dev/null +++ b/src/content/news/2022-lab-update-aviral-will-give-a-keynote-7.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Aviral will give a keynote at International Conference on Intelligent Transportation and Smart Cities." +--- + +Aviral will give a keynote at International Conference on Intelligent Transportation and Smart Cities. diff --git a/src/content/news/2022-lab-update-check-out-ieee-hkn-gradlab-5.md b/src/content/news/2022-lab-update-check-out-ieee-hkn-gradlab-5.md new file mode 100644 index 0000000..fdbba85 --- /dev/null +++ b/src/content/news/2022-lab-update-check-out-ieee-hkn-gradlab-5.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Check out IEEE HKN GradLab Episode about graduate school experiences (theme: Interpersonal lab relationship), featuring our own Shail Dave. [Feature Post]" +--- + +Check out IEEE HKN GradLab Episode about graduate school experiences (theme: Interpersonal lab relationship), featuring our own Shail Dave. [Feature Post] diff --git a/src/content/news/2022-lab-update-christian-successfully-defended-his-bachelors-23.md b/src/content/news/2022-lab-update-christian-successfully-defended-his-bachelors-23.md new file mode 100644 index 0000000..ed13b7b --- /dev/null +++ b/src/content/news/2022-lab-update-christian-successfully-defended-his-bachelors-23.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Christian successfully defended his bachelor’s thesis on “Making a Real-Time Operating System for the Raspberry Pi 2B”. [Code]" +--- + +Christian successfully defended his bachelor’s thesis on “Making a Real-Time Operating System for the Raspberry Pi 2B”. [Code] diff --git a/src/content/news/2022-lab-update-consider-participating-in-nsf-workshop-0.md b/src/content/news/2022-lab-update-consider-participating-in-nsf-workshop-0.md new file mode 100644 index 0000000..059ea3e --- /dev/null +++ b/src/content/news/2022-lab-update-consider-participating-in-nsf-workshop-0.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Consider participating in NSF Workshop Panel Discussions on Sustainable Computing, including our own Shail Dave as a topical expert for “Architectures” track." +--- + +Consider participating in NSF Workshop Panel Discussions on Sustainable Computing, including our own Shail Dave as a topical expert for “Architectures” track. diff --git a/src/content/news/2022-lab-update-edward-is-selected-as-arcs-28.md b/src/content/news/2022-lab-update-edward-is-selected-as-arcs-28.md new file mode 100644 index 0000000..89e22ad --- /dev/null +++ b/src/content/news/2022-lab-update-edward-is-selected-as-arcs-28.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Edward is selected as ARCS (The Achievement Rewards for College Scientists) scholar for the year 2022-2023. Congratulations!" +--- + +Edward is selected as ARCS (The Achievement Rewards for College Scientists) scholar for the year 2022-2023. Congratulations! diff --git a/src/content/news/2022-lab-update-edward-s-paper-on-accurate-9.md b/src/content/news/2022-lab-update-edward-s-paper-on-accurate-9.md new file mode 100644 index 0000000..ae4efc4 --- /dev/null +++ b/src/content/news/2022-lab-update-edward-s-paper-on-accurate-9.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Publication" +description: "Edward‘s paper on “Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs” is accepted at the 23rd Intelligent Transportation Systems Conference (IEEE ITSC 2022)." +--- + +Edward‘s paper on “Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs” is accepted at the 23rd Intelligent Transportation Systems Conference (IEEE ITSC 2022). diff --git a/src/content/news/2022-lab-update-hwisoo-and-moslems-paper-titled-4.md b/src/content/news/2022-lab-update-hwisoo-and-moslems-paper-titled-4.md new file mode 100644 index 0000000..ba90da9 --- /dev/null +++ b/src/content/news/2022-lab-update-hwisoo-and-moslems-paper-titled-4.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Publication" +description: "Hwisoo and Moslem’s paper titled “EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults” is accepted for publication in ACM Transactions on Architecture and Code Optimization (ACM TACO)." +--- + +Hwisoo and Moslem’s paper titled “EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults” is accepted for publication in ACM Transactions on Architecture and Code Optimization (ACM TACO). diff --git a/src/content/news/2022-lab-update-maheshs-paper-pathseeker-a-fast-32.md b/src/content/news/2022-lab-update-maheshs-paper-pathseeker-a-fast-32.md new file mode 100644 index 0000000..edbde38 --- /dev/null +++ b/src/content/news/2022-lab-update-maheshs-paper-pathseeker-a-fast-32.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Publication" +description: "Mahesh’s paper “PathSeeker: A Fast Mapping Algorithm for CGRAs” is accepted to appear at 25th International Conference on Design Automation and Test in Europe (DATE), 2022." +--- + +Mahesh’s paper “PathSeeker: A Fast Mapping Algorithm for CGRAs” is accepted to appear at 25th International Conference on Design Automation and Test in Europe (DATE), 2022. diff --git a/src/content/news/2022-lab-update-our-collaborative-paper-compatibility-checking-33.md b/src/content/news/2022-lab-update-our-collaborative-paper-compatibility-checking-33.md new file mode 100644 index 0000000..cfbb788 --- /dev/null +++ b/src/content/news/2022-lab-update-our-collaborative-paper-compatibility-checking-33.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Publication" +description: "Our collaborative paper “Compatibility Checking for Autonomous Lane-Changing Assistance Systems” is accepted to appear at 25th International Conference on Design Automation and Test in Europe (DATE), 2022." +--- + +Our collaborative paper “Compatibility Checking for Autonomous Lane-Changing Assistance Systems” is accepted to appear at 25th International Conference on Design Automation and Test in Europe (DATE), 2022. diff --git a/src/content/news/2022-lab-update-our-paper-plan-b-31.md b/src/content/news/2022-lab-update-our-paper-plan-b-31.md new file mode 100644 index 0000000..035759c --- /dev/null +++ b/src/content/news/2022-lab-update-our-paper-plan-b-31.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Publication" +description: "Our paper “Plan B – Design Methodology for Cyber-Physical Systems Robust to Timing Failure”, in collaboration with Prof. Carlee Joe-Wong, Prof. Jonathan Aldrich (Carnegie Mellon University) and Dr. Bob Iannucci (Google) is accepted for publication in ACM Transactions on Cyber-Physical Systems (TCPS). Congratulations Dr. Mohammad, Prof. MohammadReza, and Edward, and the team!" +--- + +Our paper “Plan B – Design Methodology for Cyber-Physical Systems Robust to Timing Failure”, in collaboration with Prof. Carlee Joe-Wong, Prof. Jonathan Aldrich (Carnegie Mellon University) and Dr. Bob Iannucci (Google) is accepted for publication in ACM Transactions on Cyber-Physical Systems (TCPS). Congratulations Dr. Mohammad, Prof. MohammadReza, and Edward, and the team! diff --git a/src/content/news/2022-lab-update-our-research-on-autonomous-vehicles-25.md b/src/content/news/2022-lab-update-our-research-on-autonomous-vehicles-25.md new file mode 100644 index 0000000..bbf5cf8 --- /dev/null +++ b/src/content/news/2022-lab-update-our-research-on-autonomous-vehicles-25.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Our research on Autonomous Vehicles has been featured in the ASU News article “A new approach to robotics: Innovative helper and assistive robots mark ASU’s celebration of National Robotics Week“." +--- + +Our research on Autonomous Vehicles has been featured in the ASU News article “A new approach to robotics: Innovative helper and assistive robots mark ASU’s celebration of National Robotics Week“. diff --git a/src/content/news/2022-lab-update-sanggu-defended-his-masters-thesis-20.md b/src/content/news/2022-lab-update-sanggu-defended-his-masters-thesis-20.md new file mode 100644 index 0000000..8b81afc --- /dev/null +++ b/src/content/news/2022-lab-update-sanggu-defended-his-masters-thesis-20.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Sanggu defended his master’s thesis titled “Blame-Free Motion Planning in Hybrid Traffic”." +--- + +Sanggu defended his master’s thesis titled “Blame-Free Motion Planning in Hybrid Traffic”. diff --git a/src/content/news/2022-lab-update-shail-is-invited-to-give-8.md b/src/content/news/2022-lab-update-shail-is-invited-to-give-8.md new file mode 100644 index 0000000..42b53e6 --- /dev/null +++ b/src/content/news/2022-lab-update-shail-is-invited-to-give-8.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Event" +description: "Shail is invited to give a talk on “Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators” at DAC-ROAD4NN: Annual International Workshop on Research Open Automatic Design for Neural Networks at the 59th annual ACM/IEEE/ESDA Design Automation Conference (DAC 2022 ). [Check the previous edition here.]" +--- + +Shail is invited to give a talk on “Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators” at DAC-ROAD4NN: Annual International Workshop on Research Open Automatic Design for Neural Networks at the 59th annual ACM/IEEE/ESDA Design Automation Conference (DAC 2022 ). [Check the previous edition here.] diff --git a/src/content/news/2022-lab-update-shail-s-positionvision-paper-on-29.md b/src/content/news/2022-lab-update-shail-s-positionvision-paper-on-29.md new file mode 100644 index 0000000..57668e8 --- /dev/null +++ b/src/content/news/2022-lab-update-shail-s-positionvision-paper-on-29.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "Publication" +description: "Shail‘s position/vision paper on “Accelerator Design 2.0″ — Comprehensive, Reusable, Explainable, and Agile Design Exploration of Next-Gen Hardware Accelerators” is accepted in the annual LATTE workshop, co-located with ACM ASPLOS 2022. [Paper] [Talk]" +--- + +Shail‘s position/vision paper on “Accelerator Design 2.0″ — Comprehensive, Reusable, Explainable, and Agile Design Exploration of Next-Gen Hardware Accelerators” is accepted in the annual LATTE workshop, co-located with ACM ASPLOS 2022. [Paper] [Talk] diff --git a/src/content/news/2022-lab-update-shail-s-research-on-machine-16.md b/src/content/news/2022-lab-update-shail-s-research-on-machine-16.md new file mode 100644 index 0000000..e562a17 --- /dev/null +++ b/src/content/news/2022-lab-update-shail-s-research-on-machine-16.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Shail‘s research on Machine Learning Accelerators is featured in the IEEE Bridge – Graduate Research Spotlight (in volume 118, issue 2) and highlighted by IEEE Eta Kappa Nu on various social media." +--- + +Shail‘s research on Machine Learning Accelerators is featured in the IEEE Bridge – Graduate Research Spotlight (in volume 118, issue 2) and highlighted by IEEE Eta Kappa Nu on various social media. diff --git a/src/content/news/2022-lab-update-shail-will-present-our-survey-6.md b/src/content/news/2022-lab-update-shail-will-present-our-survey-6.md new file mode 100644 index 0000000..7946b04 --- /dev/null +++ b/src/content/news/2022-lab-update-shail-will-present-our-survey-6.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Shail will present our survey and takeaways about “Efficient Sparse NN Processing on Hardware Accelerators: Survey and Insights” at Annual Sparsity in Neural Networks 2022 workshop, co-located meetup with ICML 2022. [Poster] [Tweet]" +--- + +Shail will present our survey and takeaways about “Efficient Sparse NN Processing on Hardware Accelerators: Survey and Insights” at Annual Sparsity in Neural Networks 2022 workshop, co-located meetup with ICML 2022. [Poster] [Tweet] diff --git a/src/content/news/2022-lab-update-shail-will-present-our-work-3.md b/src/content/news/2022-lab-update-shail-will-present-our-work-3.md new file mode 100644 index 0000000..096c6c7 --- /dev/null +++ b/src/content/news/2022-lab-update-shail-will-present-our-work-3.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Shail will present our work on agile and explainable exploration of efficient deep learning accelerators at IBM-IEEE CAS/EDS AI Compute Symposia 2022." +--- + +Shail will present our work on agile and explainable exploration of efficient deep learning accelerators at IBM-IEEE CAS/EDS AI Compute Symposia 2022. diff --git a/src/content/news/2022-lab-update-shails-dissertation-research-on-accelerator-18.md b/src/content/news/2022-lab-update-shails-dissertation-research-on-accelerator-18.md new file mode 100644 index 0000000..079e25b --- /dev/null +++ b/src/content/news/2022-lab-update-shails-dissertation-research-on-accelerator-18.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "Shail’s dissertation research on “Accelerator Design 2.0: Agile, Efficient, Explainable, and Sustainable” appears at the Ph.D. forum in DAC 2022 (59th annual ACM/IEEE/ESDA Design Automation Conference) and IPDPS 2022 (36th IEEE International Parallel & Distributed Processing Symposium)." +--- + +Shail’s dissertation research on “Accelerator Design 2.0: Agile, Efficient, Explainable, and Sustainable” appears at the Ph.D. forum in DAC 2022 (59th annual ACM/IEEE/ESDA Design Automation Conference) and IPDPS 2022 (36th IEEE International Parallel & Distributed Processing Symposium). diff --git a/src/content/news/2022-lab-update-the-stam-center-and-school-13.md b/src/content/news/2022-lab-update-the-stam-center-and-school-13.md new file mode 100644 index 0000000..512cd6e --- /dev/null +++ b/src/content/news/2022-lab-update-the-stam-center-and-school-13.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "The STAM Center and School of Computing and Augmented Intelligence host ESWEEK event [ASU Inner Circle]" +--- + +The STAM Center and School of Computing and Augmented Intelligence host ESWEEK event [ASU Inner Circle] diff --git a/src/content/news/2022-lab-update-we-will-give-a-demo-10.md b/src/content/news/2022-lab-update-we-will-give-a-demo-10.md new file mode 100644 index 0000000..615131f --- /dev/null +++ b/src/content/news/2022-lab-update-we-will-give-a-demo-10.md @@ -0,0 +1,7 @@ +--- +date: "2022" +type: "General" +description: "We will give a demo on “Efficient Hardware/Software Codesigns of NPUs in Minutes!” at ACM SIGDA University Demonstration, DAC 2022. See Teaser." +--- + +We will give a demo on “Efficient Hardware/Software Codesigns of NPUs in Minutes!” at ACM SIGDA University Demonstration, DAC 2022. See Teaser. diff --git a/src/content/news/2023-award-aviral-receives-the-outstanding-service-0.md b/src/content/news/2023-award-aviral-receives-the-outstanding-service-0.md new file mode 100644 index 0000000..a0bd339 --- /dev/null +++ b/src/content/news/2023-award-aviral-receives-the-outstanding-service-0.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Award" +description: "Aviral receives the Outstanding Service Award from the IEEE Council on Electronic Design Automation (CEDA), which is awarded annually for exceptional commitment and service to the EDA community." +--- + +Aviral receives the Outstanding Service Award from the IEEE Council on Electronic Design Automation (CEDA), which is awarded annually for exceptional commitment and service to the EDA community. diff --git a/src/content/news/2023-award-our-project-proposal-is-accepted-2.md b/src/content/news/2023-award-our-project-proposal-is-accepted-2.md new file mode 100644 index 0000000..605e4d5 --- /dev/null +++ b/src/content/news/2023-award-our-project-proposal-is-accepted-2.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Award" +description: "Our project proposal is accepted by competitive SRC AI hardware program from Semiconductor Research Corporation! We are excited for researching on sustainable and agile AI hardware development through “AI for AI”. Congratulations Aviral and Shail." +--- + +Our project proposal is accepted by competitive SRC AI hardware program from Semiconductor Research Corporation! We are excited for researching on sustainable and agile AI hardware development through “AI for AI”. Congratulations Aviral and Shail. diff --git a/src/content/news/2023-award-sanggu-received-outstanding-masters-student-1.md b/src/content/news/2023-award-sanggu-received-outstanding-masters-student-1.md new file mode 100644 index 0000000..74b5edb --- /dev/null +++ b/src/content/news/2023-award-sanggu-received-outstanding-masters-student-1.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Award" +description: "Sanggu received Outstanding Master’s Student Award in Computer Engineering from the School of Computing and Augmented Intelligence (SCAI) at Arizona State University." +--- + +Sanggu received Outstanding Master’s Student Award in Computer Engineering from the School of Computing and Augmented Intelligence (SCAI) at Arizona State University. diff --git a/src/content/news/2023-lab-update-aviral-gives-invited-seminar-talk-7.md b/src/content/news/2023-lab-update-aviral-gives-invited-seminar-talk-7.md new file mode 100644 index 0000000..386d4e3 --- /dev/null +++ b/src/content/news/2023-lab-update-aviral-gives-invited-seminar-talk-7.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Event" +description: "Aviral gives invited seminar talk on “An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis” at InvasIC seminar series, Friedrich-Alexander-Universität." +--- + +Aviral gives invited seminar talk on “An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis” at InvasIC seminar series, Friedrich-Alexander-Universität. diff --git a/src/content/news/2023-lab-update-aviral-is-featured-in-the-5.md b/src/content/news/2023-lab-update-aviral-is-featured-in-the-5.md new file mode 100644 index 0000000..99576bb --- /dev/null +++ b/src/content/news/2023-lab-update-aviral-is-featured-in-the-5.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "General" +description: "Aviral is featured in The State Press article Mile by mile: The self-driving cars of tomorrow are already here." +--- + +Aviral is featured in The State Press article Mile by mile: The self-driving cars of tomorrow are already here. diff --git a/src/content/news/2023-lab-update-aviral-is-invited-as-the-10.md b/src/content/news/2023-lab-update-aviral-is-invited-as-the-10.md new file mode 100644 index 0000000..5de1e85 --- /dev/null +++ b/src/content/news/2023-lab-update-aviral-is-invited-as-the-10.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "General" +description: "Aviral is invited as the speaker for ASU’s International Students Convocation." +--- + +Aviral is invited as the speaker for ASU’s International Students Convocation. diff --git a/src/content/news/2023-lab-update-aviral-serves-on-the-steering-18.md b/src/content/news/2023-lab-update-aviral-serves-on-the-steering-18.md new file mode 100644 index 0000000..1534072 --- /dev/null +++ b/src/content/news/2023-lab-update-aviral-serves-on-the-steering-18.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "General" +description: "Aviral serves on the Steering Committee of ACM/IEEE Embedded Systems Week (ESWEEK)." +--- + +Aviral serves on the Steering Committee of ACM/IEEE Embedded Systems Week (ESWEEK). diff --git a/src/content/news/2023-lab-update-aviral-will-teach-an-education-3.md b/src/content/news/2023-lab-update-aviral-will-teach-an-education-3.md new file mode 100644 index 0000000..cdbcc8e --- /dev/null +++ b/src/content/news/2023-lab-update-aviral-will-teach-an-education-3.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "General" +description: "Aviral will teach an education class on basics of machine learning design at ACM/IEEE Embedded Systems Week (ESWEEK 2023)." +--- + +Aviral will teach an education class on basics of machine learning design at ACM/IEEE Embedded Systems Week (ESWEEK 2023). diff --git a/src/content/news/2023-lab-update-matthew-defended-his-masters-thesis-12.md b/src/content/news/2023-lab-update-matthew-defended-his-masters-thesis-12.md new file mode 100644 index 0000000..9888864 --- /dev/null +++ b/src/content/news/2023-lab-update-matthew-defended-his-masters-thesis-12.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "General" +description: "Matthew defended his master’s thesis titled “B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles” and he would join Intel as AI Software Engineer. Congratulations!" +--- + +Matthew defended his master’s thesis titled “B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles” and he would join Intel as AI Software Engineer. Congratulations! diff --git a/src/content/news/2023-lab-update-matthew-s-paper-baware-blockage-2.md b/src/content/news/2023-lab-update-matthew-s-paper-baware-blockage-2.md new file mode 100644 index 0000000..1614b43 --- /dev/null +++ b/src/content/news/2023-lab-update-matthew-s-paper-baware-blockage-2.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Publication" +description: "Matthew‘s paper “B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles” is accepted to appear at International Conference on Embedded Software (EMSOFT) 2023." +--- + +Matthew‘s paper “B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles” is accepted to appear at International Conference on Embedded Software (EMSOFT) 2023. diff --git a/src/content/news/2023-lab-update-moslem-s-paper-titled-generic-16.md b/src/content/news/2023-lab-update-moslem-s-paper-titled-generic-16.md new file mode 100644 index 0000000..6e2a452 --- /dev/null +++ b/src/content/news/2023-lab-update-moslem-s-paper-titled-generic-16.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Publication" +description: "Moslem‘s paper titled “Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication” is accepted for publication in IEEE Transactions on Dependable and Secure Computing (IEEE TDSC)." +--- + +Moslem‘s paper titled “Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication” is accepted for publication in IEEE Transactions on Dependable and Secure Computing (IEEE TDSC). diff --git a/src/content/news/2023-lab-update-our-research-on-autonomous-vehicles-6.md b/src/content/news/2023-lab-update-our-research-on-autonomous-vehicles-6.md new file mode 100644 index 0000000..49bf36b --- /dev/null +++ b/src/content/news/2023-lab-update-our-research-on-autonomous-vehicles-6.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "General" +description: "Our research on Autonomous Vehicles has been featured in the ASU Fulton Engineering’s News article “ASU research ensures autonomous vehicle safety, reliability” and state/local media including Arizona Commerce Authority, Institute of Automated Mobility." +--- + +Our research on Autonomous Vehicles has been featured in the ASU Fulton Engineering’s News article “ASU research ensures autonomous vehicle safety, reliability” and state/local media including Arizona Commerce Authority, Institute of Automated Mobility. diff --git a/src/content/news/2023-lab-update-our-work-on-giph-generalizable-14.md b/src/content/news/2023-lab-update-our-work-on-giph-generalizable-14.md new file mode 100644 index 0000000..efdc674 --- /dev/null +++ b/src/content/news/2023-lab-update-our-work-on-giph-generalizable-14.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Publication" +description: "Our work on “GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing” (in collaboration with Carnegie Mellon University) is accepted to appear at Sixth Conference on Machine Learning and Systems (MLSys 2023)." +--- + +Our work on “GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing” (in collaboration with Carnegie Mellon University) is accepted to appear at Sixth Conference on Machine Learning and Systems (MLSys 2023). diff --git a/src/content/news/2023-lab-update-our-work-on-making-processor-1.md b/src/content/news/2023-lab-update-our-work-on-making-processor-1.md new file mode 100644 index 0000000..2062b01 --- /dev/null +++ b/src/content/news/2023-lab-update-our-work-on-making-processor-1.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "General" +description: "Our work on making processor design space exploration more explainable is featured on front pages of ASU news, ASU alumni news, ASU Ira Fulton Engineering news and ASU School of Computing and AI etc., ACM (Association of Computing Machinary) Tech News, Communications of the ACM (CACM) news, industry blogs, local media, etc. [News Article: Opening the Black Box]

" +--- + +Our work on making processor design space exploration more explainable is featured on front pages of ASU news, ASU alumni news, ASU Ira Fulton Engineering news and ASU School of Computing and AI etc., ACM (Association of Computing Machinary) Tech News, Communications of the ACM (CACM) news, industry blogs, local media, etc. [News Article: Opening the Black Box]

 diff --git a/src/content/news/2023-lab-update-sanggus-paper-titled-blamefree-motion-11.md b/src/content/news/2023-lab-update-sanggus-paper-titled-blamefree-motion-11.md new file mode 100644 index 0000000..bb0b22a --- /dev/null +++ b/src/content/news/2023-lab-update-sanggus-paper-titled-blamefree-motion-11.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Publication" +description: "Sanggu’s paper titled “Blame-Free Motion Planning in Hybrid Traffic” is accepted for publication in IEEE Transactions on Intelligent Vehicles (ITV)." +--- + +Sanggu’s paper titled “Blame-Free Motion Planning in Hybrid Traffic” is accepted for publication in IEEE Transactions on Intelligent Vehicles (ITV). diff --git a/src/content/news/2023-lab-update-shail-and-aviral-will-present-13.md b/src/content/news/2023-lab-update-shail-and-aviral-will-present-13.md new file mode 100644 index 0000000..3f712c8 --- /dev/null +++ b/src/content/news/2023-lab-update-shail-and-aviral-will-present-13.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Event" +description: "Shail and Aviral will present a virtual seminar talk to Intel Labs on “Agile and Explainable AI Hardware/Software Codesign Exploration”." +--- + +Shail and Aviral will present a virtual seminar talk to Intel Labs on “Agile and Explainable AI Hardware/Software Codesign Exploration”. diff --git a/src/content/news/2023-lab-update-shail-s-paper-titled-automating-4.md b/src/content/news/2023-lab-update-shail-s-paper-titled-automating-4.md new file mode 100644 index 0000000..28ea9b6 --- /dev/null +++ b/src/content/news/2023-lab-update-shail-s-paper-titled-automating-4.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Publication" +description: "Shail‘s paper titled “Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures” is accepted to appear at SRC TECHCON 2023." +--- + +Shail‘s paper titled “Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures” is accepted to appear at SRC TECHCON 2023. diff --git a/src/content/news/2023-lab-update-shail-s-paper-titled-explainabledse-9.md b/src/content/news/2023-lab-update-shail-s-paper-titled-explainabledse-9.md new file mode 100644 index 0000000..f71b582 --- /dev/null +++ b/src/content/news/2023-lab-update-shail-s-paper-titled-explainabledse-9.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Publication" +description: "Shail‘s paper titled “Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis” is accepted to appear at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Congratulations!!" +--- + +Shail‘s paper titled “Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis” is accepted to appear at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Congratulations!! diff --git a/src/content/news/2023-lab-update-we-are-invited-for-a-15.md b/src/content/news/2023-lab-update-we-are-invited-for-a-15.md new file mode 100644 index 0000000..440a853 --- /dev/null +++ b/src/content/news/2023-lab-update-we-are-invited-for-a-15.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "Publication" +description: "We are invited for a special session on “Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level” in the 26th International Conference on Design Automation and Test in Europe (DATE 2023). [Paper]" +--- + +We are invited for a special session on “Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level” in the 26th International Conference on Design Automation and Test in Europe (DATE 2023). [Paper] diff --git a/src/content/news/2023-lab-update-we-are-teaching-a-new-19.md b/src/content/news/2023-lab-update-we-are-teaching-a-new-19.md new file mode 100644 index 0000000..1c04737 --- /dev/null +++ b/src/content/news/2023-lab-update-we-are-teaching-a-new-19.md @@ -0,0 +1,7 @@ +--- +date: "2023" +type: "General" +description: "We are teaching a new course on “Topics in Machine Learning Accelerator Design” at ASU in Spring 2023 (CSE/CEN 598). [Course Reading List]" +--- + +We are teaching a new course on “Topics in Machine Learning Accelerator Design” at ASU in Spring 2023 (CSE/CEN 598). [Course Reading List] diff --git a/src/content/news/2024-award-mahesh-and-avirals-patent-on-1.md b/src/content/news/2024-award-mahesh-and-avirals-patent-on-1.md new file mode 100644 index 0000000..10497e6 --- /dev/null +++ b/src/content/news/2024-award-mahesh-and-avirals-patent-on-1.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "Award" +description: "Mahesh and Aviral’s patent on “Systems and Methods for Improved Mapping of Computational Loops on Reconfigurable Architectures” is granted by US PTO. Congratulations!" +--- + +Mahesh and Aviral’s patent on “Systems and Methods for Improved Mapping of Computational Loops on Reconfigurable Architectures” is granted by US PTO. Congratulations! diff --git a/src/content/news/2024-award-vinayak-has-been-selected-as-0.md b/src/content/news/2024-award-vinayak-has-been-selected-as-0.md new file mode 100644 index 0000000..d8b0cad --- /dev/null +++ b/src/content/news/2024-award-vinayak-has-been-selected-as-0.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "Award" +description: "Vinayak has been selected as a Google CS Research Mentorship Program (CSRMP) Recipient. Congratulations!" +--- + +Vinayak has been selected as a Google CS Research Mentorship Program (CSRMP) Recipient. Congratulations! diff --git a/src/content/news/2024-lab-update-aviral-has-been-selected-for-5.md b/src/content/news/2024-lab-update-aviral-has-been-selected-for-5.md new file mode 100644 index 0000000..7914b41 --- /dev/null +++ b/src/content/news/2024-lab-update-aviral-has-been-selected-for-5.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "General" +description: "Aviral has been selected for the position of Editor-in-Chief of the IEEE Embedded Systems Letters." +--- + +Aviral has been selected for the position of Editor-in-Chief of the IEEE Embedded Systems Letters. diff --git a/src/content/news/2024-lab-update-aviral-is-featured-in-a-1.md b/src/content/news/2024-lab-update-aviral-is-featured-in-a-1.md new file mode 100644 index 0000000..d5bc6b4 --- /dev/null +++ b/src/content/news/2024-lab-update-aviral-is-featured-in-a-1.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "General" +description: "Aviral is featured in a AZFamily article Feds investigating eight incidents involving Waymo driverless cars in Phoenix, Chandler." +--- + +Aviral is featured in a AZFamily article Feds investigating eight incidents involving Waymo driverless cars in Phoenix, Chandler. diff --git a/src/content/news/2024-lab-update-aviral-is-featured-in-a-3.md b/src/content/news/2024-lab-update-aviral-is-featured-in-a-3.md new file mode 100644 index 0000000..bd7c7d1 --- /dev/null +++ b/src/content/news/2024-lab-update-aviral-is-featured-in-a-3.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "General" +description: "Aviral is featured in a Univision Arizona interview ¿Estamos listos para los vehículos autónomos? En Arizona son ya toda una realidad." +--- + +Aviral is featured in a Univision Arizona interview ¿Estamos listos para los vehículos autónomos? En Arizona son ya toda una realidad. diff --git a/src/content/news/2024-lab-update-aviral-serves-as-the-general-6.md b/src/content/news/2024-lab-update-aviral-serves-as-the-general-6.md new file mode 100644 index 0000000..36ad6d0 --- /dev/null +++ b/src/content/news/2024-lab-update-aviral-serves-as-the-general-6.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "General" +description: "Aviral serves as the General Chair of the ACM Languages, Compilers, Tools and Theory of Embedded Systems (LCTES) 2024." +--- + +Aviral serves as the General Chair of the ACM Languages, Compilers, Tools and Theory of Embedded Systems (LCTES) 2024. diff --git a/src/content/news/2024-lab-update-aviral-was-featured-in-the-8.md b/src/content/news/2024-lab-update-aviral-was-featured-in-the-8.md new file mode 100644 index 0000000..938c048 --- /dev/null +++ b/src/content/news/2024-lab-update-aviral-was-featured-in-the-8.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "General" +description: "Aviral was featured in the ABC15 Arizona news on “What to know about Waymo’s plan to drive on freeways”. [Video]" +--- + +Aviral was featured in the ABC15 Arizona news on “What to know about Waymo’s plan to drive on freeways”. [Video] diff --git a/src/content/news/2024-lab-update-our-collaborative-paper-on-cyclebite-9.md b/src/content/news/2024-lab-update-our-collaborative-paper-on-cyclebite-9.md new file mode 100644 index 0000000..6b8fc67 --- /dev/null +++ b/src/content/news/2024-lab-update-our-collaborative-paper-on-cyclebite-9.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "Publication" +description: "Our collaborative paper on “Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs” is published in IEEE Transactions on Computers." +--- + +Our collaborative paper on “Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs” is published in IEEE Transactions on Computers. diff --git a/src/content/news/2024-lab-update-our-paper-on-design-methodology-7.md b/src/content/news/2024-lab-update-our-paper-on-design-methodology-7.md new file mode 100644 index 0000000..3ed5411 --- /dev/null +++ b/src/content/news/2024-lab-update-our-paper-on-design-methodology-7.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "Publication" +description: "Our paper on “Design Methodology for Robust, Distributed Time-Sensitive Applications” is published in IEEE Internet of Things Magazine." +--- + +Our paper on “Design Methodology for Robust, Distributed Time-Sensitive Applications” is published in IEEE Internet of Things Magazine. diff --git a/src/content/news/2024-lab-update-sai-and-kaustubhs-paper-incidentnet-0.md b/src/content/news/2024-lab-update-sai-and-kaustubhs-paper-incidentnet-0.md new file mode 100644 index 0000000..5a6ea83 --- /dev/null +++ b/src/content/news/2024-lab-update-sai-and-kaustubhs-paper-incidentnet-0.md @@ -0,0 +1,7 @@ +--- +date: "2024" +type: "Publication" +description: "Sai and Kaustubh’s paper “IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing” is accepted to appear at the 27th International Conference on Intelligent Transportation Systems (ITSC) 2024." +--- + +Sai and Kaustubh’s paper “IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing” is accepted to appear at the 27th International Conference on Intelligent Transportation Systems (ITSC) 2024. diff --git a/src/content/news/2025-award-atharva-and-kaustubh-were-accepted-3.md b/src/content/news/2025-award-atharva-and-kaustubh-were-accepted-3.md new file mode 100644 index 0000000..33284a2 --- /dev/null +++ b/src/content/news/2025-award-atharva-and-kaustubh-were-accepted-3.md @@ -0,0 +1,7 @@ +--- +date: "2025" +type: "Award" +description: "Atharva and Kaustubh were accepted in the DAC2025: DAC Young Fellow Program." +--- + +Atharva and Kaustubh were accepted in the DAC2025: DAC Young Fellow Program. diff --git a/src/content/news/2025-award-atharva-was-selected-as-the-0.md b/src/content/news/2025-award-atharva-was-selected-as-the-0.md new file mode 100644 index 0000000..d6ac561 --- /dev/null +++ b/src/content/news/2025-award-atharva-was-selected-as-the-0.md @@ -0,0 +1,7 @@ +--- +date: "2025" +type: "Award" +description: "Atharva was selected as the winner of Knowledge Catalyst Award in the Design Automation Conference (DAC) 2025." +--- + +Atharva was selected as the winner of Knowledge Catalyst Award in the Design Automation Conference (DAC) 2025. diff --git a/src/content/news/2025-award-edward-was-selected-as-the-2.md b/src/content/news/2025-award-edward-was-selected-as-the-2.md new file mode 100644 index 0000000..ae5de9c --- /dev/null +++ b/src/content/news/2025-award-edward-was-selected-as-the-2.md @@ -0,0 +1,7 @@ +--- +date: "2025" +type: "Award" +description: "Edward was selected as the recipient of the Graduate College Completion Fellowship for Fall 2025 and Spring 2026." +--- + +Edward was selected as the recipient of the Graduate College Completion Fellowship for Fall 2025 and Spring 2026. diff --git a/src/content/news/2025-award-shail-dave-received-the-computer-4.md b/src/content/news/2025-award-shail-dave-received-the-computer-4.md new file mode 100644 index 0000000..262e6f8 --- /dev/null +++ b/src/content/news/2025-award-shail-dave-received-the-computer-4.md @@ -0,0 +1,7 @@ +--- +date: "2025" +type: "Award" +description: "Shail Dave received the Computer Engineering PhD Outstanding Student Award for Spring 2025. Congratulations!!" +--- + +Shail Dave received the Computer Engineering PhD Outstanding Student Award for Spring 2025. Congratulations!! diff --git a/src/content/news/2025-lab-update-aviral-is-featured-in-a-0.md b/src/content/news/2025-lab-update-aviral-is-featured-in-a-0.md new file mode 100644 index 0000000..e9678cc --- /dev/null +++ b/src/content/news/2025-lab-update-aviral-is-featured-in-a-0.md @@ -0,0 +1,7 @@ +--- +date: "2025" +type: "General" +description: "Aviral is featured in a ASU News article Using AI for smarter metal 3D printing of mission-critical items like propellers." +--- + +Aviral is featured in a ASU News article Using AI for smarter metal 3D printing of mission-critical items like propellers. diff --git a/src/content/news/2025-lab-update-shreehari-and-edwards-paper-tipangle-1.md b/src/content/news/2025-lab-update-shreehari-and-edwards-paper-tipangle-1.md new file mode 100644 index 0000000..092a5ed --- /dev/null +++ b/src/content/news/2025-lab-update-shreehari-and-edwards-paper-tipangle-1.md @@ -0,0 +1,7 @@ +--- +date: "2025" +type: "Publication" +description: "Shreehari and Edward’s paper “TIPAngle: Traffic Tracking at City Scale by Pose Estimation of Pan and
Tilt Intersection Cameras” received best paper award in VLSID 2025 and got featured in the TCVLSI Newsletter Special Edition. link
" +--- + +Shreehari and Edward’s paper “TIPAngle: Traffic Tracking at City Scale by Pose Estimation of Pan and
Tilt Intersection Cameras” received best paper award in VLSID 2025 and got featured in the TCVLSI Newsletter Special Edition. link
diff --git a/src/content/research/ai-compilers.md b/src/content/research/ai-compilers.md new file mode 100644 index 0000000..5402514 --- /dev/null +++ b/src/content/research/ai-compilers.md @@ -0,0 +1,28 @@ +--- +title: "AI-driven Multi-Level Compilers" +status: "Active" +description: "Leveraging machine learning techniques to optimize compiler designs, creating intelligent intermediate representations for emerging and heterogeneous architectures." +icon: "BookOpen" +order: 3 +--- + +## Vision + +As computing enters a post-Moore’s Law era of extreme hardware heterogeneity, traditional compilers can no longer keep pace with the complexity of specialized architectures. We envision a future where compilers serve as intelligent orchestrators, utilizing Multi-level representations to preserve high-level application semantics that are typically lost during translation. To manage the vast optimization space across these diverse platforms, we aim to build AI-driven engines that autonomously learn and apply the best strategies for each workload. + +## Key Research Challenges + +- **The Abstraction Gap in Heterogeneous Computing**: Traditional compilers typically "lower" code into generic representations too early, discarding critical high-level application semantics. This loss of intent prevents the compiler from performing global optimizations that are only visible at higher abstraction tiers. New methodologies that maintain multiple levels of IR simultaneously to exploit domain-specific patterns are needed. +- **Decoupling Cost Models from Optimization Heuristics**: In current compilers, the "pass" (the transformation) and the "cost model" (the logic that decides if the transformation is beneficial) are tightly intertwined. This makes it impossible to update the compiler for new hardware without rewriting core logic. A clean separation of concerns where modular AI-cost models can be plugged into generic optimization passes is needed to enable rapid hardware portability. +- **The Phase Ordering and Pass Selection Problem**: The sequence and selection of optimization passes significantly impact performance, yet the "optimal" order varies wildly between different programs. Standard compilers rely on a fixed order that often leads to sub-optimal results or missed opportunities for acceleration. Intelligent, context-aware agents that can dynamically determine the most effective pass sequence and selection for a specific piece of code are needed to make compilation truly adaptive. + +## Recent Results + +![qml-research](/images/research/aic/dsp-mlir.png) +DSP-MLIR is a multi-level compiler infrastructure that leverages domain-specific abstractions and MLIR-based transformations to automate the mapping and optimization of signal processing applications onto heterogeneous hardware accelerators. + +To demonstrate the power of intent-preserving compilation, we developed DSP-MLIR, an open-source framework built on the MLIR ecosystem. This framework ensures that high-level signal processing intent is preserved and optimized from the source code down to the hardware. + +- **Closing the Abstraction Gap**: DSP-MLIR introduces a high-level, Python-like DSL and a dedicated DSP Dialect with over 90 operations. This preserves domain-specific intent (such as FFTs, filters, and windowing) deep into the compilation flow, allowing for 16 high-level transformations based on DSP theorems that traditional compilers typically miss. +- **Performance & Productivity**: Our results show that DSP-MLIR can reduce development effort by 4x to 5x compared to standard C, while providing a 12% average speedup on CPUs and DSPs and a 10% reduction in binary size compared to state-of-the-art compilers like GCC and Hexagon-Clang. +- **Unified Optimization**: By integrating with the MLIR framework, our work provides a path toward a unified compilation flow where DSP and ML kernels are co-optimized for modern edge processors, enabling seamless deployment across diverse, high-performance platforms. diff --git a/src/content/research/bypass-aware-compiler.md b/src/content/research/bypass-aware-compiler.md new file mode 100644 index 0000000..425b5da --- /dev/null +++ b/src/content/research/bypass-aware-compiler.md @@ -0,0 +1,16 @@ +--- +title: "Bypass Aware Compiler" +status: "Extended" +description: "Code size is an important constraint for many embedded systems, especially the ones in which the code is burnt on ROMs, which can be the major component on the chip. Dual instruction set, one compo..." +icon: "CircuitBoard" +order: 21 +image: "/images/research/bypass-aware-compiler.png" +--- + +## Bypass Aware Compiler + +Code size is an important constraint for many embedded systems, especially the ones in which the code is burnt on ROMs, which can be the major component on the chip. Dual instruction set, one composed of full width instructions, and another composed of narrow instructions is a promising approach to reduce code size. Our research efforts are towards developing tools and techniques to compile for such reduced bit-width Instruction Set Architectures. + +Bypasses or forwarding paths are simple yet widely used feature in modern processors to eliminate some data hazards. With Bypasses, additional datapaths and control logic are added to the processor so that the result of an operation is available for subsequent dependent operations even before it is written in the register file. Paths including the bypasses often are timing critical and add pressure on cycle time, especially the single cycle paths. The delay of bypass logic can be significant for wide issue machines. The situation is aggravated owing to the trend of long pipelines and high degrees of parallelism in modern processors. As a result, most processors can only afford some of the bypasses. The question is, which bypasses to have in the processor, so as to minimize the hardware overhead, but not loose too much performance as compared to a fully bypassed processor. + +Determining optimal bypass configuration requires a true co-design effort in which both the layout effects and the compiler effects must be taken into account. The figure on the right shows a compiler-in-the-loop design methodology for exploring the bypasses in embedded processors. The bypass configuration is described in a text form in an architecture description language (in this case,EXPRESSION). We developed a bypass-sensitive compiler that reads the bypass configuration from the text file, and schedules instructions so as to avoid data hazards due to missing bypasses. We have also parameterized a cycle-accurate simulator to the bypass configuration. Further, we automatically generate the bypass control logic for the processor pipeline, and paramterize the RTL of the processor on the bypass configuration. For a given bypass configuration, the application is then compiled using the bypass-sensitive compiler, simulated on the cycle-accurate simulator to find the run-time, and the cycle-time, area, and power is estimated using the synthesized RTL. Different bypass configurations are explored to find the best bypass configuration. diff --git a/src/content/research/coarse-grain-reconfigurable-arrays.md b/src/content/research/coarse-grain-reconfigurable-arrays.md new file mode 100644 index 0000000..7d67271 --- /dev/null +++ b/src/content/research/coarse-grain-reconfigurable-arrays.md @@ -0,0 +1,16 @@ +--- +title: "Coarse-Grain Reconfigurable Arrays" +status: "Extended" +description: "Need for faster and power-efficient processors has paved the way for many-core processors along with considerable research in accelerators. Acceleration through popular Graphics Processing Units (G..." +icon: "Grid3X3" +order: 19 +image: "/images/research/coarse-grain-reconfigurable-arrays.png" +--- + +## Coarse-Grain Reconfigurable Arrays + +Need for faster and power-efficient processors has paved the way for many-core processors along with considerable research in accelerators. Acceleration through popular Graphics Processing Units (GPUs) is over a broad range of the parallel applications but majorly limited to massively parallel loops and loops with high trip counts. Field programmable gate arrays (FPGAs) on the other hand, are reconfigurable and general-purpose but are marred by low power efficiency due to their fine-grain management. + +Coarse-Grained Reconfigurable Arrays (CGRAs)are promising accelerators, capable of accelerating even non-parallel loops and loops with lower trip-counts. They are programmable yet, power-efficient accelerators. CGRA is an array of Processing Elements (PE) connected through a 2-D network; each PE contains an ALU-like Functional Unit (FU) and a Register File (RF). FUs are capable of executing arithmetic, logical or even memory operations. At every cycle, each PE gets an instruction from the instruction memory, specifying the operation. The PE may read/write the data from/to data memory; data/address bus are shared either by PEs in the same column or by PEs in the same row. CGRA can achieve higher power efficiency due to simpler hardware and intelligent software techniques. [A Short Video on Executing the Loops on CGRA] + +Since CGRA is a simple hardware and all the intelligence and hence the complexity, has been transferred to the software, the compiler should be smart enough to effectively utilize the CGRA resources. One of the widely researched topics in CGRA research is the mapping techniques for CGRAs. Loop to be accelerated is extracted from the application and converted into a Data Dependency Graph (DDG). Problem formulation of the mapping of the DDG onto the target array is NP-complete. Plus, mapping hueristic should be able to generate the mapping with better quality in lower compilation time, as well as it should ensure maximum the usage of the CGRA resources — such as registers, PE units etc. diff --git a/src/content/research/cyber-physical-and-iot-systems.md b/src/content/research/cyber-physical-and-iot-systems.md new file mode 100644 index 0000000..c5a17c6 --- /dev/null +++ b/src/content/research/cyber-physical-and-iot-systems.md @@ -0,0 +1,16 @@ +--- +title: "Cyber-Physical and IoT Systems" +status: "Extended" +description: "Time is a foundational aspect of Cyber-Physical Systems (CPS). Correct timing of system events is critical to optimize responsiveness to the environment, in terms of timeliness, accuracy, and preci..." +icon: "Wifi" +order: 16 +image: "/images/research/cyber-physical-and-iot-systems.png" +--- + +## Cyber-Physical and IoT Systems + +Time is a foundational aspect of Cyber-Physical Systems (CPS). Correct timing of system events is critical to optimize responsiveness to the environment, in terms of timeliness, accuracy, and precision in the knowledge, measurement, prediction, and control of CPS behavior (DAC Special Session 2016). + +In order to design more resilient and reliable CPS, first and foremost, there should be a way to specify the timing constraints that a constructed Cyber-Physical System must meet. Only then, we can seek systematic approaches to check if all timing constraints are being met, and develop correct-by-construction methodologies. In this regard, we have developed a logic, Timestamp Temporal Logic (TTL) to specify the timing constraints on a distributed CPS (TTL-EMSOFT-TECS-2017). Designers can specify the timing requirement that a CPS must satisfy in a succinct and intuitive manner in TTL. For example, they can express that some two events on two different parts of the system must occur within 1 millisecond of each other. Further, we designed an FPGA-based testbed that can hook up to a CPS and take in these timing constraints specified in TTL and verify if the timing constraints are being met (CPS Timing Testbed,ReConfig 2015). One of the great features of using TTL to express timing constraints is that the time monitoring logic becomes very simple. TTL logic does not need to compute whether the constraint is being met at each and every instance of time but it re-evaluates a constraint only when there is an event that can affect the outcome. This enables our approach, TMA to perform online timing monitoring of CPS (TMA-DAC 2018) for less required computation and resources. Furthermore, we have come up with the minimum design parameters of the timing CPS that are required to enable testing the timing of CPS. For example, a system that is sampling at milliseconds level cannot test a timing constraint that has a requirement of accuracy to the level of microseconds (Testbed-DAC-2017). + +We have built several CPS applications to test the need and effectiveness of our approaches. We have built a i) flying paster – a system needed in the printing press to continue the paper feed from another roller when the current roller finishes. ii) We have been able to align the phase of different motors up to milliseconds even when they are connected through the internet. iii) Synchronize the image capture time from different cameras, so that a 3D image reconstruction can be done with minimal blurring, and iv) developed a time-sensitive traffic intersection design for autonomous vehicles (Crossroads-DAC-2017). diff --git a/src/content/research/gpu-computing.md b/src/content/research/gpu-computing.md new file mode 100644 index 0000000..0f96a12 --- /dev/null +++ b/src/content/research/gpu-computing.md @@ -0,0 +1,16 @@ +--- +title: "GPU Computing" +status: "Extended" +description: "With higher performance and better power efficiency, GPU (Graphics Processing Unit) has enabled so-called ‘supercomputing to the masses’. However, the complex memory hierarchy and various architect..." +icon: "Monitor" +order: 15 +image: "/images/research/gpu-computing.png" +--- + +## GPU Computing + +With higher performance and better power efficiency, GPU (Graphics Processing Unit) has enabled so-called ‘supercomputing to the masses’. However, the complex memory hierarchy and various architectural details introduced many optimization rules that make optimizing GPU programs very difficult. Our objective is to enable compiler to find the design choices that lead to better performance and to optimize accordingly. + +As a simple extension to C, CUDA has made programming GPUs so much easier than before. This simple and easy programming model, as well as outstanding performance and power/cost efficiency, popularized GPGPU (General Purpose computing on GPUs), and now GPU is considered as one of the most successful and promising computer architectures for the future. + +Even though to start writing GPGPU applications has become easy, optimizing programs to fully utilize GPU’s performance is very difficult yet. This is because of numerous optimization rules that come from various hardware details. Those performance considerations are mostly on memory access performance. As thousands of cores are accessing the memory concurrently, memory access performance often affects the performance of a program significantly. To optimize an application, the programmer should beware of all the performance considerations and be able to predict the possible impact on performance for each of different design decisions, such as thread block size, shared memory buffer size, or global/shared memory references. diff --git a/src/content/research/intelligent-transportation.md b/src/content/research/intelligent-transportation.md new file mode 100644 index 0000000..04b22e0 --- /dev/null +++ b/src/content/research/intelligent-transportation.md @@ -0,0 +1,31 @@ +--- +title: "Intelligent Transportation Systems" +status: "Active" +description: "Developing robust software, perception pipelines, and safety-critical architectures for next-generation intelligent and autonomous vehicles." +icon: "Car" +order: 2 +--- + +## Vision +We aim to advance the state-of-the-art in two critical directions: first, by enhancing autonomous vehicle perception through multi-modal and cooperative sensing to ensure safe navigation in complex environments; and second, by evolving traffic infrastructure into an intelligent observer capable of detecting incidents and understanding their systemic impact at a city scale. By bridging the gap between vehicle-level sensing and infrastructure-level orchestration, we strive to build a transportation network that is fundamentally resilient to both physical uncertainties and digital vulnerabilities. + +## Key Research Challenges +- **The Perception and Data Gap**: Individual AVs are limited by their own line-of-sight and the extreme rarity of real-world incident data. Multi-modal cooperative sensing and generative "Real-to-Sim" and “Sim-to-Real” modeling are needed to provide vehicles with shared perception and a library of kinematically feasible edge cases for rigorous safety validation. +- **Trust in Cooperative Systems**: Enhancing vehicle intelligence through cooperation introduces the risk of data falsification or sensor malfunctions. Robust security architectures that combine real-time authentication with decentralized consensus are needed to ensure that the "cooperative brain" of a connected fleet remains trustworthy. +- **City-Scale Incident Intelligence**: Relying on centralized, macroscopic traffic data leads to slow response times and low detection accuracy. Scalable, infrastructure-based intelligence that can detect, localize, and quantify the ripple effects of incidents using sparse, microscopic sensing is needed to manage urban resilience at scale. + +## Recent Results +### Theme I: Advancing AVs via Secure, Cooperative Perception + +Our research focuses on extending the "eyes" of the vehicle through cooperation while ensuring the absolute integrity of shared data. Through our work on CONClave (DAC 2024), we developed a tightly coupled authentication and consensus protocol that allows a fleet to identify and isolate malicious or faulty sensors 1.8x faster than existing baselines, ensuring that cooperative perception remains a reliable asset for safe navigation. Furthermore, by replacing static error models with dynamic, parameterized covariance generation, we demonstrated a 1.4x improvement in the accuracy of fusing data between moving vehicles and stationary infrastructure, effectively neutralizing the localization errors inherent in mobile sensing. + +![CONClave](/images/research/its/conclave.png) +CONClave is a secure cooperative perception framework that integrates multi-party authentication, decentralized consensus, and sensor trust-scoring to protect autonomous vehicle fleets from malicious data injection and sensor malfunctions. + +### Theme II: Advancing Infrastructure via Distributed Incident Detection + +Our work on the infrastructure side centers on turning sparse roadside sensors into a high-fidelity monitoring network capable of city-scale oversight. Through the development of IncidentNet (ITSC 2024), we have pioneered a deep learning framework that can detect and localize traffic incidents even when they occur outside a sensor's direct field of view, achieving a 98% detection rate in urban environments with sparse sensor coverage. By utilizing a novel methodology to generate realistic synthetic microscopic traffic data, our frameworks can accurately quantify how local incidents alter traffic flow across the broader city grid, enabling proactive, automated traffic management that mitigates gridlock and improves emergency response. + +![IncidentNet](/images/research/its/incidentnet.png) +IncidentNet is a deep learning framework that utilizes microscopic traffic patterns from sparse roadside sensors to detect, localize, and estimate the severity of traffic incidents, even when they occur outside the sensor's direct field of view. + diff --git a/src/content/research/llm-applications.md b/src/content/research/llm-applications.md new file mode 100644 index 0000000..326dd20 --- /dev/null +++ b/src/content/research/llm-applications.md @@ -0,0 +1,12 @@ +--- +title: "LLM Applications" +status: "Extended" +description: "Research on llm applications at the MPS Lab." +icon: "MessageSquare" +order: 24 +image: "/images/research/llm-applications.png" +--- + +## LLM Applications + +Extended research area covering llm applications. diff --git a/src/content/research/ml-acceleration.md b/src/content/research/ml-acceleration.md new file mode 100644 index 0000000..f337b3b --- /dev/null +++ b/src/content/research/ml-acceleration.md @@ -0,0 +1,28 @@ +--- +title: "Machine Learning Acceleration" +status: "Active" +description: "Hardware-software co-design and architectural innovations for efficient, high-performance execution of deep learning models on specialized accelerators and edge devices." +icon: "Cpu" +order: 1 +--- + +## Vision + +As AI models scale toward trillions of parameters, the bottleneck has shifted from raw computation to the complex interplay between data movement and architectural efficiency. We envision a future of Hardware-Software Co-design, where the execution of ML models is optimized through a deep understanding of both high-level parallelism and low-level hardware structures. Our goal is to build an intelligent orchestration layer that treats heterogeneous accelerators and their underlying memory hierarchies – from scratchpads and DMAs to multi-level caches and HBM – as a unified, programmable fabric. By architecting systems that can autonomously exploit every dimension of parallelism, we aim to redefine the performance limits of next-generation AI. + +## Key Research Challenges + +* **The Multi-Dimensional Parallelism Search Space:** Exploiting a single form of parallelism is no longer enough for modern large-scale models. The challenge lies in the simultaneous orchestration of data, pipeline, and tensor parallelism across a distributed and heterogeneous compute landscape. Scalable optimization frameworks that can discover the "golden" parallelization strategy for a specific model-hardware pair are needed. +* **Architectural Complexity and Memory Hierarchy Management:** Beyond the choice of accelerator lies a dense design space of caches, scratchpad memories, and DMA engines. Traditional execution flows often fail to exploit these low-level resources, leading to data starvation and memory stalls. Hardware-aware compilers that can intelligently manage scratchpad allocation and schedule DMA transfers to hide latency and maximize throughput across multi-level memory hierarchies are needed. +* **Mapping Complexity in Extremely Heterogeneous Systems:** Modern systems integrate a diverse array of compute units (CPUs, NPUs, GPUs, DSPs) and memory types (DDR, LPDDR, HBM, PNM, SSDs). Manually partitioning workloads across such a non-uniform landscape is prohibitively complex. Automated mapping and partitioning engines that can navigate the vast design space of heterogeneous compute and memory to ensure balanced workloads and energy-efficient execution are needed. + +## Recent Results + +![dMazeRunner](/images/research/mla/dmaze.webp) +DMazeRunner provides a holistic framework for exploring and optimizing the spatiotemporal mapping of complex loop nests onto the computational and memory resources of dataflow accelerators.To address the challenge of mapping complex ML workloads onto specialized hardware, we developed dMazeRunner, a framework designed to explore the vast spatiotemporal execution space of perfectly nested loops (such as convolutions and matrix multiplications) on dataflow accelerators. + +To address the challenge of mapping complex ML workloads onto specialized hardware, we developed dMazeRunner, a framework designed to explore the vast spatiotemporal execution space of perfectly nested loops (such as convolutions and matrix multiplications) on dataflow accelerators. + +* **Holistic Representation:** dMazeRunner utilizes a novel, holistic representation of loop nests that succinctly captures diverse execution methods, including various tiling, ordering, and parallelization strategies. +* **Accurate Modeling and Pruning:** The framework employs high-fidelity energy and performance models that explicitly account for computation, communication patterns, and data buffering. By implementing aggressive pruning heuristics, dMazeRunner discards invalid or redundant solutions, reducing search times from days to seconds. +* **Quantifiable Impact:** Our experiments demonstrate that dMazeRunner discovers execution methods that are, on average, 9× better in Energy-Delay-Product (EDP) and 5× faster than prior approaches. Even with rapid heuristics, it identifies solutions within 3% of the optimal, enabling both experts and non-experts to maximize hardware utilization and minimize off-chip memory access. \ No newline at end of file diff --git a/src/content/research/power-temperature-and-variation-aware-computing.md b/src/content/research/power-temperature-and-variation-aware-computing.md new file mode 100644 index 0000000..ee446cc --- /dev/null +++ b/src/content/research/power-temperature-and-variation-aware-computing.md @@ -0,0 +1,16 @@ +--- +title: "Power, Temperature and Variation aware Computing" +status: "Extended" +description: "Power consumption, process variations, and temperature are all problems due to technology scaling to incredible levels. Our approach to deal with power, temperature and process variations is to exp..." +icon: "Thermometer" +order: 20 +image: "/images/research/power-temperature-and-variation-aware-computing.png" +--- + +## Power, Temperature and Variation aware Computing + +Power consumption, process variations, and temperature are all problems due to technology scaling to incredible levels. Our approach to deal with power, temperature and process variations is to expose them to microarchitecture and software levels, where instruction scheduling and component sleep solutions can be developed to handle these issues. + +Two important consequences of technology scaling are the increase in leakage power and increase in variation in the characteristics of manufactured devices. Leakage power is projected to contribute more than 40% of total power budget in processors fabricated in 65 nm technology and beyond. Unlike dynamic power, leakage power is highly sensitive to variations in gate dimensions as well as the operational temperature. High variation in the power consumption results in the significant overestimation of the specification, leading to increased design time/effort and results in significant loss of parameterized yield. Hence, reducing the total power, temperature and the variation in the power consumption is an important problem. + +We introduce a leakage sensor in FUs, and develop a temperature and process variations aware power gating technique. Our power gating approach is based on the IPC, using which it determines how many FUs must be on. Once this is decided, based on the leakage of the FUs (which automatically takes temperature into account), which FUs should be power gates is determined. diff --git a/src/content/research/processor-idle-cycle-aggregation.md b/src/content/research/processor-idle-cycle-aggregation.md new file mode 100644 index 0000000..e4ec6a2 --- /dev/null +++ b/src/content/research/processor-idle-cycle-aggregation.md @@ -0,0 +1,16 @@ +--- +title: "Processor Idle Cycle Aggregation" +status: "Extended" +description: "During execution, a processor is typically stalled for a significant amount of time doing nothing, but waiting for data from memory. However, these stall durations are typically small. Our research..." +icon: "Battery" +order: 25 +image: "/images/research/processor-idle-cycle-aggregation.png" +--- + +## Processor Idle Cycle Aggregation + +During execution, a processor is typically stalled for a significant amount of time doing nothing, but waiting for data from memory. However, these stall durations are typically small. Our research in this area is to aggregate these small but several stall cycles to create a larger stall, during which the processor can be switched to a lower-power mode. + +Figure on the right plots the lengths of processor stalls over the execution of the qsort application from the MiBench benchmark suite running on the Intel XScale processor. Very small stalls (few cycles) represent processor stalls due to pipeline hazards, but a lot of stalls are approximately 30 cycles in length. This reflects the fact that the memory latency of the Intel XScale is about 30 cycles. An important observation from this graph is that although the processor is stalled for a considerable time (approximately 30% of the total program execution time) the length of each processor stall is small. The average length of a processor stall is 4 cycles, but none of them is greater than 100 cycles. + +A processor stall, theoretically is an opportunity for optimization. System throughput and energy can be improved by temporarily switching to a different thread of execution, or the energy consumption of the system may be reduced by switching the processor to a low power state. Next figure shows the power state machine of the Intel XScale processor. In the default mode of operation, the XScale is in RUN state, consuming 450mW. XScale has three low power states: IDLE, DROWSY, and SLEEP. In the IDLE state the clock to the processor is gated, and the processor consumes only 10mW, but it takes 180 processor cycles to switch to and back from the IDLE state. However, no naturally occuring processor stall is more than 100 cycles, therefore there is no opportunity to reduce the power consumption. diff --git a/src/content/research/quantum-ml.md b/src/content/research/quantum-ml.md new file mode 100644 index 0000000..ba83ae2 --- /dev/null +++ b/src/content/research/quantum-ml.md @@ -0,0 +1,28 @@ +--- +title: "Quantum Machine Learning" +status: "Active" +description: "Pioneering the next generation of artificial intelligence by exploring the intersection of quantum computing and advanced machine learning models." +icon: "Brain" +order: 4 +--- + +## Vision + +We strive to create a symbiotic partnership between two transformative frontiers: using machine learning to stabilize quantum hardware and using quantum computing to redefine the limits of ML algorithms. We aim to achieve "Quantum Advantage" on near-term (NISQ) devices by making quantum circuits noise-resilient and adaptive. + +## Key Research Challenges + +- **Barren Plateaus or Vanishing gradients**: The training of QML models is frequently hampered by the "Barren Plateau" phenomenon, a quantum analog to the vanishing gradient problem in classical deep learning. As the number of qubits or the depth of the circuit increases, the gradient of the cost function often vanishes exponentially, leaving the optimization landscape flat and featureless. This makes it nearly impossible for classical optimizers to find a path toward a global minimum. Hardware-efficient ansätz and localized cost functions that preserve gradient signals across high-dimensional Hilbert spaces are needed. +- **NISQ-Era Hardware Constraints**: We are currently operating in the Noisy Intermediate-Scale Quantum (NISQ) era, where quantum devices possess a limited number of qubits and lack full fault tolerance. These systems are highly susceptible to environmental decoherence and gate errors, which accumulate rapidly as circuit depth increases, often drowning out the true "quantum signal" with noise. Addressing this requires the development of noise-resilient algorithms and error-mitigation strategies that can extract meaningful computational results within the limited coherence times of today’s processors. +- **The Data Encoding Bottleneck**: A fundamental challenge in QML is the efficient transformation of classical information into quantum states—a process known as data encoding. While techniques like Amplitude Encoding can represent data exponentially more compactly than classical memory, the gate complexity required to prepare these states often creates a significant computational overhead. Furthermore, the choice of encoding (e.g., Angle vs. Basis vs. Amplitude) acts as a non-linear feature map that dictates the expressivity and generalization power of the entire model. Encoding architectures that can balance high-dimensional representation power with low-depth hardware requirements to ensure a tangible advantage over classical feature engineering are needed. + +## Recent Results + +![qml-research](/images/research/qml/qml.png) +QPMeL learns classical embeddings of quantum data that utilizes a quality-performance trade-off model to optimize the efficiency and accuracy of quantum machine learning pipelines. + +One of our recent breakthroughs is QPMeL (Quantum Polar Metric Learning), a framework designed to bypass the traditional instabilities of quantum training. QPMeL uses a quantum-aware, classically-trained approach: by mapping classical data to the surface of independent unit spheres (aligned with the Bloch sphere), the model learns "Rotational Representations" that translate directly into quantum states. + +- **Overcoming Barren Plateaus**: While standard QML models often struggle with "Barren Plateaus" when trained on quantum hardware, QPMeL offloads the primary optimization to a classical "head." By using our novel Projective Metric Function (PMeF), QPMeL avoids the flat gradients of the quantum loss landscape, ensuring stable and fast convergence even as the system scales. +- **Hardware-Efficiency**: QPMeL encodings are hardware-efficient by design, requiring only a single layer of $R_y$ and $R_z$ gates per qubit. This drastically reduces circuit depth compared to standard ansatz, allowing high-fidelity execution within the limited coherence times of current noisy hardware. +- **Adaptive Representation**: Instead of using fixed, manual mappings, QPMeL utilizes trainable encodings that allow the model to learn the most effective way to separate features in Hilbert space. This results in the first QML model capable of scaling to 10-class classification and 15-way multi-modal (image-text) few-shot learning with state-of-the-art accuracy. diff --git a/src/content/research/real-time-systems.md b/src/content/research/real-time-systems.md new file mode 100644 index 0000000..cf4665b --- /dev/null +++ b/src/content/research/real-time-systems.md @@ -0,0 +1,16 @@ +--- +title: "Real-Time Systems" +status: "Extended" +description: "Our vision:Our vision is to enable correct-by-construction cyber-physical system design using software-managed memory hierarchies with our efficient memory management schemes and accurate analysis ..." +icon: "Clock" +order: 23 +image: "/images/research/real-time-systems.png" +--- + +## Real-Time Systems + +Our vision:Our vision is to enable correct-by-construction cyber-physical system design using software-managed memory hierarchies with our efficient memory management schemes and accurate analysis techniques. + +Cyber-physical systemsare systems in which cyber world interacts with physical world. Software components (in cyber world) monitor and control physical components (in physical world) throughfeedback loops that consist of sensing, computation, and actuation.In these feedback loops, tasks read input from sensors, compute or decide what the desired action is, and perform that action through actuation of physical components. + +Cyber-physical systems havestrict timing constraints that must be satisfied for their correct operations.These timing constraints specify the deadline for each task, by which the task must finish its execution. In safety-critical applications like automotive systems, avionics, medical devices, any failure in this may lead to a catastrophic disaster. For instance, in the example of autonomous driving, the software must finish calculating the amount of braking or steering before it is too late to prevent a crash. It is crucial, therefore, to find the worst-case execution times (WCETs) of all tasks to ensure that all tasks can meet their deadlines.A correct-by-construction approach enables the assertion of the timing correctness at design time, before testing. diff --git a/src/content/research/reduced-bit-width-instruction-set-architecture.md b/src/content/research/reduced-bit-width-instruction-set-architecture.md new file mode 100644 index 0000000..53be846 --- /dev/null +++ b/src/content/research/reduced-bit-width-instruction-set-architecture.md @@ -0,0 +1,16 @@ +--- +title: "Reduced bit-width Instruction Set Architecture" +status: "Extended" +description: "Code size is an important constraint for many embedded systems, especially the ones in which the code is burnt on ROMs, which can be the major component on the chip. Dual instruction set, one compo..." +icon: "Binary" +order: 22 +image: "/images/research/reduced-bit-width-instruction-set-architecture.png" +--- + +## Reduced bit-width Instruction Set Architecture + +Code size is an important constraint for many embedded systems, especially the ones in which the code is burnt on ROMs, which can be the major component on the chip. Dual instruction set, one composed of full width instructions, and another composed of narrow instructions is a promising approach to reduce code size. Our research efforts are towards developing tools and techniques to compile for such reduced bit-width Instruction Set Architectures. + +Programmable RISC processors are increasingly being used to design modern embedded systems. Examples of such systems include consumer electronics items, e.g., cell phones, printers, modems etc. Using RISC processors in such systems offers the advantage of increased design flexibility, high computing power and low on-chip power consumption. However, RISC processor systems suffer from the problem of poor code density which may require more ROM for storing program code. As a large part of the IC area is devoted to the ROM this is a severe limitation for large volume, cost sensitive embedded systems. + +reduced bit-width ISA is an architectural feature in which the processor has two instruction set, one is composed of the normal 32-bit wide instructions, while the other has narrow 16-bit wide instructions. If the application can be expressed only in terms of narrow instructions, then 50% code compression can be achieved. Many embedded processors, including ARM-Thumb, MIPS 32/16 bit TinyRISC, ST100 and the ARC Tangent A5. Processors with rISA dynamically translate (or decompress, or expand) the narrow rISA instructions into corresponding normal instructions. This translation usually occurs before or during the decode stage. Typically, each rISA instruction has an equivalent instruction in the normal instruction set. This makes translation simple and can usually be done with minimal performance penalty. As the translation engine converts rISA instructions into normal instructions, no other hardware is needed to execute rISA instructions. Using rISA optimizes the fetch power of the processor also. This is because, fetch-width of the processor being the same, the processor when operating in rISA mode fetches twice as many rISA instructions (as compared to normal instructions) in each fetch operation. Thus while executing rISA instructions, the processor needs to make lesser fetch requests to the instruction memory. This results in a decrease in power and energy consumption by the instruction memory subsystem. diff --git a/src/content/research/reliability-robustness-ml.md b/src/content/research/reliability-robustness-ml.md new file mode 100644 index 0000000..65aa6c1 --- /dev/null +++ b/src/content/research/reliability-robustness-ml.md @@ -0,0 +1,17 @@ +--- +title: "Reliability for Machine Learning" +status: "Extended" +description: "Ensuring the dependability and predictable performance of machine learning systems in the presence of hardware faults and adversarial conditions." +icon: "Shield" +order: 5 +--- + +## Reliability for Machine Learning + +As machine learning models are deployed in mission-critical applications, their reliability becomes paramount. Our extended research focuses on: + +- **Fault Tolerance**: Developing techniques to detect and recover from transient and permanent hardware faults during neural network execution. +- **Software-level Solutions**: Creating robust algorithms that can tolerate underlying hardware inaccuracies without significant loss in model accuracy. +- **Adversarial Robustness**: Understanding and mitigating vulnerabilities of AI systems to intentional perturbations or unexpected inputs. + +We strive to build machine learning systems that are not just intelligent, but also thoroughly dependable. diff --git a/src/content/research/software-branch-hinting.md b/src/content/research/software-branch-hinting.md new file mode 100644 index 0000000..379a6c3 --- /dev/null +++ b/src/content/research/software-branch-hinting.md @@ -0,0 +1,16 @@ +--- +title: "Software Branch Hinting" +status: "Extended" +description: "As power-efficiency becomes the paramount concern in processor design, architectures are coming up that completely do away with hardware branch prediction, and rely solely on software branch hintin..." +icon: "GitBranch" +order: 18 +image: "/images/research/software-branch-hinting.png" +--- + +## Software Branch Hinting + +As power-efficiency becomes the paramount concern in processor design, architectures are coming up that completely do away with hardware branch prediction, and rely solely on software branch hinting. A popular example is the Synergistic Processing Unit (SPU) in the IBM Cell processor. To be able to minimize the branch penalty using branch hint instructions, in addition to estimating the branch probabilities, it is important to carefully insert branch hints. + +For software branch hinted processors, the application may contain branch hint instructions which indicate that the branch instructions at specified PC addresses will jump to specified target addresses. Just like hardware branch predictors, software branch hinting mechanism also requires a Branch Target Buffer (BTB). When a hint instruction is executed, the BTB entry is first updated, and then target instructions are loaded to the Hint Target Buffer from the specified target address.The hardware usually fetches instructions from Inline Prefetch Buffer which is constantly loaded with the sequential instructions according to PC address. When a branch instruction is fetched, the PC address is compared with the branch address in the BTB entry. If it matches, the instructions are fetched from Hint Target Buffer instead of Inline Prefetch Buffer. + +For software branch hinting to work best, there two fundamental considerations: first is to estimate the taken probabilities of branches, and the second is to find the locations in the code for branch hint instructions to minimize branch penalty. Even if we know the taken probabilities of all the branches, minimizing branch penalty by means of branch hint instructions is not trivial. The reasons derive from two constraints of the given architecture. Firstly, for a branch hint to be effective, there must be some separation between a branch and its hint. The hint instruction must be executed several instructions earlier than the branch. Second, only a limited number (one for the Cell SPU) of branch hints can be active at any given time. For example, if two branches are too closely located in the control flow, the second branch cannot have enough separation. To hint the second branch, its hint needs to be placed above the first branch, and this will overwrite the hint for the first branch.Thus, hints may conflict with each other, and reduce the achievable benefits. diff --git a/src/content/research/software-managed-manycore-smm.md b/src/content/research/software-managed-manycore-smm.md new file mode 100644 index 0000000..2409c0e --- /dev/null +++ b/src/content/research/software-managed-manycore-smm.md @@ -0,0 +1,16 @@ +--- +title: "Software Managed Manycore (SMM)" +status: "Extended" +description: "Multicore with Software Programmable Memory" +icon: "Server" +order: 17 +image: "/images/research/software-managed-manycore-smm.png" +--- + +## Software Managed Manycore (SMM) + +Multicore with Software Programmable Memory + +Multi-cores provide a way to continue increasing performance, without much increase in the power consumption of the processor. One major challenge in developing multi-core architectures is scaling the memory hierarchy. Maintaining the illusion of a single unified memory in hardware is becoming infeasible. This is because: first, that the power and performance overheads of automatic memory management in hardware (i.e. by caches) is becoming prohibitive, and second, that cache coherency protocols do not scale to hundreds and thousands of cores. + +Software Managed Manycore (SMM) architectures are scalable multi-core designs that employ Software Programmable Memory (SPM) in each core — the more power-efficient alternative of caches. The above figure shows an example of SMM architectures. SMM processors can only access code and data that are current on their local SPM. That is to say, the data movement between the close-to-processor memory and the main memory has to be done explicitly in software — typically through the use of Direct Memory Access (DMA) instructions. Our research objective is to develop compiler technology to automatically compile applications for these architectures with memory transfer requests automatically inserted at proper program points and make them usable. diff --git a/src/content/resources/ai-compilers.md b/src/content/resources/ai-compilers.md new file mode 100644 index 0000000..416b8fb --- /dev/null +++ b/src/content/resources/ai-compilers.md @@ -0,0 +1,11 @@ +--- +researchArea: "AI-driven Multi-Level Compilers" +resources: + - title: "DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing" + type: "Paper" + url: "https://mpslab-asu.github.io/publications/papers/Kumar2025LCTES.pdf" + authors: "Abhinav Kumar, Atharva Khedkar, Hwisoo So, Megan Kuo, Ameya Gurjar, Partha Biswas, Aviral Shrivastava" + description: "A domain-specific language and MLIR dialect for efficient compilation of digital signal processing workloads." +--- + +Curated resources for AI-driven Multi-Level Compilers research. diff --git a/src/content/resources/intelligent-transportation.md b/src/content/resources/intelligent-transportation.md new file mode 100644 index 0000000..d005a5f --- /dev/null +++ b/src/content/resources/intelligent-transportation.md @@ -0,0 +1,16 @@ +--- +researchArea: "Intelligent Transportation Systems" +resources: + - title: "Conclave - Secure and Robust Cooperative Perception for CAVs" + type: "Paper" + url: "https://mpslab-asu.github.io/publications/papers/Andert2024DAC.pdf" + authors: "Edward Andert, Francis Mendoza, Hans Behrens, Aviral Shrivastava" + description: "A tightly coupled authentication and consensus protocol for cooperative perception in autonomous vehicle fleets." + - title: "IncidentNet: Traffic Incident Detection, Localization and Severity Estimation" + type: "Paper" + url: "https://mpslab-asu.github.io/publications/papers/Peddiraju2024ITSC.pdf" + authors: "Sai Shashank Peddiraju, Kaustubh Harapanahalli, Edward Andert, Aviral Shrivastava" + description: "A deep learning framework for traffic incident detection using sparse roadside sensors." +--- + +Curated resources for Intelligent Transportation Systems research. diff --git a/src/content/resources/ml-acceleration.md b/src/content/resources/ml-acceleration.md new file mode 100644 index 0000000..9da7eb6 --- /dev/null +++ b/src/content/resources/ml-acceleration.md @@ -0,0 +1,35 @@ +--- +researchArea: "Machine Learning Acceleration" +resources: + - title: "Explainable-DSE: Agile and Explainable Exploration of DL Accelerator Codesigns" + type: "Paper" + url: "https://mpslab-asu.github.io/publications/papers/Dave2024ASPLOS.pdf" + authors: "Shail Dave, Tony Nowatzki, Aviral Shrivastava" + description: "An agile DSE framework using bottleneck analysis for efficient hardware/software codesign of DNN accelerators." + - title: "Efficient processing of deep neural networks: A tutorial and survey" + type: "Paper" + authors: "Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, and Joel S. Emer" + - title: "Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks" + type: "Paper" + authors: "Yu-Hsin Chen, Joel Emer, and Vivienne Sze" + - title: "In-datacenter performance analysis of a tensor processing unit" + type: "Paper" + authors: "Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, et al." + - title: "dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators" + type: "Paper" + authors: "Shail Dave, Youngbin Kim, Sasikanth Avancha, Kyoungwoo Lee, Aviral Shrivastava" + - title: "Timeloop: A Systematic Approach to DNN Accelerator Evaluation" + type: "Paper" + authors: "Angshuman Parashar, Priyanka Raina, Sophia Shao, et al." + - title: "Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights" + type: "Paper" + authors: "Shail Dave, Riyadh Baghdadi, Tony Nowatzki, et al." + - title: "TVM: end-to-end optimization stack for deep learning" + type: "Paper" + authors: "Tianqi Chen, Thierry Moreau, Ziheng Jiang, et al." + - title: "Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding" + type: "Paper" + authors: "Song Han, Huizi Mao, and William J. Dally" +--- + +Curated resources for Machine Learning Acceleration research. diff --git a/src/content/resources/quantum-ml.md b/src/content/resources/quantum-ml.md new file mode 100644 index 0000000..8e8528e --- /dev/null +++ b/src/content/resources/quantum-ml.md @@ -0,0 +1,11 @@ +--- +researchArea: "Quantum Machine Learning" +resources: + - title: "Quantum Polar Metric Learning: Efficient Classically Learned Quantum Embeddings" + type: "Paper" + url: "https://mpslab-asu.github.io/publications/papers/Sharma2023Arxiv.pdf" + authors: "Vinayak Sharma, Aviral Shrivastava" + description: "A quantum metric learning approach achieving 3X better multi-class separation with half the gates and depth." +--- + +Curated resources for Quantum Machine Learning research. diff --git a/src/data/publications.bib b/src/data/publications.bib new file mode 100644 index 0000000..6b1127a --- /dev/null +++ b/src/data/publications.bib @@ -0,0 +1,3104 @@ +@conference{Joshi2025codes, + title = {ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors}, + author = {Sumedh Joshi and Hwisoo So and Aviral Shrivastava }, + url = {https://mpslab-asu.github.io/publications/papers/Joshi2025CODES.pdf, pdf https://mpslab-asu.github.io/publications/slides/Joshi2025CODES.pptx, slides}, + year = {2025}, + date = {2025-10-03}, + urldate = {2025-10-03}, + booktitle = {Proceedings of the 2025 International Conference on Hardware/Software Codesign and System Synthesis}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Conference} +} + +@mastersthesis{Harapanahalli2025THESIS, + title = {SIGN: A Scalable Incident Detection, Localization, and Severity Estimation using Graph Neural Networks}, + author = {Kaustubh Harapanahalli}, + url = {https://mpslab-asu.github.io/publications/papers/Harapanahalli2025THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Harapanahalli2025THESIS.pptx, slides}, + year = {2025}, + date = {2025-07-07}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{Lagudu2025LCTES, + title = {LUCI: Lightweight UI Command Interface}, + author = {Guna Lagudu and Vinayak Sharma and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lagudu2025LCTES.pdf, pdf https://mpslab-asu.github.io/publications/slides/Lagudu2025LCTES.pdf, slides}, + doi = {10.1145/3735452.3735536}, + year = {2025}, + date = {2025-06-16}, + urldate = {2025-06-16}, + booktitle = {Proceedings of Languages, Compilers, Tools and Theory of Embedded Systems (LCTES)}, + research = {}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{Kumar2025LCTES, + title = {DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing}, + author = {Abhinav Kumar and Atharva Khedkar and Hwisoo So and Megan Kuo and Ameya Gurjar and Partha Biswas and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kumar2025LCTES.pdf, pdf https://mpslab-asu.github.io/publications/slides/Kumar2025LCTES.pptx, slides}, + doi = {10.1145/3735452.3735527}, + year = {2025}, + date = {2025-06-16}, + urldate = {2025-06-16}, + booktitle = {Proceedings of Languages, Compilers, Tools and Theory of Embedded Systems (LCTES)}, + research = {}, + pubstate = {published}, + category = {Proceedings} +} + +@patent{Khayatian2025Patent, + title = {Cooperative Driving of Connected Autonomous Vehicles in Smart Cities using Responsibility-Sensitive Safety Rules}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Harshith Alamsetti and Aviral Shrivastava }, + url = {https://patents.google.com/patent/US12246753, Google Patents}, + year = {2025}, + date = {2025-03-11}, + urldate = {2025-03-11}, + howpublished = {https://patents.google.com/patent/US12246753/}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {Patent} +} + +@conference{Jagadeesha2025VLSISoC, + title = {TIPANGLE: Traffic Tracking at City Scale by Pose Estimation of Pan and Tilt Traffic Cameras on Edge Devices}, + author = {Shreehari Jagadeesha and Edward Andert and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jagadeesha2025VLSID.pdf, pdf https://mpslab-asu.github.io/publications/slides/Jagadeesha2025VLSID.pdf, slides}, + year = {2025}, + date = {2025-01-21}, + urldate = {2025-01-21}, + booktitle = {IEEE International Conference on Very Large System Integration and Embedded Systems}, + journal = {IEEE International Conference Very Large System Integration and Embedded Systems}, + research = {Best Paper Award, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Conference} +} + +@article{Kim2024Access, + title = {Adversarial Defense on Harmony: Reverse Attack for Robust Models Against Adversarial Attack}, + author = {Yebon Kim and Jinhyo Jung and Hyunjun Kim and Hwisoo So and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee and Uiwon Hwang}, + url = {https://mpslab-asu.github.io/publications/papers/Hwisoo2024IEEE.pdf, pdf}, + year = {2024}, + date = {2024-11-25}, + urldate = {2024-11-25}, + booktitle = {IEEE Access}, + journal = {IEEE Access}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Article} +} + +@mastersthesis{Joshi2025thesis, + title = {ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors}, + author = {Sumedh Joshi}, + url = {https://mpslab-asu.github.io/publications/papers/Joshi2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Joshi2024THESIS.pdf, slides}, + year = {2024}, + date = {2024-10-24}, + urldate = {2024-10-24}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Masters Thesis} +} + +@mastersthesis{mendoza2024thesis, + title = {AEGIS: A Special-Purpose Computer Network For Strategic Cyber Defense}, + author = {Francis Mendoza}, + url = {https://mpslab-asu.github.io/publications/papers/Mendoza2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Mendoza2024THESIS.pdf, slides}, + year = {2024}, + date = {2024-09-30}, + urldate = {2024-09-30}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Masters Thesis} +} + +@conference{Shrivastava2024Cases, + title = {Primer on Data in Quantum Machine Learning}, + author = {Aviral Shrivastava and Vinayak Sharma}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2024CASES.pdf, pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2024CASES.pptx, slides}, + year = {2024}, + date = {2024-09-29}, + urldate = {2024-09-29}, + booktitle = { 2024 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)}, + research = {Quantum Machine Learning}, + pubstate = {published}, + category = {Conference} +} + +@mastersthesis{Kumar2024thesis, + title = {DSP-MLIR: A Compiler for Digital Signal Processing in MLIR}, + author = {Abhinav Kumar and Aviral Shrivastava }, + url = {https://mpslab-asu.github.io/publications/papers/Kumar2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Kumar2024THESIS.pptx, slides}, + year = {2024}, + date = {2024-09-23}, + urldate = {2024-09-23}, + school = {Arizona State University}, + research = {AI-driven Multi-Level Compilers}, + pubstate = {published}, + category = {Masters Thesis} +} + +@conference{Peddiraju2024ITSC, + title = {IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing}, + author = {Sai Shashank Peddiraju and Kaustubh Harapanahalli and Edward Andert and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Peddiraju2024ITSC.pdf, pdf https://mpslab-asu.github.io/publications/posters/Peddiraju2024ITSC.pptx, slides}, + year = {2024}, + date = {2024-08-02}, + urldate = {2024-08-02}, + booktitle = {2024 IEEE 27th International Conference on Intelligent Transportation Systems (ITSC)}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {Conference}, + code = {https://github.com/MPSLab-ASU/IncidentNet}, + website = {https://mpslab-asu.github.io/INet/} +} + +@conference{Andert2024dac, + title = {Conclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring}, + author = {Edward Andert and Francis Mendoza and Hans Behrens and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Andert2024DAC.pdf, pdf https://mpslab-asu.github.io/publications/slides/Andert2024DAC.pptx, slides}, + year = {2024}, + date = {2024-06-26}, + urldate = {2024-06-26}, + booktitle = {Proceedings of the 61st ACM/IEEE Design Automation Conference}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {Conference} +} + +@conference{Hwisoo2024DAC, + title = {Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs}, + author = {Jinhyo Jung and Hwisoo So and Woobin Ko and Sumedh Shridhar Joshi and Yebon Kim and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Hwisoo2024DAC.pdf, pdf https://mpslab-asu.github.io/publications/slides/Hwisoo2024DAC.pptx, slides}, + year = {2024}, + date = {2024-06-23}, + urldate = {2024-06-23}, + booktitle = {Proceedings of the 61st ACM/IEEE Design Automation Conference}, + journal = {Proceedings of the 61st ACM/IEEE Design Automation Conference}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Conference} +} + +@phdthesis{Dave2024THESIS, + title = {An Agile Methodology for Designing Efficient Domain-Specific Architectures}, + author = {Shail Dave}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Dave2024THESIS.pptx, slides}, + year = {2024}, + date = {2024-06-10}, + urldate = {2024-06-10}, + research = {Machine Learning Acceleration}, + pubstate = {published}, + category = {PhD Thesis} +} + +@mastersthesis{Peddiraju2024Thesis, + title = {IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing}, + author = {Sai Shashank Peddiraju}, + url = {https://mpslab-asu.github.io/publications/papers/Peddiraju2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Peddiraju2024THESIS.pptx, slides}, + year = {2024}, + date = {2024-05-14}, + urldate = {2024-05-14}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {Masters Thesis} +} + +@patent{Dave2024Patent, + title = {Systems and methods for agile and explainable optimization of efficient hardware/software codesigns for domain-specific computing systems using bottleneck analysis}, + author = {Shail Dave and Aviral Shrivastava and Tony Nowatzki}, + url = {https://patents.google.com/patent/US20240134769A1, Google Patents}, + year = {2024}, + date = {2024-04-25}, + urldate = {2024-04-25}, + howpublished = {https://patents.google.com/patent/US20240134769A1/}, + research = {Machine Learning Acceleration}, + pubstate = {published}, + category = {Patent} +} + +@mastersthesis{Lagudu2024Thesis, + title = {LUCI: Multi-Application Orchestration Agent}, + author = {Guna Lagudu}, + url = {https://mpslab-asu.github.io/publications/papers/Lagudu2024THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Lagudu2024THESIS.pptx, slides}, + year = {2024}, + date = {2024-04-08}, + urldate = {2024-04-08}, + school = {Arizona State University}, + research = {LLM Applications}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{Dave2024ASPLOS, + title = {Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis}, + author = {Shail Dave and Tony Nowatzki and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2024ASPLOS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Dave2024ASPLOS.pptx, slides https://mpslab-asu.github.io/publications/posters/Dave2024ASPLOS.pdf, poster https://youtu.be/y-F1Cp66_oQ, teaser}, + year = {2024}, + date = {2024-04-02}, + urldate = {2024-04-02}, + booktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)}, + abstract = {Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive number of trials to obtain valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. In this paper, we propose Explainable-DSE – a framework for DSE of DNN accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE is able to identify the bottlenecks and therefore the reasons for design inefficiency, and can therefore make mitigating acquisitions in further explorations. We describe the construction of such bottleneck models for DNN accelerator domain. We also propose an API for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6× lower latency in 47× fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.}, + note = {Won Silver Medal at ACM Student Research Competition 2022-23 (Host: ACM SIGBED)}, + research = {Machine Learning Acceleration}, + pubstate = {published}, + category = {Proceedings} +} + +@patent{balasubramanian2024patent, + title = {Systems and methods for fast-mapping of coarse-grained reconfigurable arrays}, + author = {Mahesh Balasubramanian and Aviral Shrivastava}, + url = {https://patents.google.com/patent/US20240311230A1, Google Patents}, + year = {2024}, + date = {2024-03-13}, + urldate = {2024-03-13}, + howpublished = {https://patents.google.com/patent/US20240311230A1/}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Patent} +} + +@patent{balasubramanian2024patent, + title = {Systems and methods for improved mapping of computational loops on reconfigurable architectures}, + author = {Mahesh Balasubramanian and Aviral Shrivastava}, + url = {https://patents.google.com/patent/US11928468B2, Google Patents}, + year = {2024}, + date = {2024-03-12}, + urldate = {2024-03-12}, + howpublished = {https://patents.google.com/patent/US11928468B2/}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Patent} +} + +@article{shrivastava2024IoTM, + title = {Design Methodology for Robust, Distributed Time-Sensitive Applications}, + author = {Aviral Shrivastava and Mohammad Khayatian and Bob Iannucci}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2024IEEE.pdf, pdf}, + year = {2024}, + date = {2024-01-11}, + urldate = {2024-01-11}, + journal = {IEEE Internet of Things Magazine}, + research = {Real-Time Systems, Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@article{Khayatian2024TCPS, + title = {Cooperative Driving of Connected Autonomous Vehicles using Responsibility Sensitive Safety Rules: A Control Barrier Functions Approach}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and I-Ching Tseng and Chung-Wei Lin and Calin Belta and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2024TCPS.pdf, pdf}, + year = {2024}, + date = {2024-01-01}, + urldate = {2024-01-01}, + journal = {IEEE Transactions on Cyber Physical Systems}, + volume = {8}, + issue = {1}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {article} +} + +@article{Willis2024TC, + title = {Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs}, + author = {Benjamin Willis and Aviral Shrivastava and Joshua Mack and Shail Dave and Chaitali Chakrabarti and John Brunhaver}, + url = {https://mpslab-asu.github.io/publications/papers/Willis2024TC.pdf, pdf}, + year = {2024}, + date = {2024-01-01}, + urldate = {2024-01-01}, + journal = {IEEE Transactions on Computers}, + research = {}, + pubstate = {published}, + category = {article} +} + +@workingpaper{sharma2023quantum, + title = {Quantum Polar Metric Learning: Efficient Classically Learned Quantum Embeddings}, + author = {Vinayak Sharma and Aviral Shrivastava }, + url = {https://mpslab-asu.github.io/publications/papers/Sharma2023Arxiv.pdf, pdf https://mpslab-asu.github.io/QPMeL/}, + doi = { https://doi.org/10.48550/arXiv.2312.01655}, + year = {2023}, + date = {2023-12-04}, + urldate = {2023-12-04}, + abstract = {Deep metric learning has recently shown extremely promising results in the classical data domain, creating well-separated feature spaces. This idea was also adapted to quantum computers via Quantum Metric Learning(QMeL). QMeL consists of a 2 step process with a classical model to compress the data to fit into the limited number of qubits, then train a Parameterized Quantum Circuit(PQC) to create better separation in Hilbert Space. However, on Noisy Intermediate Scale Quantum (NISQ) devices. QMeL solutions result in high circuit width and depth, both of which limit scalability. We propose Quantum Polar Metric Learning (QPMeL) that uses a classical model to learn the parameters of the polar form of a qubit. We then utilize a shallow PQC with Ry and Rz gates to create the state and a trainable layer of ZZ(θ)-gates to learn entanglement. The circuit also computes fidelity via a SWAP Test for our proposed Fidelity Triplet Loss function, used to train both classical and quantum components. When compared to QMeL approaches, QPMeL achieves 3X better multi-class separation, while using only 1/2 the number of gates and depth. We also demonstrate that QPMeL outperforms classical networks with similar configurations, presenting a promising avenue for future research on fully classical models with quantum loss functions.}, + howpublished = {ArXiV}, + research = {Quantum Machine Learning}, + pubstate = {published}, + category = {Working Paper} +} + +@mastersthesis{Jagadeesha2023THESIS, + title = {TIPANGLE: A Machine Learning Approach for Accurate Spatial Pan and Tilt Angle Determination of Pan Tilt Traffic Cameras}, + author = {Shreehari Jagadeesha}, + url = {https://mpslab-asu.github.io/publications/papers/Jagadeesha2023THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Jagadeesha2023THESIS.pptx, slides}, + year = {2023}, + date = {2023-11-10}, + urldate = {2023-11-10}, + school = {Arizona State University}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {Masters Thesis} +} + +@article{so2023electronics, + title = {gemV-tool: A Comprehensive Soft Error Reliability for Machine Learning Estimation Tool for Design Space Exploration}, + author = {Hwisoo So and Yohan Ko and Jinhyo Jung and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Hwisoo2023Electronics.pdf, pdf}, + year = {2023}, + date = {2023-11-08}, + urldate = {2023-11-08}, + journal = {Electronics 2023, 12(22), 4573}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@conference{Dave2023TECHCON, + title = {Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures}, + author = {Shail Dave and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2023TECHCON.pdf, pdf https://mpslab-asu.github.io/publications/posters/Dave2023TECHCON.pptx, poster}, + year = {2023}, + date = {2023-09-11}, + urldate = {2023-09-11}, + booktitle = {Proceedings of the TECHCON}, + abstract = {Domain-specific architectures (DSAs) are increasingly designed to efficiently process a variety of workloads, such as deep learning, linear algebra, and graph analytics. Most research efforts have focused on proposing new DSAs or efficiently exploring hardware/software designs of previously proposed architecture templates. Recent architectural modeling or simulation frameworks for DSAs can analyze execution costs, e.g., for a limited architectural templates for dense DNNs such as systolic arrays or a spatial architecture with an array of processing elements and 3-level memory hierarchy. However, they are manually developed by domain-experts, containing several 1000s of lines-of-code, and extending them for characterizing new architectures is infeasible, such as DSAs for sparse DNNs. Further, the lack of automated architecture-level execution modeling limits the design space of novel architectures that can be explored/optimized, affecting overall efficiency of solutions, and it delays time-to-market with low sustainability of design process. To address this issue, this paper introduces DSAProf : a framework for automated execution modeling and bottleneck characterization by a modular, dataflow-driven approach. The framework uses a flow-graph-based methodology for modeling DSAs in a modular manner via a library of architectural components and analyzing their executions. The methodology can account for analytically modeling and simulating intricacies in the presence of a variety of architectural features such as asynchronous execution of workgroups, sparse data processing, arbitrary buffer hierarchies, and multi-chip or mixed-precision modules. Preliminary evaluations of modeling previously proposed DSAs for dense/sparse deep learning demonstrate that our approach is extensible for novel DSAs and it can accurately and automatically characterize their latency and identify execution bottlenecks, without requiring designers to manually build analysis/simulator from scratch for every DSA.}, + research = {Machine Learning Acceleration}, + pubstate = {published}, + category = {conference} +} + +@article{Szeto2023TECS, + title = {B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles}, + author = {Matthew Szeto and Edward Andert and Aviral Shrivastava and Martin Reisslein and Chung Wei Lin and Christ Richmond}, + url = {https://mpslab-asu.github.io/publications/papers/Szeto2023TECS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Szeto2023THESIS.pptx, slides}, + year = {2023}, + date = {2023-09-09}, + urldate = {2023-09-09}, + journal = {ACM Transactions on Embedded Computing Systems}, + volume = {22}, + number = {154}, + issue = {5}, + pages = {1-23}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {article} +} + +@article{Mehrabian2023MICPRO, + title = {A run-time verification method with consideration of uncertainties for cyber-physical systems}, + author = {Mohammadreza Mehrabian and Mohammad Khayatian and Aviral Shrivastava and Patricia Derler and Hugo Andrade}, + url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2023MICPRO.pdf, pdf}, + year = {2023}, + date = {2023-06-22}, + urldate = {2023-06-22}, + journal = {Microprocessors and Microsystems}, + volume = {101}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {article} +} + +@inproceedings{Hu2023MLSYS, + title = {GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing}, + author = {Yi Hu and Chaoran Zhang and Edward Andert and Harshul Singh and Aviral Shrivastava and James Laudon and Yanqi Zhou and Bob Iannucci and Carlee Joe-Wong}, + url = {https://mpslab-asu.github.io/publications/papers/Hu2023MLSYS.pdf, pdf}, + year = {2023}, + date = {2023-06-04}, + urldate = {2023-06-04}, + booktitle = {Proceedings of the Sixth Conference on Machine Learning and Systems (MLSys)}, + research = {Machine Learning Acceleration, Real-Time Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{Szeto2023THESIS, + title = {B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles}, + author = {Matthew Szeto}, + url = {https://mpslab-asu.github.io/publications/papers/Szeto2023THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Szeto2023THESIS.pptx, slides}, + year = {2023}, + date = {2023-05-08}, + urldate = {2023-05-08}, + school = {Arizona State University}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{Ranjbar2023DATE, + title = {Learning-Oriented Reliability for Machine Learning Improvement of Computing Systems From Transistor to Application Level}, + author = {Behnaz Ranjbar and Florian Klemme and Paul R. Genssler and Hussam Amrouch and Jinhyo Jung and Shail Dave and Hwisoo So and Kyongwoo Lee and Aviral Shrivastava and Ji-Yung Lin and Pieter Weckx and Subrat Mishra and Francky Catthoor and Dwaipayan Biswas and Akash Kumar}, + url = {https://mpslab-asu.github.io/publications/papers/Ranjbar2023DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Ranjbar2023DATE.pptx, slides}, + year = {2023}, + date = {2023-04-17}, + urldate = {2023-04-17}, + booktitle = {Proceedings of the 26th International Conference on Design Automation and Test in Europe (DATE)}, + research = {Efficient Embedded Computing, Machine Learning Acceleration, Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@article{ParkTIV2023, + title = {Blame-Free Motion Planning in Hybrid Traffic}, + author = {Sanggu Park and Edward Andert and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Park2023TIV.pdf, paper}, + year = {2023}, + date = {2023-04-05}, + urldate = {2023-04-05}, + journal = {IEEE Transactions on Intelligent Vehicles}, + pages = {1-10}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {article} +} + +@article{Didehban2023TDSC, + title = {Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication}, + author = {Moslem Didehban and Hwisoo So and Prudhvi Gali and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2023TDSC.pdf, paper}, + year = {2023}, + date = {2023-02-14}, + urldate = {2023-02-14}, + journal = {IEEE Transactions on Dependable and Secure Computing}, + volume = {1}, + pages = {1-16}, + abstract = {Transient faults or soft errors are considered one of the most daunting Reliability for Machine Learning challenges for microprocessors. Software solutions for soft error protection are attractive because they can provide flexible and effective error protection. For instance, nZDC [1] state-of-the-art instruction duplication error protection scheme achieves a high degree of error detection by verifying the results of memory write operations and utilizes an effective control-flow checking mechanism. However, nZDC control-flow checking mechanism is architecture-dependent and suffers from some vulnerability holes. In this work, we address these issues by substituting nZDC control-flow checking mechanism with a general (ISA-independent) scheme and propose two transformations, coarse-grained scheduling, and asymmetric control-flow signatures, for hard-to-detect control flow errors. Fault injection experiments on different hardware components of synthesizable Verilog description of an OpenRISC-based microprocessor reveal that the proposed transformation shows 85% less silent data corruptions compared to nZDC. In addition, programs protected by the proposed scheme run on average around 37% faster than nZDC-protected programs.}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@article{Shrivastava2023D&T, + title = {Report on the 2022 Embedded Systems Week (ESWEEK)}, + author = {Aviral Shrivastava and Xiaobo Sharon Hu}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2023D&T.pdf, pdf}, + year = {2023}, + date = {2023-01-23}, + urldate = {2023-01-23}, + journal = {IEEE Design & Test}, + volume = {40}, + issue = {1}, + pages = {108-111}, + abstract = {Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences [the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES); the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS); and the International Conference on Embedded Software (EMSOFT)] and a variety of symposia, hot-topic workshops, tutorials, and education classes, ESWEEK presents to the attendees a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.}, + research = {Cyber Physical and IoT Systems, Efficient Embedded Computing, Machine Learning Acceleration, Real-Time Systems, Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@mastersthesis{Ta2022THESIS, + title = {COMSAT: Modified Modulo Scheduling Techniques for Acceleration on Unknown Trip Count and Early Exit Loops}, + author = {Quoc Long Vinh Ta}, + url = {https://mpslab-asu.github.io/publications/papers/Ta2022THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Ta2022THESIS.pptx, slides }, + year = {2022}, + date = {2022-12-08}, + urldate = {2022-12-08}, + school = {Arizona State University}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{Andert2022ITSC, + title = {Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs}, + author = {Edward Andert and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Andert2022ITSC.pdf, pdf https://mpslab-asu.github.io/publications/slides/Andert2022ITSC.pptx, slides https://docs.google.com/presentation/d/1-i4m5GRfRn3lsFdo4RAhaY4qxdRgBfrX/edit?usp=sharing&ouid=101396061526471459814&rtpof=true&sd=true , slides}, + year = {2022}, + date = {2022-10-08}, + urldate = {2022-10-08}, + booktitle = {Proceedings of the IEEE 25th International Conference on Intelligent Transportation Systems (ITSC)}, + organization = {IEEE}, + research = {Intelligent Transportation Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@article{Jung2022JSA, + title = {Root cause analysis of soft-error-induced failures from hardware and software perspectives}, + author = {Jinhyo Jung and Yohan Ko and Hwisoo So and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jung2022JSA.pdf, pdf }, + year = {2022}, + date = {2022-07-08}, + urldate = {2022-07-08}, + journal = {Journal of Systems Architecture (JSA)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@article{So2022TACO, + title = {EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults}, + author = {Hwisoo So and Moslem Didehban and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/So2022TACO.pdf, paper }, + year = {2022}, + date = {2022-07-05}, + urldate = {2022-07-05}, + journal = {ACM Transactions on Architecture and Code Optimization (TACO)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@workshop{Dave2022SNN, + title = {Efficient Processing of Sparse and Compact DNN Models on Hardware Accelerators: Survey and Insights}, + author = {Shail Dave and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/posters/Dave2022SNN.pdf, poster}, + year = {2022}, + date = {2022-07-01}, + urldate = {2022-07-01}, + booktitle = {In Annual Workshop on Sparsity in Neural Networks (SparseNN)}, + research = {GPU Computing, Machine Learning Acceleration}, + pubstate = {published}, + category = {Workshop} +} + +@mastersthesis{Park2022Thesis, + title = {Blame-Free Motion Planning in Hybrid Traffic}, + author = {Sanggu Park}, + url = {https://mpslab-asu.github.io/publications/papers/Park2022THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Park2022THESIS.pptx, slides}, + year = {2022}, + date = {2022-05-11}, + urldate = {2022-05-11}, + school = {Arizona State University}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{Dave2022VTS, + title = {Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems}, + author = {Shail Dave and Alberto Marchisio and Muhammad Abdullah Hanif and Amira Guesmi and Aviral Shrivastava and Ihsen Alouani and Muhammad Shafique}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2022VTS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Dave2022VTS.pptx, slides}, + year = {2022}, + date = {2022-04-25}, + urldate = {2022-04-25}, + booktitle = {Proceedings of the 2022 IEEE 40th VLSI Test Symposium (VTS)}, + abstract = {The real-world use cases of Machine Learning (ML) have exploded over the past few years. However, the current computing infrastructure is insufficient to support all real-world applications and scenarios. Apart from high efficiency requirements, modern ML systems are expected to be highly reliable against hardware failures as well as secure against adversarial and IP stealing attacks. Recent developments have also highlighted various privacy concerns. Towards trustworthy ML systems, in this work we highlight different challenges faced by the embedded systems community towards enabling efficient, dependable and secure deployment of ML. To address these challenges, we present an agile design methodology to generate efficient, reliable and secure ML systems based on user-defined constraints and objectives.}, + research = {Efficient Embedded Computing, Machine Learning Acceleration, Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@bachelorthesis{Cunningham2022THESIS, + title = {Making a Real-Time Operating System for the Raspberry Pi 2B}, + author = {Christian Cunningham}, + url = {https://mpslab-asu.github.io/publications/papers/Cunningham2022THESIS.pdf, thesis https://mpslab-asu.github.io/publications/papers/Cunningham2022THESIS.pptx, slides https://github.com/MPSLab-ASU/Jobbed, Code}, + year = {2022}, + date = {2022-04-09}, + urldate = {2022-04-09}, + school = {Arizona State University}, + research = {Real-Time Systems}, + pubstate = {published}, + category = {Bachelors Thesis} +} + +@inproceedings{Balasubramanian2022DATE, + title = {PathSeeker: A Fast Mapping Algorithm for CGRAs}, + author = {Mahesh Balasubramanian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2022DATE.pdf, pdf https://mpslab-asu.github.io/publications/slides/Balasubramanian2022DATE.pptx, slides}, + year = {2022}, + date = {2022-03-16}, + urldate = {2022-03-16}, + booktitle = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)}, + journal = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{Huang2022DATE, + title = {Compatibility Checking for Autonomous Lane-Changing Assistance Systems}, + author = {Po-Yu Huang and Kai-Wei Liu and Zong-Lun Li and Sanggu Park and Edward Andert and Chung-Wei Lin and Aviral Shrivastava }, + url = {https://mpslab-asu.github.io/publications/papers/Huang2022DATE.pdf, pdf https://mpslab-asu.github.io/publications/slides/Huang2022DATE.pptx, slides https://mpslab-asu.github.io/publications/slides/Huang2022DATE.pdf, poster}, + year = {2022}, + date = {2022-03-16}, + urldate = {2022-03-16}, + booktitle = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@patent{Khayatian2022PATENT, + title = {Systems and methods for intersection management of connected autonomous vehicles}, + author = {Mohammad Khayatian and Aviral Shrivastava and Mohammadreza Mehrabian}, + url = {https://patents.google.com/patent/US11269330B2, Google Patents}, + year = {2022}, + date = {2022-03-08}, + urldate = {2022-03-08}, + howpublished = {https://patents.google.com/patent/US11269330B2/}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Patent} +} + +@workshop{Dave2022LATTE, + title = {Design Space Description Language for Automated and Comprehensive Exploration of Next-Gen Hardware Accelerators}, + author = {Shail Dave and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2022LATTE.pdf, pdf https://mpslab-asu.github.io/publications/slides/Dave2022LATTE.pptx, slides https://capra.cs.cornell.edu/latte22/, workshop https://youtu.be/Z5jZ2dbE0To, talk}, + year = {2022}, + date = {2022-03-01}, + urldate = {2022-03-01}, + booktitle = {Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE)}, + abstract = {Exploration of accelerators typically involves an architectural template specified in architecture description language (ADL). It can limit the design space that can be explored, reusability and automation of system stack, explainability, and exploration efficiency. We envision Design Space Description Language (DSDL) for comprehensive, reusable, explainable, and agile DSE. We describe how its flow graph abstraction enables comprehensive DSE of modular designs, with architectural components organized in various hierarchies and groups. We discuss automation of characterizing, simulating, and programming new architectures. Lastly, we describe how DSDL flow graphs facilitate bottleneck analysis, yielding explainability of costs and selected designs and super-fast exploration.}, + note = {co-located with ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).}, + research = {Coarse-Grained Reconfigurable Arrays, Machine Learning Acceleration}, + pubstate = {published}, + category = {Workshop} +} + +@article{Khayatian2022TCPS, + title = {Plan B - Design Methodology for Cyber-Physical Systems Robust to Timing Failure}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Edward Andert and Reese Grimsley and Kyle Liang and Yi Hu and Ian McCormack and Carlee Joe-Wong and Jonathan Aldrich and Bob Iannucci and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2022TCPS.pdf, pdf}, + year = {2022}, + date = {2022-01-31}, + urldate = {2022-01-31}, + journal = {ACM Transactions on Cyber Physical Systems (TCPS)}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {article} +} + +@article{So2021ELECTRONICS, + title = {Revisiting Symptom-Based Fault Tolerant Techniques against Soft Errors}, + author = {Hwisoo So and Moslem Didehban and Yohan Ko and Reiley Jeyapaul and Jongho Kim and Youngbin Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/So2021ELECTRONICS.pdf, pdf}, + year = {2021}, + date = {2021-12-04}, + urldate = {2021-12-04}, + journal = {MDPI Electronics}, + volume = {10}, + number = {23}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@phdthesis{Balasubramanian2021THESIS, + title = {Compiler Design for Accelerating Applications on Coarse-Grained Reconfigurable Architectures}, + author = {Mahesh Balasubramanian }, + url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2021THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Balasubramanian2021THESIS.pptx, slides}, + year = {2021}, + date = {2021-10-25}, + urldate = {2021-12-13}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {PhD Thesis} +} + +@inproceedings{Ko2021ICCD, + title = {Comprehensive Failure Analysis against Soft Errors from Hardware and Software Perspectives}, + author = {Yohan Ko and Jin Hyo Jung and Hwisoo So and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Ko2021ICCD.pdf, paper https://mpslab-asu.github.io/publications/slides/Ko2021ICCD.pptx, slides}, + year = {2021}, + date = {2021-10-24}, + urldate = {2021-10-24}, + booktitle = {Proceedings of the 2021 IEEE International Conference on Computer Design (ICCD)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@article{Dave2021PIEEE, + title = {Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights}, + author = {Shail Dave and Riyadh Baghdadi and Tony Nowatzki and Sasikanth Avancha and Aviral Shrivastava and Baoxin Li}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2021PIEEE.pdf, paper}, + year = {2021}, + date = {2021-10-01}, + urldate = {2021-10-01}, + journal = {Proceedings of the IEEE (PIEEE)}, + note = {arXiv: 2007.00864}, + research = {Coarse-Grained Reconfigurable Arrays, Machine Learning Acceleration, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {article} +} + +@phdthesis{Mehrabian2021THESIS, + title = {A Methodology and Formalism to Monitor Timing Specifications Of Cyber-Physical Systems}, + author = {Mohammadreza Mehrabian}, + url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2021THESIS.pdf, pdf https://mpslab-asu.github.io/publications/slides/Mehrabian2021THESIS.pptx, slides}, + year = {2021}, + date = {2021-07-06}, + urldate = {2021-07-06}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {PhD Thesis} +} + +@phdthesis{Khayatian2021PhDThesis, + title = {Safe and Robust Cooperative Algorithms for Connected Autonomous Vehicles}, + author = {Mohammad Khayatian}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2021Thesis.pdf, pdf https://mpslab-asu.github.io/publications/slides/Khayatian2021Thesis.pptx, slides}, + year = {2021}, + date = {2021-06-23}, + urldate = {2021-06-23}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {PhD Thesis} +} + +@inproceedings{KhayatianICCPS2021, + title = {Cooperative Driving of Connected Autonomous Vehicles Using Responsibility-Sensitive Safety (RSS) Rules}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Harshith Allamsetti and Kai Wei and Po Yu and Chung-Wei Lin and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2021ICCPS.pdf, paper https://mpslab-asu.github.io/publications/slides/Khayatian2021ICCPS.pptx, slide}, + year = {2021}, + date = {2021-04-10}, + urldate = {2021-04-10}, + booktitle = {Proceedings of the 12th ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS)}, + journal = {ICCPS}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{SoDATE2021, + title = {CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults}, + author = {Hwisoo So and Moslem Didehban and Jinhyo Jung and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/So2021DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/So2021DATE.pptx, slides}, + year = {2021}, + date = {2021-02-01}, + urldate = {2021-02-01}, + booktitle = {Proceedings of the 24th International Conference on Design Automation and Test in Europe (DATE)}, + journal = {Proceedings of the 24th International Conference on Design Automation and Test in Europe (DATE)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@article{SinghTACO2020, + title = {SPX64: A Scratchpad Memory for General-Purpose Microprocessors}, + author = {Abhishek Singh and Shail Dave and PanteA Zardoshti and Robert Brotzman and Chao Zhang and Xiaochen Guo and Aviral Shrivastava and Gang Tan and Michael Spear}, + url = {https://mpslab-asu.github.io/publications/papers/Singh2020TACO.pdf, paper}, + year = {2021}, + date = {2021-01-18}, + journal = {ACM Transactions on Architecture and Code Optimization (TACO)}, + research = {Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {article} +} + +@inproceedings{KhayatianITSC2020, + title = {R^{2}IM -- Robust and Resilient Intersection Management of Connected Autonomous Vehicles}, + author = {Mohammad Khayatian and Rachel Dedinsky and Sarthake Choudhary and Mohammadreza Mehrabian and Aviral Shrivastava}, + url = {https://MPSLab-ASU.github.io/publications/papers/Khayatian2020ITSC.pdf, paper https://MPSLab-ASU.github.io/publications/slides/Khayatian2020ITSC.pptx, slides}, + year = {2020}, + date = {2020-09-20}, + booktitle = {2020 IEEE International Conference on Intelligent Transportation System Conference (ITSC)}, + organization = {IEEE}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@article{Balasubramanian2020TCAD, + title = {CRIMSON: Compute-intensive loop acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs}, + author = {Mahesh Balasubramanian and Aviral Shrivastava }, + url = {https://MPSLab-ASU.github.io/publications/papers/Balasubramanian2020TCAD.pdf, paper}, + year = {2020}, + date = {2020-09-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {article} +} + +@article{KhayatianTCPS2020, + title = {A Survey on Intersection Management of Connected Autonomous Vehicles}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Edward Andert and Rachel Dedinsky and Sarthake Choudhary and Yingyan Lou and Aviral Shrivastava}, + url = {https://MPSLab-ASU.github.io/publications/papers/Khayatian2020TCPS.pdf, paper}, + year = {2020}, + date = {2020-07-20}, + journal = {ACM Transactions on Cyber-Physical Systems}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {article} +} + +@mastersthesis{Allamsetti2020thesis, + title = {Cooperative Driving of Connected Autonomous Vehicles Using Responsibility Sensitive Safety Rules}, + author = {Harshith Allamsetti}, + url = {https://MPSLab-ASU.github.io/publications/papers/Allamsetti2020THESIS.pdf, paper https://MPSLab-ASU.github.io/publications/slides/Allamsetti2020THESIS.pptx, slides}, + year = {2020}, + date = {2020-06-25}, + urldate = {2020-06-25}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{BalasubramanianI2020IPDPS, + title = {Scaling of Union of Intersections for Inference of Granger Causal Networks from Observational Data}, + author = {Mahesh Balasubramanian and Trevor Ruiz and Brandon Cook and Mr Prabhat and Sharmodeep Bhattacharyya and Aviral Shrivastava and Kristofer Bouchard}, + url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2020IPDPS.pdf, paper https://mpslab-asu.github.io/publications/slides/Balasubramanian2020IPDPS.pptx, slides}, + year = {2020}, + date = {2020-05-01}, + booktitle = {Proceeding of the 34th IEEE International Parallel & Distributed Processing Symposium (IPDPS)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{DaveICASSP2020, + title = {dMazeRunner: Optimizing Convolutions on Dataflow Accelerators}, + author = {Shail Dave and Aviral Shrivastava and Youngbin Kim and Sasikanth Avancha and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2020ICASSP.pdf, paper https://mpslab-asu.github.io/publications/slides/Dave2020ICASSP.pptx, slides https://github.com/MPSLab-ASU/dMazeRunner, code https://www.youtube.com/watch?v=21F79Taelts, video}, + year = {2020}, + date = {2020-04-09}, + urldate = {2020-04-09}, + booktitle = {ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)}, + note = {Invited}, + research = {Machine Learning Acceleration}, + pubstate = {published}, + category = {Proceedings} +} + +@workshop{DedinskyASD2019, + title = {A Dependable Detection Mechanism for Intersection Management of Connected Autonomous Vehicles}, + author = {Rachel Dedinsky and Mohammad Khayatian and Mohammadreza Mehrabian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dedinsky2019ASD.pdf, pdf http://asd.userweb.mwn.de/Archives/2019/index.html, workshop}, + year = {2019}, + date = {2019-03-28}, + urldate = {2019-03-28}, + booktitle = {Workshop on Autonomous Systems Design (ASD 2019)}, + note = {co-located with 22nd International Conference on Design Automation and Test in Europe (DATE).}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Workshop} +} + +@mastersthesis{DedinskyMSThesis2019, + title = {R2IM: Reliable and Robust Intersection Manager Robust to Rogue Vehicles}, + author = {Rachel Dedinsky}, + url = {https://mpslab-asu.github.io/publications/papers/Dedinsky2019THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Dedinsky2019THESIS.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + school = {Arizona State University}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{LinVLSID2019, + title = {Efficient Heap Data Management on Software Managed Manycore Architectures}, + author = {Jinn-Pean Lin and Jing Lu and Jian Cai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lin2019VLSID.pdf, paper https://mpslab-asu.github.io/publications/slides/Lin2019VLSID.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KimVLSID2019, + title = {WCET-Aware Stack Frame Management of Embedded Systems using Scratchpad Memories}, + author = {Yooseong Kim and Mohammad Khayatian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2019VLSID.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2019VLSID.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)}, + research = {Cyber Physical and IoT Systems, Power, Temperature and Variation Aware Computing, Real-Time Systems, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{SoDATE2019, + title = {A software-level Redundant MultiThreading for Soft/Hard Error Detection and Recovery}, + author = {Hwisoo So and Moslem Didehban and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/So2019DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/So2019DATE.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of the 22nd International Conference on Design Automation and Test in Europe (DATE)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@article{DaveTECS2019, + title = {DMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators}, + author = {Shail Dave and Youngbin Kim and Sasikanth Avancha and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2019TECS.pdf, paper https://mpslab-asu.github.io/publications/slides/Dave2019TECS.pptx, slides https://mpslab-asu.github.io/publications/posters/Dave2019TECS.pdf, poster https://github.com/MPSLab-ASU/dMazeRunner, code}, + year = {2019}, + date = {2019-01-01}, + urldate = {2019-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + volume = {18}, + number = {5s}, + note = {Special Issue on ESWEEK 2019 - Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)}, + research = {Machine Learning Acceleration}, + pubstate = {published}, + category = {article} +} + +@article{RisheekesanTECS2019, + title = {Control Flow Checking or Not? (for Soft Errors)}, + author = {Abhishek Risheekesan and Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Risheekesan2019TECS.pdf, paper}, + year = {2019}, + date = {2019-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@phdthesis{Lu2019PhDThesis, + title = {Application-aware Performance Optimization for Software Managed Manycore Architectures}, + author = {Jing Lu}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2019THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Lu2019THESIS.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + school = {Arizona State University}, + research = {Power, Temperature and Variation Aware Computing, Software Branch Hinting, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {PhD Thesis} +} + +@inproceedings{ShrivastavaDAC2019, + title = {Software Approaches for In-time Resilience}, + author = {Aviral Shrivastava and Moslem Didehban}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2019DAC.pdf, paper}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of the 56th Annual Design Automation Conference (DAC)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@article{KhayatianTCPS2019, + title = {Crossroads+: A Time-Aware Approach for Intersection Management of Connected Autonomous Vehicles}, + author = {Mohammad Khayatian and Yingyan Lou and Mohammadreza Mehrabian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2019TCPS.pdf, paper}, + year = {2019}, + date = {2019-01-01}, + journal = {ACM Transactions on Cyber-Physical Systems (TCPS)}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {article} +} + +@inproceedings{Hekmatnejad2019MEMOCODE, + title = {Encoding and Monitoring Responsibility Sensitive Safety Rules for Automated Vehicles in Signal Temporal Logic}, + author = {Mohammad Hekmatnejad and Shakiba Yaghoubi and Adel Dokhanchi and Heni Ben Amor and Aviral Shrivastava and Lina Karam and Georgios Fainekos}, + url = {https://mpslab-asu.github.io/publications/papers/Hekmatnejad2019MEMOCODE.pdf, paper https://mpslab-asu.github.io/publications/slides/Hekmatnejad2019MEMOCODE.pdf, slides}, + year = {2019}, + date = {2019-01-01}, + urldate = {2019-01-01}, + booktitle = {Proceedings of the 2019 17th ACM/IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KimICCD2019, + title = {Static Function Prefetching for Efficient Code Management on Scratchpad Memory}, + author = {Youngbin Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2019ICCD.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2019ICCD.pptx, slides}, + year = {2019}, + date = {2019-01-01}, + booktitle = {Proceedings of the 2019 IEEE International Conference on Computer Design (ICCD)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@workshop{DaveDATEDEMO2018, + title = {CCF: A CGRA Compilation Framework}, + author = {Shail Dave and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2018DATEDEMO.pdf, pdf https://youtu.be/iGV1lHsjy4w, talk https://github.com/MPSLab-ASU/CCF, code}, + year = {2018}, + date = {2018-03-21}, + booktitle = {University Booth at the 21st International Conference on Design Automation and Test in Europe (DATE) }, + research = {}, + pubstate = {published}, + category = {Workshop} +} + +@inproceedings{BalasubramanianDATE2018, + title = {LASER: A Hardware/Software Approach to Accelerate Complicated Loops on CGRAs}, + author = {Mahesh Balasubramanian and Shail Dave and Aviral Shrivastava and Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2018DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Balasubramanian2018DATE.pptx, slides}, + year = {2018}, + date = {2018-01-01}, + booktitle = {Proceedings of the 21st International Conference on Design Automation and Test in Europe (DATE)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@article{DidehbanTR2018, + title = {A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments}, + author = {Moslem Didehban and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2018TR.pdf, paper}, + year = {2018}, + date = {2018-01-01}, + journal = {IEEE Transactions on Reliability for Machine Learning}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@inproceedings{KhayatianRTSS2018, + title = {RIM: Robust Intersection Management for Connected Autonomous Vehicles}, + author = {Mohammad Khayatian and Mohammadreza Mehrabian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Khayatian2018RTSS.pdf, paper https://mpslab-asu.github.io/publications/slides/Khayatian2018RTSS.pptx, slides}, + year = {2018}, + date = {2018-01-01}, + booktitle = {Proceedings of the 39th IEEE Real-Time Systems Symposium (RTSS)}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{MehrabianDAC2018, + title = {TMA: An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems}, + author = {Mohammadreza Mehrabian and Mohammad Khayatian and Ahmed Moussa and Aviral Shrivastava and Ya-Shian Li and Patricia Derler and Edward Griffor and Hugo A Andrade and Marc Weiss and John Eidson}, + url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2018DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Mehrabian2018DAC.pptx, slides}, + year = {2018}, + date = {2018-01-01}, + booktitle = {Proceedings of the 55th Annual Design Automation Conference (DAC)}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@phdthesis{Didehban2018PhDThesis, + title = {Software Techniques For Dependable Execution}, + author = {Moslem Didehban}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2018THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Didehban2018THESIS.pptx, slides}, + year = {2018}, + date = {2018-01-01}, + school = {Arizona State University}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {PhD Thesis} +} + +@inproceedings{DaveDAC2018, + title = {RAMP: Resource-Aware Mapping for CGRAs}, + author = {Shail Dave and Mahesh Balasubramanian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Dave2018DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Dave2018DAC.pptx, slides https://mpslab-asu.github.io/publications/posters/Dave2018DAC.pdf, poster }, + year = {2018}, + date = {2018-01-01}, + urldate = {2018-01-01}, + booktitle = {Proceedings of the 55th Annual Design Automation Conference (DAC)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaDAC2017, + title = {A Testbed to Verify the Timing Behavior of Cyber-Physical Systems}, + author = {Aviral Shrivastava and Mohammadreza Mehrabian and Mohammad Khayatian and Patricia Derler and Hugo A Andrade and Kevin Stanton and Ya-Shian Li-Baboud and Edward Griffor and Marc Weiss and John Eidson}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2017DAC.pdf, paper }, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of The 54th Annual Design Automation Conference (DAC)}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{DidehbanICCAD2017, + title = {NEMESIS: A Software Approach for Computing in Presence of Soft Errors}, + author = {Moslem Didehban and Aviral Shrivastava and Dheeraj Lokam}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2017ICCAD.pdf, paper https://mpslab-asu.github.io/publications/slides/Didehban2017ICCAD.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{CaiDATE2017, + title = {Reducing Code Management Overhead in Software-Managed Multicores}, + author = {Jian Cai and Yooseong Kim and Youngbin Kim and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Cai2017DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Cai2017DATE.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of the 2017 International Conference on Design Automation and Test in Europe (DATE)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{AndertMSTHESIS2017, + title = {Crossroads - A Time-Sensitive Autonomous Intersection Management Technique}, + author = {Edward Andert}, + url = {https://www.youtube.com/watch?v=pX5TjijLP9o&feature=youtu.be, video https://mpslab-asu.github.io/publications/papers/Andert2017THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Andert2017THESIS.pptx, slides }, + year = {2017}, + date = {2017-01-01}, + school = {Arizona State University}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{DidehbanDAC2017, + title = {An Integrated Safe and Fast Recovery Scheme from Soft Errors}, + author = {Moslem Didehban and Dheeraj Lokam and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2017DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Didehban2017DAC.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of The 54th Annual Design Automation Conference (DAC)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{AndertDAC2017, + title = {Crossroads - A Time-Sensitive Autonomous Intersection Management Technique}, + author = {Edward Andert and Mohammad Khayatian and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Andert2017DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Andert2017DAC.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + booktitle = {Proceedings of The 54th Annual Design Automation Conference (DAC)}, + note = {Best Paper Award Candidate}, + research = {Intelligent Transportation Systems, Intelligent Transportation Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@article{KoTECS2017, + title = {Protecting Caches from Soft Errors: A Microarchitect's Perspective}, + author = {Yohan Ko and Reiley Jeyapaul and Youngbin Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Ko2017TECS.pdf, paper }, + year = {2017}, + date = {2017-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + volume = {16}, + number = {4}, + pages = {93:1-93:28}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@phdthesis{KimPHDTHESIS2017, + title = {WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems}, + author = {Yooseong Kim}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2017THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2017THESIS.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + school = {Arizona State University}, + note = {Outstanding Computer Science Graduating PhD Student of the Year Award}, + research = {Cyber Physical and IoT Systems, Power, Temperature and Variation Aware Computing, Real-Time Systems, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {PhD Thesis} +} + +@article{KimTECS2017, + title = {WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory}, + author = {Yooseong Kim and David Broman and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2017TECS.pdf, paper}, + year = {2017}, + date = {2017-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + volume = {16}, + number = {4}, + pages = {112:1-112:26}, + research = {Cyber Physical and IoT Systems, Power, Temperature and Variation Aware Computing, Real-Time Systems, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {article} +} + +@article{MehrabianTECS2017, + title = {Timestamp Temporal Logic (TTL) for Time Testing of Cyber-Physical Systems}, + author = {Mohammadreza Mehrabian and Mohammad Khayatian and Aviral Shrivastava and John Eidson and Patricia Derler and Hugo A Andrade and Ya-Shian Li-Baboud and Edward Griffor and Marc Weiss and Kevin Stanton}, + url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2017TECS.pdf, paper https://mpslab-asu.github.io/publications/slides/Mehrabian2017TECS.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + volume = {16}, + number = {169}, + series = {5s}, + note = {Special Issue on ESWEEK 2017 - Proceedings of the International Conference on Embedded Software (EMSOFT)}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {article} +} + +@mastersthesis{LinMSThesis2017, + title = {Optimizing Heap Data Management on Software Managed Many-core Architectures}, + author = {Jinn-Pean Lin}, + url = {https://mpslab-asu.github.io/publications/papers/Lin2017THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Lin2017THESIS.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + school = {Arizona State University}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Masters Thesis} +} + +@phdthesis{CaiPHDTHESIS2017, + title = {Scratchpad Management in Software Managed Manycore Architectures}, + author = {Jian Cai}, + url = {https://mpslab-asu.github.io/publications/papers/Cai2017THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Cai2017THESIS.pptx, slides}, + year = {2017}, + date = {2017-01-01}, + school = {Arizona State University}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {PhD Thesis} +} + +@inproceedings{CaiASAP2016, + title = {Efficient Pointer Management of Stack Data for Software Managed Multicores}, + author = {Jian Cai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Cai2016ASAP.pdf, paper https://mpslab-asu.github.io/publications/slides/Cai2016ASAP.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@article{ShrivastavaIET2016, + title = {Automatic Management of Software Programmable Memories in Manycore Architectures}, + author = {Aviral Shrivastava and Nikil Dutt and Jian Cai and Majid Shoushtari and Bryan Donyanavard and Hossein Tajik}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2016IET.pdf, paper }, + year = {2016}, + date = {2016-01-01}, + journal = {IET Computers & Digital Techniques}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {article} +} + +@inproceedings{DidehbanDAC2016, + title = {NZDC: A Compiler technique for near Zero Silent data Corruption}, + author = {Moslem Didehban and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Didehban2016DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Didehban2016DAC.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of The 53rd Annual Design Automation Conference (DAC)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{LokamMSTHESIS2016, + title = {InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes}, + author = {Dheeraj Lokam}, + url = {https://mpslab-asu.github.io/publications/papers/Lokam2016THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Lokam2016THESIS.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + school = {Arizona State University}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Masters Thesis} +} + +@article{JeyapaulVLSI2016, + title = {Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability for Machine Learning}, + author = {Reiley Jeyapaul and Roberto Flores and Alfonso Avila and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2016TVLSI.pdf, paper}, + year = {2016}, + date = {2016-01-01}, + journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@inproceedings{ShrivastavaCODESISSS2016, + title = {Time in Cyber-Physical Systems}, + author = {Aviral Shrivastava and Patricia Derler and Ya-Shian Li and Kevin Stanton and Mohammad Khayatian and Hugo A Andrade and Marc Weiss and John Eidson and Sundeep Chandhoke}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2016CODES.pdf, paper }, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of the international symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS)}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KimICCAD2016, + title = {Splitting Functions in Code Management on Scratchpad Memories}, + author = {Youngbin Kim and Jian Cai and Yooseong Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2016ICCAD.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2016ICCAD.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{TanikellaASAP2016, + title = {GemV: A Validated Toolset for the Early Exploration of System Reliability for Machine Learning}, + author = {Srinivas Karthik Tanikella and Yohan Ko and Reiley Jeyapaul and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Tanikella2016ASAP.pdf, paper https://mpslab-asu.github.io/publications/slides/Tanikella2016ASAP.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{TanikellaMSTHESIS2016, + title = {GemV: A Validated Micro-architecture Vulnerability Estimation Tool}, + author = {Srinivas Karthik Tanikella}, + url = {https://mpslab-asu.github.io/publications/papers/Tanikella2016THESIS.pdf, paper }, + year = {2016}, + date = {2016-01-01}, + school = {Arizona State University}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{CaiVLSID2016, + title = {Software Coherence Management on Non-Coherent Cache Multi-cores}, + author = {Jian Cai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Cai2016VLSID.pdf, paper https://mpslab-asu.github.io/publications/slides/Cai2016VLSID.pptx, slides}, + year = {2016}, + date = {2016-01-01}, + booktitle = {Proceedings of 29th International Conference on VLSI Design (VLSID)}, + note = {(Best Student Paper Award)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@patent{BaiPATENT2015, + title = {Stack data management for software managed multi-core processors}, + author = {Ke Bai and Aviral Shrivastava and Jing Lu}, + year = {2015}, + date = {2015-01-01}, + howpublished = {http://www.google.com/patents/US9015689}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Patent} +} + +@inproceedings{AndradeRECONFIG2015, + title = {Towards a Reconfigurable Distributed Testbed to Enable Advanced Research and Development of Timing and Synchronization in Cyber-Physical Systems}, + author = {Hugo A Andrade and Patricia Derler and John Eidson and Ya-Shian Li-Baboud and Aviral Shrivastava and Kevin Stanton and Marc Weiss}, + url = {https://mpslab-asu.github.io/publications/papers/Andrade2015RECONFIG.pdf, paper }, + year = {2015}, + date = {2015-01-01}, + booktitle = {International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, + research = {Cyber Physical and IoT Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{RuCASES2015, + title = {Optimization of Multi-Channel BCH Error Decoding for Common Cases}, + author = {Russell Dill and Aviral Shrivastava and Hyunok Oh}, + url = {https://mpslab-asu.github.io/publications/papers/Dill2015CASES.pdf, paper https://mpslab-asu.github.io/publications/slides/Dill2015CASES.pptx, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {In Proceedings of the 2014 international conference on Compilers, architecture, and synthesis for embedded systems (CASES)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{HokeunRTAS2015, + title = {A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems}, + author = {Hokeun Kim and David Broman and Edward A Lee and Michael Zimmer and Aviral Shrivastava and Junkwang Oh}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2015RTAS.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2015RTAS.pdf, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {Real-Time and Embedded Technology and Applications Symposium (RTAS)}, + research = {Cyber Physical and IoT Systems, Real-Time Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{DillMASTERTHESIS2015, + title = {Optimization of Multi-Channel BCH Error Decoding for Common Cases}, + author = {Russell Dill}, + url = {https://mpslab-asu.github.io/publications/papers/Dill2015THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Dill2015THESIS.pptx, slides}, + year = {2015}, + date = {2015-01-01}, + school = {Arizona State University}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Masters Thesis} +} + +@article{PagerTECS2015, + title = {A Software Scheme for Multithreading on CGRAs}, + author = {Jared Pager and Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Pager2015TECS.pdf, paper}, + year = {2015}, + date = {2015-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {article} +} + +@inproceedings{RadhikaDATE2015, + title = {Path Selection Based Acceleration of Conditionals in CGRAs}, + author = {Shri Hari Rajendran Radhika and Aviral Shrivastava and Mahdi Hamzeh}, + url = {https://mpslab-asu.github.io/publications/papers/Radhika2015DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Radhika2015DATE.slides, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {Proceedings of the 2015 International Conference on Design Automation and Test in Europe (DATE)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{RawatDATE2015, + title = {Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures}, + author = {Tushar Rawat and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Rawat2015DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Rawat2015DATE.pptx, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {Proceedings of the 2015 International Conference on Design Automation and Test in Europe (DATE)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@article{LuTECS2015, + title = {Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores}, + author = {Jing Lu and Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2015TECS.pdf, paper}, + year = {2015}, + date = {2015-01-01}, + journal = {ACM Transactions on Embedded Computing Systems (TECS)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {article} +} + +@inproceedings{YohanDAC2015, + title = {Guidelines to Design Parity Protected Write-back L1 Data Cache}, + author = {Yohan Ko and Reiley Jeyapaul and Youngbin Kim and Kyoungwoo Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Ko2015DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Ko2015DAC.pptx, slides}, + year = {2015}, + date = {2015-01-01}, + booktitle = {Proceedings of The 52nd Annual Design Automation Conference (DAC)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaCASA2014, + title = {Control Flow Checking or Not?(for Soft Errors)}, + author = {Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2014CASA.pdf, paper}, + year = {2014}, + date = {2014-05-01}, + booktitle = {2014 Conference on Computer Animation and Social Agents}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@phdthesis{BaiPHDTHESIS2014, + title = {Compiler and Runtime for Memory Management on Software Managed Manycore Processors}, + author = {Ke Bai}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2014THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Bai2014THESIS.pptx, slides}, + year = {2014}, + date = {2014-02-01}, + urldate = {2014-02-01}, + school = {Arizona State University}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {PhD Thesis} +} + +@article{JeyapaulTPDS2013, + title = {UnSync-CMP: Multicore CMP Architecture for Energy Efficient Soft Error Reliability for Machine Learning}, + author = {Reiley Jeyapaul and Abhishek Risheekesan and Aviral Shrivastava and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2014TPDS.pdf, paper}, + year = {2014}, + date = {2014-01-01}, + journal = {Transactions on Parallel and Distributed Systems}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@inproceedings{KimRTAS2014, + title = {WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores}, + author = {Yooseong Kim and David Broman and Jian Cai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2014RTAS.pdf, paper https://mpslab-asu.github.io/publications/slides/Kim2014RTAS.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + booktitle = {Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)}, + research = {Cyber Physical and IoT Systems, Power, Temperature and Variation Aware Computing, Real-Time Systems, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{HoltonCASES2014, + title = {Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM) Architectures}, + author = {Bryce Holton and Ke Bai and Aviral Shrivastava and Harini Ramaprasad}, + url = {https://mpslab-asu.github.io/publications/papers/Holton2014CASES.pdf, paper https://mpslab-asu.github.io/publications/slides/Holton2014CASES.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + booktitle = {Proceedings of the 2014 international conference on Compilers, architecture, and synthesis for embedded systems (CASES)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaDAC2014, + title = {Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors}, + author = {Aviral Shrivastava and Abhishek Risheekesan and Reiley Jeyapaul and Carole-Jean Wu}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2014DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Shrivastava2014DAC.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + booktitle = {Proceedings of the The 51st Annual Design Automation Conference (DAC)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{HamzehDAC2014, + title = {Branch-Aware Loop Mapping on CGRAs}, + author = {Mahdi Hamzeh and Aviral Shrivastava and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Hamzeh2014DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Hamzeh2014DAC.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + booktitle = {Proceedings of the The 51st Annual Design Automation Conference on (DAC), 2014}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{RawatMASTERTHESIS2014, + title = {Enabling Multithreaded Applications on Hybrid Shared Memory Many-core Architectures}, + author = {Tushar Rawat}, + url = {https://mpslab-asu.github.io/publications/papers/Rawat2014THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Rawat2014THESIS.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + school = {Arizona State University}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Masters Thesis} +} + +@mastersthesis{RadhikaMASTERTHESIS2014, + title = {Path Selection Based Branching for Coarse Grained Reconfigurable Arrays}, + author = {Shri Hari Rajendran Radhika}, + url = {https://mpslab-asu.github.io/publications/papers/Radhika2014THESIS.pdf, paper}, + year = {2014}, + date = {2014-01-01}, + school = {Arizona State University}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Masters Thesis} +} + +@mastersthesis{SalujaMASTERTHESIS2014, + title = {Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective}, + author = {Dipal Saluja}, + url = {https://mpslab-asu.github.io/publications/papers/Saluja2014THESIS.pdf, paper https://mpslab-asu.github.io/publications/slides/Saluja2014THESIS.pptx, slides}, + year = {2014}, + date = {2014-01-01}, + school = {Arizona State University}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Masters Thesis} +} + +@mastersthesis{HoltonMASTERTHESIS2014, + title = {Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM)}, + author = {Bryce Holton}, + url = {https://mpslab-asu.github.io/publications/papers/Holton2014THESIS.pdf, paper}, + year = {2014}, + date = {2014-01-01}, + school = {Arizona State University}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Masters Thesis} +} + +@article{LeeTECS2013, + title = {Software-Based Register File Vulnerability Reduction for Embedded Processors}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2013TECS.pdf, paper}, + year = {2013}, + date = {2013-11-01}, + journal = {ACM Transactions on Embedded Computing Systems}, + volume = {13}, + number = {1}, + pages = {38:1-38:20}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@article{JeyapaulTODAES2013, + title = {Enabling Energy Efficient Reliability for Machine Learning in Embedded Systems Through Smart Cache Cleaning}, + author = {Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2013TODAES.pdf, paper}, + year = {2013}, + date = {2013-10-01}, + journal = {Transactions on Design Automation of Electronic Systems}, + volume = {18}, + number = {4}, + pages = {53:1-53:25}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@article{KimTECS2013, + title = {Memory Performance Estimation of CUDA Programs}, + author = {Yooseong Kim and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2013TECS.pdf, paper}, + year = {2013}, + date = {2013-09-01}, + journal = {ACM Transactions on Embedded Computing Systems}, + volume = {13}, + number = {21}, + pages = {21:1-21:22}, + research = {GPU Computing}, + pubstate = {published}, + category = {article} +} + +@article{BaiTECS2013, + title = {A Software-Only Scheme for Managing Heap Data on Limited Local Memory (LLM) Multicore Processors}, + author = {Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2013TECS.pdf, paper}, + year = {2013}, + date = {2013-08-01}, + journal = {ACM TECS: ACM Transactions on Embedded Computing Systems}, + volume = {13}, + number = {1}, + pages = {5:1-5:18}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {article} +} + +@mastersthesis{RhisheekesanMASTERTHESIS2013, + title = {Quantitative Evaluation of Control-flow based Soft Error Protection Mechanisms}, + author = {Abhishek Risheekesan}, + url = {https://mpslab-asu.github.io/publications/papers/Risheekesan2013THESIS.pdf, paper}, + year = {2013}, + date = {2013-03-01}, + school = {Arizona State University}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{BaiDATE2013, + title = {Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures}, + author = {Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2013DATE.pdf, paper https://mpslab-asu.github.io/publications/slides/Bai2013DATE.pptx, slides}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the 2013 International Conference on Design Automation and Test in Europe (DATE)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{LuDAC2013, + title = {SSDM: Smart Stack Data Management for Software Managed Multicores (SMMs)}, + author = {Jing Lu and Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2013DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Lu2013DAC.pptx, slides}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the 50th Design Automation Conference (DAC)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{BaiCODESISSS2013, + title = {CMSM: An Efficient and Effective Code Management for Software Managed Multicores}, + author = {Ke Bai and Jing Lu and Aviral Shrivastava and Bryce Holton}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2013CODES.pdf, paper https://mpslab-asu.github.io/publications/slides/Bai2013CODES.pptx, slides}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the international symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{MahdiDAC2013, + title = {REGIMap: Register-aware Application Mapping on Coarse-grained Reconfigurable Architectures (CGRAs)}, + author = {Mahdi Hamzeh and Aviral Shrivastava and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Hamzeh2013DAC.pdf, paper https://mpslab-asu.github.io/publications/slides/Hamzeh2013DAC.pptx, slides}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the 50th Annual Design Automation Conference (DAC)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{BromanESLSYN2013, + title = {Precision Timed Infrastructure: Design Challenges}, + author = {David Broman and Michael Zimmer and Yooseong Kim and Hokeun Kim and Jian Cai and Aviral Shrivastava and Stephen A Edwards and Edward A Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Broman2013ESLSYN.pdf, paper}, + year = {2013}, + date = {2013-01-01}, + booktitle = {Proceedings of the Electronic System Level Synthesis Conference (ESLsyn 2013)}, + research = {Cyber Physical and IoT Systems, Real-Time Systems}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{LeeVLSID2013, + title = {Power-Efficient Protection from Soft Errors}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2013VLSID.pdf, paper}, + year = {2013}, + date = {2013-01-01}, + booktitle = {2013 26th International Conference on VLSI Design (VLSID 2013)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@article{HongTVLSI2012, + title = {Return Data Interleaving for Multi-channel Embedded CMP Systems}, + author = {Fei Hong and Aviral Shrivastava and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Hong2012TVLSI.pdf}, + year = {2012}, + date = {2012-07-01}, + journal = {IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits}, + volume = {20}, + number = {7}, + pages = {1351-1354}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {article} +} + +@phdthesis{JeyapaulPHDTHESIS2012, + title = {Smart Compilers for Reliable and Power-efficient Embedded Computing}, + author = {Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2012THESIS.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2012THESIS.pptx}, + year = {2012}, + date = {2012-05-01}, + school = {Arizona State University}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {PhD Thesis} +} + +@article{LeeTECS2012, + title = {PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2012TECS.pdf}, + year = {2012}, + date = {2012-01-01}, + journal = {ACM TECS: ACM Transactions on Embedded Computing Systems}, + volume = {11}, + number = {2}, + pages = {26:1-26:27}, + research = {Power, Temperature and Variation Aware Computing, Processor Idle Cycle Aggregation}, + pubstate = {published}, + category = {article} +} + +@inproceedings{MahdiDAC2012, + title = {EPIMap: Using Epimorphism to Map Applications on CGRAs}, + author = {Mahdi Hamzeh and Aviral Shrivastava and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Hamzeh2012DAC.pdf https://mpslab-asu.github.io/publications/slides/Hamzeh2012DAC.pptx}, + year = {2012}, + date = {2012-01-01}, + booktitle = {Proceedings of the 49th Design Automation Conference (DAC)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{DiMASTERTHESIS2012, + title = {STL on Limited Local Memory (LLM) Multi-core Processors}, + author = {Di Lu}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2012THESIS.pdf https://mpslab-asu.github.io/publications/slides/Lu2012THESIS.pptx}, + year = {2012}, + date = {2012-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{LeeCODESISSS2012, + title = {Soft Errors: The Hardware-Software Interface}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Reiley Jeyapaul}, + year = {2012}, + date = {2012-01-01}, + booktitle = {Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis}, + pages = {577--578}, + booktitle = {ACM}, + address = {New York, NY, USA}, + series = {CODES+ISSS '12}, + crossref = {978-1-4503-1426-8}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{PiotrVLSI2012, + title = {Design of an RNS Reverse Converter for a New Five-Moduli Special Set}, + author = {Piotr Patronik and Krzysztof Berezowski and Janusz Biernat and Stanislaw J Piestrak and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Patronik2014GLSVLSI.pdf}, + year = {2012}, + date = {2012-01-01}, + urldate = {2012-01-01}, + pages = {67-70}, + booktitle = {Proceedings of the great lakes symposium on VLSI}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@article{FeiVLSI2011, + title = {Return Data Interleaving for Multi-Channel Embedded CMPs Systems}, + author = {Fei Hong and Aviral Shrivastava and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Hong2011TVLSI.pdf}, + year = {2011}, + date = {2011-06-01}, + journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, + number = {12769237}, + pages = {1351-1354}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {article} +} + +@article{LeeTVLSI2011, + title = {Static Analysis of Register File Vulnerability}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2011TVLSI.pdf}, + year = {2011}, + date = {2011-04-01}, + journal = {IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits}, + volume = {30}, + number = {4}, + pages = {606-616}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@inproceedings{AarulVLSI2011, + title = {LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches}, + author = {Aarul Jain and Aviral Shrivastava and Chaitali Chakrabarti}, + url = {https://mpslab-asu.github.io/publications/papers/Jain2011VLSID.pdf https://mpslab-asu.github.io/publications/slides/Jain2011VLSID.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the 24th International Conference on VLSI Design}, + pages = {298-303}, + booktitle = {IEEE Computer Society}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{PiotrISLPED2011, + title = {Fast and Energy-Efficient Constant-Coefficient FIR Filters Using Residue Number System}, + author = {Piotr Patronik and Krzysztof Berezowski and Stanislaw Piestrak and Janusz Biernat and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Patronik2011ISLPED.pdf}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED)}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KimDAC2011, + title = {CuMAPz: A tool to Analyze Memory Access Patterns in CUDA}, + author = {Yooseong Kim and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2011DAC.pdf https://mpslab-asu.github.io/publications/slides/Kim2011DAC.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the 48th Design Automation Conference (DAC)}, + pages = {128-133}, + research = {GPU Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{JeyapaulICPP2011, + title = {UnSync: A Soft-Error Resilient Redundant Multicore Architecture}, + author = {Reiley Jeyapaul and Fei Hong and Aviral Shrivastava and Abhishek Risheekesan and Kyoungwoo Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2011ICPP.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2011ICPP.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the International Conference on Parallel Processing (ICPP)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaICPP2011, + title = {Enabling Multithreading on CGRAs}, + author = {Aviral Shrivastava and Jared Pager and Reiley Jeyapaul and Mahdi Hamzeh and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2011ICPP.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2011ICPP.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the International Conference on Parallel Processing (ICPP)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{BaiASAP2011, + title = {Stack Data Management for Limited Local Memory (LLM) Multi-core Processors}, + author = {Ke Bai and Aviral Shrivastava and Saleel Kudchadker}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2011ASAP.pdf https://mpslab-asu.github.io/publications/slides/Bai2011ASAP.slides}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{BaiCASES2011, + title = {Vector class on limited local memory (LLM) multi-core processors}, + author = {Ke Bai and Di Lu and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2011CASES.pdf https://mpslab-asu.github.io/publications/slides/Bai2011CASES.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the 14th international conference on Compilers,architectures and synthesis for embedded systems (CASES)}, + pages = {215--224}, + booktitle = {ACM}, + address = {New York, NY, USA}, + series = {CASES '11}, + note = {ISBN 978-1-4503-0713-0}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@article{KimTODAES2011, + title = {Memory Access Optimization in compilation for Coarse Grain Reconfigurable Architectures}, + author = {Yongjoo Kim and Jongeun Lee and Aviral Shrivastava and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2011TODAES.pdf}, + year = {2011}, + date = {2011-01-01}, + journal = {ACM TODAES: ACM Transactions on Design Automation of Electronic Systems}, + volume = {11}, + number = {3}, + pages = {42:1-42:27}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {article} +} + +@article{KimTCAD2011, + title = {High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures}, + author = {Yongjoo Kim and Jongeun Lee and Aviral Shrivastava and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2011TCAD.pdf}, + year = {2011}, + date = {2011-01-01}, + journal = {IEEE TCAD: IEEE Transactions on Computer Aided Design}, + volume = {30}, + number = {11}, + pages = {1599 - 1609}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {article} +} + +@mastersthesis{PagerMASTERTHESIS2011, + title = {Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems}, + author = {Jared Pager}, + url = {https://mpslab-asu.github.io/publications/papers/Pager2011THESIS.pdf https://mpslab-asu.github.io/publications/slides/Pager2011THESIS.pptx}, + year = {2011}, + date = {2011-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{LuCODESISSS2011, + title = {Branch Penalty Reduction on IBM Cell SPUs via Software Branch Hinting}, + author = {Jing Lu and Yooseong Kim and Aviral Shrivastava and Chuan Huang}, + url = {https://mpslab-asu.github.io/publications/papers/Lu2011CODES.pdf https://mpslab-asu.github.io/publications/slides/Lu2011CODES.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of CODES+ISSS}, + pages = {355-364}, + research = {Power, Temperature and Variation Aware Computing, Software Branch Hinting}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{JeyapaulCASES2011, + title = {Smart Cache Cleaning: Energy efficient vulnerability reduction in embedded processors}, + author = {Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2011CASES.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2011CASES.pptx}, + year = {2011}, + date = {2011-01-01}, + booktitle = {Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems}, + pages = {105--114}, + booktitle = {ACM}, + series = {CASES '11}, + key = {978-1-4503-0713-0}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@article{LeeTODAES2010, + title = {Partitioning Techniques for Partially Protected Caches in Resource-Constrained Embedded Systems}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Ilya Issenin and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2010TODAES.pdf}, + year = {2010}, + date = {2010-10-01}, + journal = {ACM TODAES: ACM Transactions on Design Automation of Embedded Systems}, + volume = {15}, + number = {4}, + pages = {30:1-30:30}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@inproceedings{AaCODESISSS2010, + title = {Compilation Techniques for CGRAs: Exploring All Parallelization Approaches}, + author = {Tom Vander Aa and Praveen Raghavan and Scott Mahlke and Bjorn De Sutter and Aviral Shrivastava and Frank Hannig}, + url = {https://mpslab-asu.github.io/publications/papers/Vanderaa2010CODES.pdf}, + year = {2010}, + date = {2010-10-01}, + pages = {185-186}, + booktitle = {Hardware/Software Codesign and System Synthesis (CODES+ISSS)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{JungASAP2010, + title = {Dynamic code mapping for limited local memory systems}, + author = {Seungchul Jung and Aviral Shrivastava and Ke Bai}, + url = {https://mpslab-asu.github.io/publications/papers/Jung2010ASAP.pdf https://mpslab-asu.github.io/publications/slides/Jung2010ASAP.pptx}, + year = {2010}, + date = {2010-07-01}, + booktitle = {Proceedings of the International Conference on Application-specific Systems Architectures and Processors (ASAP)}, + note = {ISSN 1063-6268}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@article{LeeTCAD2010, + title = {A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2010TCAD.pdf}, + year = {2010}, + date = {2010-07-01}, + journal = {IEEE TCAD: IEEE Transactions on Computer Aided Design}, + volume = {29}, + number = {7}, + pages = {1018-1027}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@inproceedings{ShrivastavaLCTES2010, + title = {Cache Vulnerability Equations for protecting data in embedded processor caches from soft errors}, + author = {Aviral Shrivastava and Jongeun Lee and Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2010LCTES.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2010LCTES.slides}, + year = {2010}, + date = {2010-01-01}, + journal = {SIGPLAN}, + volume = {45}, + number = {4}, + pages = {143-152}, + booktitle = {Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems}, + note = {ISSN 0362-1340}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{JeyapaulSCOPES2010, + title = {B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems}, + author = {Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2010SCOPES.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2010SCOPES.pptx}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems(SCOPES)}, + pages = {2:1-2:10}, + series = {SCOPES '10}, + note = {ISBN 978-1-4503-0084-1}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KimLCTES2010, + title = {Operation and data mapping for CGRAs with multi-bank memory}, + author = {Yongjoo Kim and Jongeun Lee and Aviral Shrivastava and Jonghee Yoon and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2010LCTES.pdf https://mpslab-asu.github.io/publications/slides/Kim2010LCTES.slides}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 2010 International Conference on Languages Compilers and Tools for Embedded Systems (LCTES)}, + volume = {45}, + number = {4}, + pages = {17-26}, + note = {ISSN 0362-1340}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KimHIPEAC2010, + title = {Memory-Aware Application Mapping on Coarse Grain Reconfigurable Arrays}, + author = {Yongjoo Kim and Jongeun Lee and Aviral Shrivastava and Jonghee Yoon and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Kim2010HIPEAC.pdf}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 2010 International Conference on High-Performance Embedded Architectures and Compilers (HIPEAC)}, + volume = {45}, + number = {4}, + pages = {17-26}, + note = {ISSN 0362-1340}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@article{ShrivastavaTVLSI2010, + title = {Reducing Functional Unit Power Consumption and its Variation using Leakage Sensors}, + author = {Aviral Shrivastava and Deepa Kannan and Sarvesh Bhardwaj and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2010TVLSI.pdf}, + year = {2010}, + date = {2010-01-01}, + journal = {IEEE TVLSI : IEEE Transactions on Very Large Scale Integration Systems}, + volume = {18}, + number = {6}, + pages = {988-997}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {article} +} + +@inproceedings{BoydDATE2011, + title = {Power-Accuracy Tradeoffs in Human Activity Transition Detection}, + author = {Jeffrey Boyd and Hari Sundaram and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Boyd2010DATE.pdf https://mpslab-asu.github.io/publications/slides/Boyd2010DATE.pptx}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 2010 International Conference on Design Automation and Test in Europe (DATE)}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@book{PandaSPRINGER2010, + title = {Power-Efficient System Design}, + author = {Preeti Ranjan Panda and Aviral Shrivastava and B V N Silpa and Krishnaiah Gummidipudi}, + url = {http://www.springer.com/us/book/9781441963871}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Springer}, + edition = {1st edition}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {book} +} + +@mastersthesis{SaleelMASTERTHESIS2010, + title = {Managing Stack Data on Limited Local Memory Multi-core Processors}, + author = {Saleel Kudchadker}, + url = {https://mpslab-asu.github.io/publications/papers/Kudchadker2010THESIS.pdf https://mpslab-asu.github.io/publications/slides/Kudchadker2010THESIS.slides}, + year = {2010}, + date = {2010-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Masters Thesis} +} + +@mastersthesis{FeiMASTERTHESIS2010, + title = {UnSync: A Soft-Error Resilient Redundant CMP Architecture}, + author = {Fei Hong}, + url = {https://mpslab-asu.github.io/publications/papers/Hong2010THESIS.pdf}, + year = {2010}, + date = {2010-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inproceedings{BaiCODESISSS2010, + title = {Heap Data Management for Limited Local Memory (LLM) Multi-core Processors}, + author = {Ke Bai and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Bai2010CODES.pdf https://mpslab-asu.github.io/publications/slides/Bai2010CODES.pptx}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Proceedings of the 23th international symposium on System Synthesis (CODES+ISSS)}, + pages = {317-326}, + booktitle = {ACM Press}, + address = {New York, NY, USA}, + note = {ISBN}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{JungMASTERTHESIS2010, + title = {Dynamic Code Mapping for Limited Local Memory Systems}, + author = {Seungchul Jung}, + url = {https://mpslab-asu.github.io/publications/papers/Jung2010THESIS.pdf https://mpslab-asu.github.io/publications/slides/Jung2010THESIS.pptx}, + year = {2010}, + date = {2010-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Masters Thesis} +} + +@article{JeyapaulVLSID2010, + title = {Code Transformations for TLB Power Reduction}, + author = {Reiley Jeyapaul and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2010IJPP.pdf}, + year = {2010}, + date = {2010-01-01}, + journal = {International Journal of Parallel Programming}, + volume = {38}, + number = {3-4}, + pages = {254-276}, + booktitle = {Springer US}, + note = {ISSN 0885-7458}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {article} +} + +@inbook{PandaBOOK2010, + title = {Basic Low Power Digital Design}, + author = {Preeti Ranjan Panda and B V N Silpa and Aviral Shrivastava and Krishnaiah Gummidipudi}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Power-efficient System Design}, + number = {978-1-4419-6387-1}, + pages = {11-39}, + booktitle = {Springer US}, + chapter = {2}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Book} +} + +@inbook{PandaBook2010_2, + title = {Power Aware Operating Systems, Compilers, and Application Software}, + author = {Preeti Ranjan Panda and B V N Silpa and Aviral Shrivastava and Krishnaiah Gummidipudi}, + year = {2010}, + date = {2010-01-01}, + booktitle = {Power-efficient System Design}, + number = {978-1-4419-6387-1}, + pages = {139-181}, + booktitle = {Springer US}, + chapter = {5}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Book} +} + +@inproceedings{ChokshiCASES2009, + title = {Exploiting residue number system for power-efficient digital signal processing in embedded processors}, + author = {Rooju Chokshi and Krzysztof Berezowski and Aviral Shrivastava and Stanislaw Piestrak}, + url = {https://mpslab-asu.github.io/publications/papers/Chokshi2009CASES.pdf https://mpslab-asu.github.io/publications/slides/Chokshi2009CASES.pptx}, + year = {2009}, + date = {2009-01-01}, + booktitle = {CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems}, + pages = {19-28}, + note = {ISBN 978-1-60558-626-7}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{LeeLCTES2009, + title = {A compiler optimization to reduce soft errors in register files}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2009LCTES.pdf https://mpslab-asu.github.io/publications/slides/Lee2009LCTES.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {LCTES '09: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems}, + pages = {41-49}, + note = {ISBN 978-1-60558-356-3}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{SoaresVLSISOC2009, + title = {Adaptive Reduced Bit-width Instruction Set Architecture (adapt-rISA)}, + author = {Sandro Neves Soares and Ashok Halambi and Aviral Shrivastava and Flavio Rech Wagner and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Soares2009VLSISOC.pdf https://mpslab-asu.github.io/publications/slides/Soares2009VLSISOC.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {VLSI-SOC 2009 :Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integreation}, + research = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{MylavarapuDATE2009, + title = {FSAF: File system aware flash translation layer for NAND Flash Memories}, + author = {Sai Krishna Mylavarapu and Siddharth Choudhuri and Aviral Shrivastava and Jongeun Lee and T Givargis}, + url = {https://mpslab-asu.github.io/publications/papers/Mylavarapu2009DATE.pdf https://mpslab-asu.github.io/publications/slides/Mylavarapu2009DATE.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {Design, Automation Test in Europe Conference Exhibition (DATE)}, + note = {ISSN 1530-1591}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{LeeDATE2009, + title = {Static analysis to mitigate soft errors in register files}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2009DATE.pdf https://mpslab-asu.github.io/publications/slides/Lee2009DATE.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {Design, Automation Test in Europe Conference Exhibition (DATE)}, + note = {ISSN 1530-1591}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KannanASPDAC2009, + title = {A software solution for dynamic stack management on scratch pad memory}, + author = {Arun Kannan and Aviral Shrivastava and Amit Pabalkar and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2009ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Kannan2009ASPDAC.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation}, + pages = {612-617}, + note = {ISBN 978-1-4244-2748-2}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{LeeASPDAC2009, + title = {Compiler-managed register file protection for energy-efficient soft error reduction}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2009ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Lee2009ASPDAC.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation}, + pages = {618-623}, + note = {ISBN 978-1-4244-2748-2}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{JeyapaulVLSI2009, + title = {Code Transformations for TLB Power Reduction}, + author = {Reiley Jeyapaul and Sandeep Marathe and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2009VLSID.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2009VLSID.slides}, + year = {2009}, + date = {2009-01-01}, + booktitle = {VLSID '09: Proceedings of the International Conference on VLSI Design}, + pages = {413-418}, + note = {ISBN 978-0-7695-3506-7}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{ArunMASTERTHESIS2009, + title = {A Software-Only Solution for Stack Management on Systems with Scratch Pad Memory}, + author = {Arun Kannan}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2009THESIS.pdf https://mpslab-asu.github.io/publications/slides/Kannan2009THESIS.slides}, + year = {2009}, + date = {2009-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Masters Thesis} +} + +@article{ShrivastavaTCAD2009, + title = {A Software-only solution to use Scratch Pads for Stack Data}, + author = {Aviral Shrivastava and Arun Kannan and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2009TCADA.pdf}, + year = {2009}, + date = {2009-01-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + volume = {28}, + number = {11}, + pages = {1719-1728}, + note = {ISSN 0278-0070}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {article} +} + +@article{ShrivastavaTCADCIL2009, + title = {Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures}, + author = {Aviral Shrivastava and Ilya Issenin and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2009TCADB.pdf}, + year = {2009}, + date = {2009-01-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + volume = {28}, + number = {3}, + pages = {461-466}, + note = {ISSN 0278-0070}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {article} +} + +@article{YoonTVLSI2009, + title = {A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures}, + author = {Jonghee Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Yoon2009TVLSI.pdf}, + year = {2009}, + date = {2009-01-01}, + journal = {IEEE Transactions on Very Large Scale Integrated Circuits}, + volume = {17}, + number = {11}, + pages = {1565-1579}, + note = {ISSN 1063-8210}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {article} +} + +@article{LeeTVLSI2009, + title = {Partially Protected Caches to Reduce Failures due to Soft Errors in Multimedia Applications}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Ilya Issenin and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2009TVLSI.pdf}, + year = {2009}, + date = {2009-01-01}, + journal = {IEEE Transactions on VLSI}, + volume = {17}, + number = {9}, + pages = {1343-1348}, + note = {ISSN 1063-8210}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@mastersthesis{AmitMASTERTHESIS2009, + title = {A Dynamic Code Mapping Technique for Scratch Pad Memories in Embedded Systems}, + author = {Amit Pabalkar}, + url = {https://mpslab-asu.github.io/publications/papers/Pabalkar2009THESIS.pdf https://mpslab-asu.github.io/publications/slides/Pabalkar2009THESIS.slides}, + year = {2009}, + date = {2009-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Masters Thesis} +} + +@mastersthesis{RoojuMASTERTHESIS2009, + title = {Residue number system enhancements for programmable processors}, + author = {Rooju Chokshi}, + url = {https://mpslab-asu.github.io/publications/papers/Chokshi2009THESIS.pdf https://mpslab-asu.github.io/publications/slides/Chokshi2009THESIS.slides}, + year = {2009}, + date = {2009-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Masters Thesis} +} + +@mastersthesis{SaiMASTERTHESIS2009, + title = {Improving Application Response Times of Nand Flash based Systems}, + author = {Sai Krishna Mylavarapu}, + url = {https://mpslab-asu.github.io/publications/papers/Mylavarapu2009THESIS.pdf https://mpslab-asu.github.io/publications/slides/Mylavarapu2009THESIS.slides}, + year = {2009}, + date = {2009-01-01}, + school = {School of Computing, Informatics, and Decision Systems Engineering (CIDSE)}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Masters Thesis} +} + +@techreport{LeeTECHREPORT2008, + title = {Cross-Layer Interactions of Error Control Schemes in Mobile Multimedia Systems}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Minyoung Kim and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008REPORTA.pdf}, + year = {2008}, + date = {2008-07-01}, + institution = {University of California, Irvine}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Tech Report} +} + +@article{ParkTCAD2008, + title = {Register File Power Reduction Using Bypass Sensitive Compiler}, + author = {Sanghyun Park and Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau and Yunheung Paek and Eugene Earlie}, + url = {https://mpslab-asu.github.io/publications/papers/Park2008TCAD.pdf}, + year = {2008}, + date = {2008-06-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + volume = {27}, + number = {6}, + pages = {1155-1159}, + note = {ISSN 0278-0070}, + research = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {article} +} + +@techreport{LeeTECHREPORT2008_2, + title = {Partially Protected Caches to Reduce Failures due to Soft Errors in Mission-Critical Multimedia Systems}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Ilya Issenin and Nikil Dutt and Nalini Venkatasubramanian}, + year = {2008}, + date = {2008-06-01}, + institution = {University of California, Irvine}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Tech Report} +} + +@inproceedings{LeeCODESISSS2008, + title = {Static analysis of processor stall cycle aggregation}, + author = {Jongeun Lee and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008CODES.pdf https://mpslab-asu.github.io/publications/slides/Lee2008CODES.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {CODES/ISSS '08: Proceedings of the international conference on Hardware/Software codesign and system synthesis}, + pages = {25-30}, + note = {ISBN 978-1-60558-470-6}, + research = {Power, Temperature and Variation Aware Computing, Processor Idle Cycle Aggregation}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{PabalkarHIPC2008, + title = {SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories}, + author = {Amit Pabalkar and Aviral Shrivastava and Arun Kannan and Jongeun Lee}, + url = {https://mpslab-asu.github.io/publications/papers/Pabalkar2008HIPC.pdf https://mpslab-asu.github.io/publications/slides/Pabalkar2008HIPC.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {HIPC 2008 :International Conference on High Performance Computing}, + pages = {569-582}, + research = {Power, Temperature and Variation Aware Computing, Software Managed Manycore (SMM)}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{LeeMM2008, + title = {Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Minyoung Kim and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008MM.pdf https://mpslab-asu.github.io/publications/slides/Lee2008MM.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {MM '08: Proceeding of the 16th ACM international conference on Multimedia}, + pages = {319-328}, + note = {ISBN 978-1-60558-303-7}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ParkDATE2008, + title = {Hiding cache miss penalty using priority-based execution for embedded processors}, + author = {Sanghyun Park and Aviral Shrivastava and Yunheung Paek}, + year = {2008}, + date = {2008-01-01}, + booktitle = {DATE '08: Proceedings of the conference on Design, automation and test in Europe}, + note = {ISBN 978-3-9810801-3-1}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{YoonDAC2008, + title = {SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures}, + author = {Jonghee Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Reiley Jeyapaul and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Yoon2008ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Yoon2008ASPDAC.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation}, + pages = {776-782}, + note = {ISBN 978-1-4244-1922-7 (Best Paper Award Candidate)}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaDAC2008, + title = {A compiler-in-the-loop framework to explore horizontally partitioned cache architectures}, + author = {Aviral Shrivastava and Ilya Issenin and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2008ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2008ASPDAC.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation}, + pages = {328-333}, + note = {ISBN 978-1-4244-1922-7}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KannanVLSID2008, + title = {PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors}, + author = {Deepa Kannan and Aseem Gupta and Aviral Shrivastava and Nikil Dutt and Fadi J Kurdahi}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2008VLSIDA.pdf https://mpslab-asu.github.io/publications/slides/Kannan2008VLSIDA.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {VLSID '08: Proceedings of the 21st International Conference on VLSI Design}, + pages = {421-427}, + note = {ISBN 0-7695-3083-4}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{KannanVLSI2008, + title = {Temperature and Process Variations aware Power Gating of Functional Units}, + author = {Deepa Kannan and Aviral Shrivastava and Vipin Mohan and Sarvesh Bhardwaj and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2008VLSIDB.pdf}, + year = {2008}, + date = {2008-01-01}, + booktitle = {VLSID '08: Proceedings of the 21st International Conference on VLSI Design}, + pages = {515-520}, + note = {ISBN 0-7695-3083-4}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@incollection{MishraPDL2008, + title = {ADL-Driven Methodologies for Design Automation of Programmable Architectures}, + author = {Prabhat Mishra and Aviral Shrivastava}, + url = {http://dl.acm.org/citation.cfm?id=1481522}, + year = {2008}, + date = {2008-01-01}, + booktitle = {Processor Description Languages: Applications and Methodologies}, + series = {Systems on Silicon}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Collection} +} + +@article{LeeDESDMR2008, + title = {Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008DESD.pdf https://mpslab-asu.github.io/publications/slides/Lee2008DESD.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {DIPES 2008 :IFIP Conference on Distributed and Parallel Embedded Systems}, + journal = {Distributed Embedded Systems: Design, Middleware and Resources}, + volume = {271}, + pages = {213-225}, + note = {10.1007/978-0-387-09661-2_21}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {article} +} + +@inproceedings{KannanVLSID2008_2, + title = {Power Reduction of Functional Units Considering Temperature and Process Variations}, + author = {Deepa Kannan and Aviral Shrivastava and Sarvesh Bhardwaj and Sarma Vrudhula}, + url = {https://mpslab-asu.github.io/publications/papers/Kannan2008VLSIDC.pdf https://mpslab-asu.github.io/publications/slides/Kannan2008VLSIDC.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {VLSID'08: Proceedings of the 21st International Conference on VLSI Design}, + pages = {533--539}, + booktitle = {IEEE Computer Society}, + address = {Washington, DC, USA}, + note = {ISBN 0-7695-3083-4}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@mastersthesis{JeyapaulMASTERTHESIS2008, + title = {Static Analysis to Mitigate Soft Error Failures in Processors}, + author = {Reiley Jeyapaul}, + url = {https://mpslab-asu.github.io/publications/papers/Jeyapaul2008THESIS.pdf https://mpslab-asu.github.io/publications/slides/Jeyapaul2008THESIS.pptx}, + year = {2008}, + date = {2008-01-01}, + school = {Arizona State University}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Masters Thesis} +} + +@inbook{MishraBOOK2008, + title = {ADL-driven Methodologies for Design Automation of Embedded Processors}, + author = {Prabhat Mishra and Aviral Shrivastava}, + year = {2008}, + date = {2008-01-01}, + booktitle = {Processor Description Languages}, + pages = {13-33}, + booktitle = {Elsevier Inc.}, + chapter = {2}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Book} +} + +@inproceedings{LeeACMMM2008, + title = {Mitigating the Impact of Hardware Defects on Multimedia Applications � A Cross-Layer Approach}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Minyoung Kim and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2008MM.pdf https://mpslab-asu.github.io/publications/slides/Lee2008MM.slides}, + year = {2008}, + date = {2008-01-01}, + booktitle = {ACM International Conference on Multimedia}, + booktitle = {ACM}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{BakerCODESISSS2007, + title = {Smart driver for power reduction in next generation bistable electrophoretic display technology}, + author = {Michael A Baker and Aviral Shrivastava and Karam S Chatha}, + url = {https://mpslab-asu.github.io/publications/papers/Baker2007CODES.pdf https://mpslab-asu.github.io/publications/slides/Baker2007CODES.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {CODES+ISSS '07: Proceedings of international conference on Hardware/software codesign and system synthesis}, + pages = {197-202}, + note = {ISBN 978-1-59593-824-4}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{YoonWASP2007, + title = {Power Conscious Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm}, + author = {Jonghee Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/slides/Yoon2007WASP.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {WASP '07: Workshop on Application Specific Processors}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ZhuDATE2007, + title = {Interactive presentation: Functional and timing validation of partially bypassed processor pipelines}, + author = {Qiang Zhu and Aviral Shrivastava and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Zhu2007DATE.pdf https://mpslab-asu.github.io/publications/slides/Zhu2007DATE.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {DATE '07: Proceedings of the conference on Design, automation and test in Europe}, + pages = {1164-1169}, + note = {ISBN 978-3-9810801-2-4}, + research = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{MisraICC2007, + title = {Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors}, + author = {Satyajayant Misra and Guoliang Xue and Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Misra2007ICC.pdf https://mpslab-asu.github.io/publications/slides/Misra2007ICC.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {ICC '07. IEEE International Conference on Communications}, + pages = {3057-3062}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@incollection{ShrivastavaTCDHOAMCG22007, + title = {Compiler Aided Design of Embedded Computers}, + author = {Aviral Shrivastava and Nikil Dutt}, + url = {https://www.crcpress.com/The-Compiler-Design-Handbook-Optimizations-and-Machine-Code-Generation/Srikant-Shankar/9781420043822}, + year = {2007}, + date = {2007-01-01}, + booktitle = {The Compiler Design Handbook: Optimizations and Machine Code Generation:2nd Edition}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Collection} +} + +@article{ParkTCAD2007, + title = {Automatic Design Space Exploration of Register Bypasses in Embedded Processors}, + author = {Sanghyun Park and Aviral Shrivastava and Eugene Earlie and Nikil Dutt and Alexandru Nicolau and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Park2007TCAD.pdf}, + year = {2007}, + date = {2007-01-01}, + journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, + volume = {26}, + number = {12}, + pages = {2102-2115}, + note = {ISSN 0278-0070}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {article} +} + +@inproceedings{YoonVLSI2007, + title = {Efficient Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm}, + author = {Jonghee Yoon and Aviral Shrivastava and Sanghyun Park and Minwook Ahn and Reiley Jeyapaul and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Yoon2007VLSID.pdf https://mpslab-asu.github.io/publications/slides/Yoon2007VLSID.slides}, + year = {2007}, + date = {2007-01-01}, + booktitle = {2007 International Conference on VLSI Design (VLSID 2007)}, + booktitle = {IEEE}, + research = {Coarse-Grained Reconfigurable Arrays}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{LeeCASES2006, + title = {Mitigating soft error failures for multimedia applications by selective data protection}, + author = {Kyoungwoo Lee and Aviral Shrivastava and Ilya Issenin and Nikil Dutt and Nalini Venkatasubramanian}, + url = {https://mpslab-asu.github.io/publications/papers/Lee2006CASES.pdf https://mpslab-asu.github.io/publications/slides/Lee2006CASES.slides}, + year = {2006}, + date = {2006-01-01}, + booktitle = {CASES '06: Proceedings of the international conference on Compilers, architecture and synthesis for embedded systems}, + pages = {411-420}, + note = {ISBN 1-59593-543-6}, + research = {Reliability for Machine Learning}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ParkLCTES2006, + title = {Bypass Aware Instruction Scheduling for Register File Power Reduction}, + author = {Sanghyun Park and Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau and Yunheung Paek and Eugene Earlie}, + url = {https://mpslab-asu.github.io/publications/papers/Park2006LCTES.pdf https://mpslab-asu.github.io/publications/slides/Park2006LCTES.slides}, + year = {2006}, + date = {2006-01-01}, + booktitle = {Proceedings of the conference on Language, Compilers and Tool support for Embedded Systems}, + pages = {173-181}, + note = {ISBN 0362-1340}, + research = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ParkDATE2006, + title = {Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors}, + author = {Sanghyun Park and Eugene Earlie and Aviral Shrivastava and Alexandru Nicolau and Nikil Dutt and Yunheung Paek}, + url = {https://mpslab-asu.github.io/publications/papers/Park2006DATE.pdf https://mpslab-asu.github.io/publications/slides/Park2006DATE.slides}, + year = {2006}, + date = {2006-01-01}, + booktitle = {DATE '06: Proceedings of the conference on Design, automation and test in Europe}, + pages = {1197-1202}, + note = {ISBN 3-9810801-0-6}, + research = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@article{MishraTODAES2006, + title = {Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs}, + author = {Prabhat Mishra and Aviral Shrivastava and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Mishra2006TOADAES.pdf}, + year = {2006}, + date = {2006-01-01}, + journal = {ACM Transactions on Design Automation of Electronic Systems}, + volume = {11}, + number = {3}, + pages = {626-658}, + note = {ISSN 1084-4309}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {article} +} + +@article{ShrivastavaTVLSI2006, + title = {Retargetable pipeline hazard detection for partially bypassed processors}, + author = {Aviral Shrivastava and Eugene Earlie and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2006TVLSI.pdf}, + year = {2006}, + date = {2006-01-01}, + booktitle = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, + volume = {14}, + pages = {791-801}, + note = {ISBN 1063-8210}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {article} +} + +@article{ShrivastavaTODAES2006, + title = {Compilation framework for code size reduction using reduced bit-width ISAs (rSAs)}, + author = {Aviral Shrivastava and Partha Biswas and Ashok Halambi and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2006TODAES.pdf}, + year = {2006}, + date = {2006-01-01}, + journal = {ACM Transactions on Design Automation of Electronic Systems}, + volume = {11}, + number = {1}, + pages = {123-146}, + note = {ISSN 1084-4309}, + research = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + category = {article} +} + +@phdthesis{ShrivastavaPHDTHESIS2006, + title = {Compiler-in-Loop Exploration of Programmable Embedded Systems}, + author = {Aviral Shrivastava}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2006THESIS.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2006THESIS.slides}, + year = {2006}, + date = {2006-01-01}, + school = {Donald Bren School of Information and Computer Sciences}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {PhD Thesis} +} + +@inproceedings{ShrivastavaCASES2005, + title = {Compilation techniques for energy reduction in horizontally partitioned cache architectures}, + author = {Aviral Shrivastava and Ilya Issenin and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2005CASES.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2005CASES.slides}, + year = {2005}, + date = {2005-01-01}, + booktitle = {CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems}, + pages = {90-96}, + note = {ISBN 1-59593-149-X}, + research = {Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaCODESISSS2005, + title = {Aggregating processor free time for energy reduction}, + author = {Aviral Shrivastava and Eugene Earlie and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2005CODES.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2005CODES.slides}, + year = {2005}, + date = {2005-01-01}, + booktitle = {CODES+ISSS '05: Proceedings of the international conference on Hardware/software codesign and system synthesis}, + pages = {154-159}, + note = {ISBN 1-59593-161-9}, + research = {Power, Temperature and Variation Aware Computing, Processor Idle Cycle Aggregation}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaDATE2005, + title = {PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors}, + author = {Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau and Eugene Earlie}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2005DATE.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2005DATE.slides}, + year = {2005}, + date = {2005-01-01}, + booktitle = {DATE '05: Proceedings of the conference on Design, Automation and Test in Europe}, + research = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaTECHCONSRC2005, + title = {Compiler-in-the-Loop ADL-driven Early Architectural Exploration}, + author = {Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau and Eugene Earlie}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2005TECHCON.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2005TECHCON.slides}, + year = {2005}, + date = {2005-01-01}, + booktitle = {TECHCON 2005: Semiconductor Research Corporation}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaCODES2004, + title = {Operation tables for scheduling in the presence of incomplete bypassing.}, + author = {Aviral Shrivastava and Eugene Earlie and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2004CODES.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2004CODES.slides}, + year = {2004}, + date = {2004-01-01}, + booktitle = {CODES+ISSS}, + pages = {194-199}, + research = {Bypass Aware Compiler, Power, Temperature and Variation Aware Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaASPDAC2004, + title = {Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)}, + author = {Aviral Shrivastava and Nikil Dutt}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2004ASPDAC.pdf https://mpslab-asu.github.io/publications/slides/Shrivastava2004ASPDAC.slides}, + year = {2004}, + date = {2004-01-01}, + booktitle = {ASP-DAC '04: Proceedings of the 2004 conference on Asia South Pacific design automation}, + pages = {475-477}, + note = {ISBN 0-7803-8175-0}, + research = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + category = {Proceedings} +} + +@techreport{PasrichaTECHREPORT2003, + title = {A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor}, + author = {Sudeep Pasricha and Partha Biswas and Prabhat Mishra and Aviral Shrivastava and Atri Mandal and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Pasricha2003REPORT.pdf}, + year = {2003}, + date = {2003-04-01}, + institution = {University of California, Irvine}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Tech Report} +} + +@inproceedings{HalambiISSS2002, + title = {A design space exploration framework for reduced bit-width instruction set architecture (rISA) design}, + author = {Ashok Halambi and Aviral Shrivastava and Partha Biswas and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Halambi2002ISSS.pdf https://mpslab-asu.github.io/publications/slides/Halambi2002ISSS.slides}, + year = {2002}, + date = {2002-01-01}, + booktitle = {ISSS '02: Proceedings of the 15th international symposium on System Synthesis}, + pages = {120-125}, + note = {ISBN 1-58113-576-9}, + research = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{HalambiDATE2002, + title = {An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs}, + author = {Ashok Halambi and Aviral Shrivastava and Partha Biswas and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Halambi2002DATE.pdf https://mpslab-asu.github.io/publications/slides/Halambi2002DATE.slides}, + year = {2002}, + date = {2002-01-01}, + booktitle = {DATE '02: Proceedings of the conference on Design, automation and test in Europe}, + pages = {402}, + research = {Power, Temperature and Variation Aware Computing, Reduced bit-width Instruction Set Architecture}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{HalambiSCOPES2001, + title = {A customizable compiler framework for embedded systems}, + author = {Ashok Halambi and Aviral Shrivastava and Nikil Dutt and Alexandru Nicolau}, + url = {https://mpslab-asu.github.io/publications/papers/Halambi2001SCOPES.pdf}, + year = {2001}, + date = {2001-01-01}, + booktitle = {In SCOPES}, + booktitle = {Springer}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Proceedings} +} + +@inproceedings{ShrivastavaVLSI2000, + title = {Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming}, + author = {Aviral Shrivastava and Mohit Kumar and Sanjiv Kapoor and Shashi Kumar and M Balakrishnan}, + url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2000VLSID.pdf}, + year = {2000}, + date = {2000-01-01}, + booktitle = {VLSID '00: Proceedings of the 13th International Conference on VLSI Design}, + pages = {110}, + note = {ISBN 0-7695-0487-6}, + research = {Efficient Embedded Computing}, + pubstate = {published}, + category = {Proceedings} +} + diff --git a/src/data/software.json b/src/data/software.json new file mode 100644 index 0000000..bbec19f --- /dev/null +++ b/src/data/software.json @@ -0,0 +1,79 @@ +[ + { + "name": "DSP-MLIR", + "url": "https://github.com/MPSLab-ASU/DSP_MLIR", + "description": "Digital Signal Processing Compiler in MLIR", + "researchGroup": "MLIR", + "image": "/images/software/dsp-mlir.png" + }, + { + "name": "nZDC", + "url": "https://github.com/MPSLab-ASU/nZDC-Compiler", + "description": "LLVM based compiler for near zero silent data corruption.", + "researchGroup": "MLIR", + "image": "/images/software/nzdc.png" + }, + { + "name": "LLVM-r", + "url": "https://github.com/MPSLab-ASU/LLVM-r", + "description": "Resilience-aware LLVM based compiler with instruction-based duplication for error protection.", + "researchGroup": "MLIR", + "image": "/images/software/llvm-r.png" + }, + { + "name": "Expert", + "url": "https://github.com/MPSLab-ASU/EXPERT---Redundant-MultiThreding", + "description": "Error detection support with redundant multi-threading.", + "researchGroup": "MLIR", + "image": "/images/software/expert.png" + }, + { + "name": "GemV", + "url": "https://github.com/MPSLab-ASU/gemV", + "description": "Micro-architecture vulnerability estimation tool (based on gem5 simulator). For a brief summary of error resilience tools, please visit this page .", + "researchGroup": "MLIR", + "image": "/images/software/gemv.png" + }, + { + "name": "dMazeRunner", + "url": "https://github.com/MPSLab-ASU/dMazeRunner", + "description": "Dataflow optimization infrastructure for coarse-grain programmable accelerators.", + "researchGroup": "Machine Learning Accelerators", + "image": "/images/software/dmazerunner.png" + }, + { + "name": "DiRAC", + "url": "https://github.com/MPSLab-ASU/DiRAC", + "description": "Architecture template and cycle-level microarchitecture simulator for dataflow accelerators.", + "researchGroup": "Machine Learning Accelerators", + "image": "/images/software/dirac.png" + }, + { + "name": "CCF", + "url": "https://github.com/MPSLab-ASU/ccf", + "description": "CGRA compilation and simulation framework.", + "researchGroup": "Accelerated Computing", + "image": "/images/software/ccf.png" + }, + { + "name": "SMM toolchain", + "url": "https://github.com/cmlasu/smm_frameworks", + "description": "Toolchain for application execution on SMM architectures.", + "researchGroup": "Software Managed Manycores", + "image": "/images/software/smm-toolchain.png" + }, + { + "name": "TMA", + "url": "https://github.com/cmlasu/tma", + "description": "Timestamp based monitoring tool for CPS applications.", + "researchGroup": "Cyber-Physical & IoT Systems", + "image": "/images/software/tma.png" + }, + { + "name": "Jobbed", + "url": "https://github.com/MPSLab-ASU/Jobbed", + "description": "RTOS for the Raspberry Pi 2B", + "researchGroup": "Cyber-Physical & IoT Systems", + "image": "/images/software/jobbed.png" + } +] \ No newline at end of file diff --git a/src/data/sponsors.json b/src/data/sponsors.json new file mode 100644 index 0000000..86024d4 --- /dev/null +++ b/src/data/sponsors.json @@ -0,0 +1,57 @@ +[ + { + "name": "NSF", + "logo": "/images/sponsors/logo-nsf.jpg", + "url": "" + }, + { + "name": "Intel", + "logo": "/images/sponsors/intlogo.jpg", + "url": "" + }, + { + "name": "Semiconductor Research Corporation", + "logo": "/images/sponsors/semiconductor-research-corporation-wikipedia.png", + "url": "" + }, + { + "name": "NVIDIA", + "logo": "/images/sponsors/nvidia-logo.jpg", + "url": "" + }, + { + "name": "NIST", + "logo": "/images/sponsors/nist.png", + "url": "http://www.nist.gov/" + }, + { + "name": "Department of Energy", + "logo": "/images/sponsors/new-doe-logo-color-web.jpg", + "url": "http://www.energy.gov/" + }, + { + "name": "Raytheon", + "logo": "/images/sponsors/rtn-logo.gif", + "url": "" + }, + { + "name": "Science Foundation Arizona", + "logo": "/images/sponsors/logosfaz.gif", + "url": "" + }, + { + "name": "Microsoft Research", + "logo": "/images/sponsors/logo-msr.png", + "url": "" + }, + { + "name": "SignHear", + "logo": "/images/sponsors/signhear-logo.png", + "url": "" + }, + { + "name": "Semiconductor Design Center", + "logo": "/images/sponsors/sdc-color.gif", + "url": "" + } +] \ No newline at end of file diff --git a/src/env.d.ts b/src/env.d.ts new file mode 100644 index 0000000..acef35f --- /dev/null +++ b/src/env.d.ts @@ -0,0 +1,2 @@ +/// +/// diff --git a/src/layouts/Layout.astro b/src/layouts/Layout.astro new file mode 100644 index 0000000..59b998c --- /dev/null +++ b/src/layouts/Layout.astro @@ -0,0 +1,37 @@ +--- +import '../styles/main.scss'; + +interface Props { + title: string; + description?: string; +} + +const { title, description = 'MPS Lab — Making Programming Simple at Arizona State University' } = Astro.props; +--- + + + + + + + + + {title} | MPS Lab @ ASU + + + + + +
+ +
+ + + diff --git a/src/pages/contact.astro b/src/pages/contact.astro new file mode 100644 index 0000000..2bbd314 --- /dev/null +++ b/src/pages/contact.astro @@ -0,0 +1,128 @@ +--- +import Footer from "../components/astro/Footer.astro"; +import Navbar from "../components/astro/Navbar.astro"; +import Layout from "../layouts/Layout.astro"; +--- + + + + +
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