diff --git a/README.md b/README.md index bcebba8..724f4b9 100644 --- a/README.md +++ b/README.md @@ -136,4 +136,12 @@ nix-shell -p imagemagick --run "convert frame.ppm frame.png" python convert.py -python.exe .\load_program.py .\programs\test.hex --port COM6 \ No newline at end of file +python.exe .\load_program.py .\programs\test.hex --port COM6 + +## New VGA Testing +``` +cd generated +verilator --cc --exe --build -j 0 ../simulation/vga-image.cpp -f filelist.f --top VGAController +./obj_dir/VVGAController +ffmpeg -i frame.ppm frame.png -y +``` \ No newline at end of file diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v index 6678366..b54ee29 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v @@ -54,7 +54,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__25.00000______0.000______50.0______175.402_____98.575 +// clk_out2__250.00000______0.000______50.0______110.209_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo index 8e682f1..234c973 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.veo @@ -53,7 +53,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__25.00000______0.000______50.0______175.402_____98.575 +// clk_out2__250.00000______0.000______50.0______110.209_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml index 8ed3b55..b47c36e 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml @@ -1314,11 +1314,11 @@ GENtimestamp - Sun Apr 05 17:27:05 UTC 2026 + Sun Jun 14 20:24:19 UTC 2026 outputProductCRC - 9:ad4d551b + 9:86681ebc @@ -1333,11 +1333,11 @@ GENtimestamp - Sun Apr 05 17:27:05 UTC 2026 + Sun Jun 14 20:24:19 UTC 2026 outputProductCRC - 9:ad4d551b + 9:86681ebc @@ -1352,11 +1352,11 @@ GENtimestamp - Sun Apr 05 17:27:05 UTC 2026 + Sun Jun 14 20:24:19 UTC 2026 outputProductCRC - 9:067c9c1a + 9:e49d9c4c @@ -1371,11 +1371,11 @@ GENtimestamp - Sun Apr 05 17:27:05 UTC 2026 + Sun Jun 14 20:24:19 UTC 2026 outputProductCRC - 9:067c9c1a + 9:e49d9c4c @@ -1386,7 +1386,7 @@ outputProductCRC - 9:067c9c1a + 9:e49d9c4c @@ -1397,7 +1397,7 @@ outputProductCRC - 9:7443706c + 9:c6be101f @@ -1411,11 +1411,11 @@ GENtimestamp - Sun Apr 05 17:27:05 UTC 2026 + Sun Jun 14 20:24:19 UTC 2026 outputProductCRC - 9:4527b5ca + 9:7f359653 @@ -1429,11 +1429,11 @@ GENtimestamp - Sun Apr 05 17:27:05 UTC 2026 + Sun Jun 14 20:24:19 UTC 2026 outputProductCRC - 9:067c9c1a + 9:e49d9c4c @@ -1444,7 +1444,7 @@ outputProductCRC - 9:067c9c1a + 9:e49d9c4c @@ -1460,11 +1460,11 @@ GENtimestamp - Sun Apr 05 17:27:05 UTC 2026 + Sun Jun 14 20:24:18 UTC 2026 outputProductCRC - 9:067c9c1a + 9:e49d9c4c @@ -1478,11 +1478,11 @@ GENtimestamp - Sun Apr 05 17:27:05 UTC 2026 + Sun Jun 14 20:24:19 UTC 2026 outputProductCRC - 9:067c9c1a + 9:e49d9c4c @@ -2725,7 +2725,7 @@ C_OUTCLK_SUM_ROW2 - clk_out2__25.00000______0.000______50.0______175.402_____98.575 + clk_out2__250.00000______0.000______50.0______110.209_____98.575 C_OUTCLK_SUM_ROW3 @@ -2753,7 +2753,7 @@ C_CLKOUT2_REQUESTED_OUT_FREQ - 25 + 250 C_CLKOUT3_REQUESTED_OUT_FREQ @@ -2837,7 +2837,7 @@ C_CLKOUT2_OUT_FREQ - 25.00000 + 250.00000 C_CLKOUT3_OUT_FREQ @@ -3005,7 +3005,7 @@ C_MMCM_CLKOUT1_DIVIDE - 40 + 4 C_MMCM_CLKOUT2_DIVIDE @@ -3531,7 +3531,7 @@ C_DIVIDE2_AUTO - 1.0 + 0.1 C_DIVIDE3_AUTO @@ -3639,7 +3639,7 @@ C_CLKOUT1_ACTUAL_FREQ - 25.00000 + 250.00000 C_CLKOUT2_ACTUAL_FREQ @@ -4352,7 +4352,7 @@ CLKOUT2_REQUESTED_OUT_FREQ - 25 + 250 CLKOUT2_REQUESTED_PHASE @@ -4688,7 +4688,7 @@ MMCM_CLKOUT1_DIVIDE - 40 + 4 MMCM_CLKOUT1_DUTY_CYCLE @@ -4997,7 +4997,7 @@ CLKOUT2_JITTER Clkout2 Jitter - 175.402 + 110.209 CLKOUT2_PHASE_ERROR diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v index 3bdbfa9..36879bf 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v @@ -54,7 +54,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__25.00000______0.000______50.0______175.402_____98.575 +// clk_out2__250.00000______0.000______50.0______110.209_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) @@ -134,7 +134,7 @@ wire clk_in2_clk_wiz_0; .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKOUT1_DIVIDE (40), + .CLKOUT1_DIVIDE (4), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v index 3dd5440..b6c1198 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Sun Apr 5 13:21:14 2026 +// Date : Sun Jun 14 16:06:02 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode funcsim -rename_top clk_wiz_0 -prefix // clk_wiz_0_ clk_wiz_0_sim_netlist.v @@ -111,7 +111,7 @@ module clk_wiz_0_clk_wiz_0_clk_wiz .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT0_USE_FINE_PS("FALSE"), - .CLKOUT1_DIVIDE(40), + .CLKOUT1_DIVIDE(4), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT1_USE_FINE_PS("FALSE"), diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl index ac9abb0..b5b7737 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Sun Apr 5 13:21:14 2026 +-- Date : Sun Jun 14 16:06:02 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode funcsim -rename_top clk_wiz_0 -prefix -- clk_wiz_0_ clk_wiz_0_sim_netlist.vhdl @@ -94,7 +94,7 @@ mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, - CLKOUT1_DIVIDE => 40, + CLKOUT1_DIVIDE => 4, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v index 22daff1..6894a73 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v @@ -2,7 +2,7 @@ // Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 -// Date : Sun Apr 5 13:21:14 2026 +// Date : Sun Jun 14 16:06:02 2026 // Host : arya running 64-bit EndeavourOS Linux // Command : write_verilog -force -mode synth_stub -rename_top clk_wiz_0 -prefix // clk_wiz_0_ clk_wiz_0_stub.v diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl index de31cff..ed80057 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl @@ -2,7 +2,7 @@ -- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 --- Date : Sun Apr 5 13:21:14 2026 +-- Date : Sun Jun 14 16:06:02 2026 -- Host : arya running 64-bit EndeavourOS Linux -- Command : write_vhdl -force -mode synth_stub -rename_top clk_wiz_0 -prefix -- clk_wiz_0_ clk_wiz_0_stub.vhdl diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo index 8e682f1..234c973 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/ip/clk_wiz_0/clk_wiz_0.veo @@ -53,7 +53,7 @@ // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) //---------------------------------------------------------------------------- // clk_out1__25.00000______0.000______50.0______175.402_____98.575 -// clk_out2__25.00000______0.000______50.0______175.402_____98.575 +// clk_out2__250.00000______0.000______50.0______110.209_____98.575 // //---------------------------------------------------------------------------- // Input Clock Freq (MHz) Input Jitter (UI) diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt index 77b73c8..9d772f7 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 +# Generated by export_simulation on Sun Jun 14 16:24:19 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh index 3f07532..76dd8a5 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 +# Script generated by Vivado on Sun Jun 14 16:24:19 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt index 77b73c8..9d772f7 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 +# Generated by export_simulation on Sun Jun 14 16:24:19 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh index 3663c88..b1d159e 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 +# Script generated by Vivado on Sun Jun 14 16:24:19 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt index 77b73c8..9d772f7 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 +# Generated by export_simulation on Sun Jun 14 16:24:19 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh index fe45b67..e824464 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 +# Script generated by Vivado on Sun Jun 14 16:24:19 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt index 77b73c8..9d772f7 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 +# Generated by export_simulation on Sun Jun 14 16:24:19 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh index 2de1372..e6ec085 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 +# Script generated by Vivado on Sun Jun 14 16:24:19 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt index 77b73c8..9d772f7 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 +# Generated by export_simulation on Sun Jun 14 16:24:19 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh index 206ce22..e254abe 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 +# Script generated by Vivado on Sun Jun 14 16:24:19 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt index 77b73c8..9d772f7 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt @@ -5,7 +5,7 @@ # run the exported script and how to fetch design source file details # from the file_info.txt file. # -# Generated by export_simulation on Sun Apr 05 13:27:06 EDT 2026 +# Generated by export_simulation on Sun Jun 14 16:24:19 EDT 2026 # ################################################################################ diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh index 3d4a5d5..c53a5fc 100755 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh @@ -2,7 +2,7 @@ #********************************************************************************************************** # Vivado (TM) v2025.2 (64-bit) # -# Script generated by Vivado on Sun Apr 05 13:27:06 EDT 2026 +# Script generated by Vivado on Sun Jun 14 16:24:19 EDT 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci index f9777fc..547d006 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci @@ -87,7 +87,7 @@ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -171,7 +171,7 @@ "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], - "MMCM_CLKOUT1_DIVIDE": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -247,7 +247,7 @@ "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT1_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], - "CLKOUT2_JITTER": [ { "value": "175.402", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "110.209", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT2_PHASE_ERROR": [ { "value": "98.575", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], @@ -339,14 +339,14 @@ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], - "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__25.00000______0.000______50.0______175.402_____98.575", "resolve_type": "generated", "usage": "all" } ], + "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__250.00000______0.000______50.0______110.209_____98.575", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ], "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "250", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -367,7 +367,7 @@ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT1_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_CLKOUT2_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_CLKOUT2_OUT_FREQ": [ { "value": "250.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], @@ -409,7 +409,7 @@ "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ], "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ], "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "40.000", "resolve_type": "generated", "format": "float", "usage": "all" } ], - "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "40", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -540,7 +540,7 @@ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ], - "C_DIVIDE2_AUTO": [ { "value": "1.0", "resolve_type": "generated", "usage": "all" } ], + "C_DIVIDE2_AUTO": [ { "value": "0.1", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE3_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE4_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], "C_DIVIDE5_AUTO": [ { "value": "0.025", "resolve_type": "generated", "usage": "all" } ], @@ -567,7 +567,7 @@ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], - "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ], + "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "250.00000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ], @@ -686,5 +686,5 @@ } } }, - "checksum": "eb66e59e" + "checksum": "3bd70495" } \ No newline at end of file diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v index 58bc133..638b67a 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v @@ -70,18 +70,18 @@ module Top( .clock (cpu_clk), .reset (reset), .io_execute (execute), - .io_debug_write (debug_write), - .io_debug_write_address (debug_write_address), - .io_debug_write_data (debug_write_data), - .io_debug_1 (debug_1), - .io_debug_2 (debug_2), + .io_flash (debug_write), + .io_flash_address (debug_write_address), + .io_flash_value (debug_write_data), +// .io_debug_1 (debug_1), +// .io_debug_2 (debug_2), .io_hsync (vgaHSync), .io_vsync (vgaVSync), .io_rgb (rgb), .io_blanking (blanking), - .io_vga_clk (clk_25), - .io_btns(btns) - + .io_vga_clk (clk_25) +// .io_btns (btns) +// .io_tx (RsTx) ); assign vgaRed = blanking ? 4'h0 : rgb[11:8]; diff --git a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr index b6531a3..ce21ec8 100644 --- a/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr +++ b/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr @@ -66,12 +66,12 @@