Additional Inquiry about Operating the Phase Noise Analyzer on Alpha 250-4

[YeojunPark]

Hi,

256K = 256 x 1024 = 262144 bits, this corresponds to 8192 samples of 32 bits.
Each ADC channel sample is on 16 bits (two extra dummy bits on top of the actual 14 bits) then 2 ADC channels are concatenated to get a 32 bits sample.

The BRAM that stores the data is configured as a "True Dual-Port Memory" so you can write data on one port while reading from the other port.

There is no effect on the jitter, the ADC sampling clock is provided by the clock generator and runs independently of the FPGA acquisition.

Originally posted by @tvanderbruggen in #628

As you mentioned, I understand that I need to replace the corresponding section (Lines 56–71) from alpha250/phase-noise-analyzer/config.yml into the config.yml file of alpha250-4 (specifically, alpha250-4/adc-bram/config.yml). However, I'm not sure what to do with the uploaded TCL script (alpha250/phase-noise-analyzer/block_design.tcl, Line 33). Could you clarify how I should handle it?

[tvanderbruggen]

Hi,

Removing line 33 in the block_design.tcl should be enough to disconnect the DDS from the DAC output.