Hi Matthias,
Now that my lvs overhaul of the gf180 pdk gets used in the sscs chipathon, I am realizing some of the shortcomings of my approach concerning the substrate.
First of all, my goal is to have LVS working on the foundry supplied cells. In there, you can find that isosub is used to separate regions connected to the iovss or core vss. For example on this corner cell: (isosub in salmon color)
When discussing with Prof. Pretl, he mentioned that this isosub feature is something desirable, as he has encountered a few instance where making this distinction between noisy digital logic and sensitive analog design was necessary.
Having to use isosub by itself is not a problem: one can simply use it as a normal layer. The problem comes in when we consider "simple" usecases, where one would like to omit having to add an isosub polygon matching the extent of the current cell. For example, for a basic inverter cell:
When I initially implemented this, I went about the problem like so: create a polygon matching the extent of the current cell, separate it according to the isosub polygons and generate the substrate polygon layer from it.
However, I now know that the sized operation (required for having a 1dbu space between isosub polygon and the default substrate) break the deep lvs in this case from #1813.
There thus seem to be two opposite things. Either I consider a single substrate net, breaking LVS for IO cells and advanced mixed designs, or I need to require everybody to always use isosub polygon under their designs (or always require flat LVS).
I think there will be people unhappy in either case.
Do you see a way out of this? Maybe a "sequestrate" option that does not require merging? Or a way to turn off automatic shorting if polygon edges touch each other (which would allow boolean operation usage)? Or maybe something else?
As always, thanks for the good work!
Hi Matthias,
Now that my lvs overhaul of the gf180 pdk gets used in the sscs chipathon, I am realizing some of the shortcomings of my approach concerning the substrate.
First of all, my goal is to have LVS working on the foundry supplied cells. In there, you can find that isosub is used to separate regions connected to the iovss or core vss. For example on this corner cell: (isosub in salmon color)
When discussing with Prof. Pretl, he mentioned that this isosub feature is something desirable, as he has encountered a few instance where making this distinction between noisy digital logic and sensitive analog design was necessary.
Having to use isosub by itself is not a problem: one can simply use it as a normal layer. The problem comes in when we consider "simple" usecases, where one would like to omit having to add an isosub polygon matching the extent of the current cell. For example, for a basic inverter cell:
When I initially implemented this, I went about the problem like so: create a polygon matching the extent of the current cell, separate it according to the isosub polygons and generate the substrate polygon layer from it.
However, I now know that the
sizedoperation (required for having a 1dbu space between isosub polygon and the default substrate) break the deep lvs in this case from #1813.There thus seem to be two opposite things. Either I consider a single substrate net, breaking LVS for IO cells and advanced mixed designs, or I need to require everybody to always use isosub polygon under their designs (or always require flat LVS).
I think there will be people unhappy in either case.
Do you see a way out of this? Maybe a "sequestrate" option that does not require merging? Or a way to turn off automatic shorting if polygon edges touch each other (which would allow boolean operation usage)? Or maybe something else?
As always, thanks for the good work!