feat: add support for risc-v

Author: lievenhey

app/perfregisterinfo.cpp

@@ -31,6 +31,8 @@ const int PerfRegisterInfo::s_numRegisters[PerfRegisterInfo::ARCH_INVALID][PerfR
     { 0,  0},
     { 0,  0},
     { 9, 17},
+	{ 0,  0},
+	{32, 32},
 };
 
 const int PerfRegisterInfo::s_wordWidth[PerfRegisterInfo::ARCH_INVALID][PerfRegisterInfo::s_numAbis] = {
@@ -41,6 +43,8 @@ const int PerfRegisterInfo::s_wordWidth[PerfRegisterInfo::ARCH_INVALID][PerfRegi
     {0, 0},
     {0, 0},
     {4, 8},
+	{0, 0},
+	{4, 8},
 };
 
 // Perf and Dwarf register layouts are the same for ARM and ARM64
@@ -59,6 +63,9 @@ static int x86_64[] = {0, 3, 2, 1, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23, 8
 static int mips[] = { 32,  1,  2,  3,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 16, 17,
                         18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31};
 
+static int riscv[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+	                    20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31};
+
 static int none[] = {0};
 
 const int *PerfRegisterInfo::s_perfToDwarf[PerfRegisterInfo::ARCH_INVALID][PerfRegisterInfo::s_numAbis] = {
@@ -70,14 +77,15 @@ const int *PerfRegisterInfo::s_perfToDwarf[PerfRegisterInfo::ARCH_INVALID][PerfR
     {none,    none   },
     {x86,     x86_64 },
     {mips,    mips   },
+	{riscv,   riscv  },
 };
 
 const int PerfRegisterInfo::s_perfIp[ARCH_INVALID] = {
-    15, 32, 0xffff, 0xffff, 0xffff, 0xffff, 8
+    15, 32, 0xffff, 0xffff, 0xffff, 0xffff, 8, 0xffff, 0
 };
 
 const int PerfRegisterInfo::s_perfSp[ARCH_INVALID] = {
-    13, 31, 0xffff, 0xffff, 0xffff, 0xffff, 7
+    13, 31, 0xffff, 0xffff, 0xffff, 0xffff, 7, 0xffff, 2
 };
 
 const int PerfRegisterInfo::s_dwarfLr[ARCH_INVALID][s_numAbis] = {
@@ -87,7 +95,9 @@ const int PerfRegisterInfo::s_dwarfLr[ARCH_INVALID][s_numAbis] = {
     {0xffff, 0xffff},
     {0xffff, 0xffff},
     {0xffff, 0xffff},
-    {0xffff, 0xffff}
+    {0xffff, 0xffff},
+    {0xffff, 0xffff},
+	{1, 1}
 };
 
 const int PerfRegisterInfo::s_dwarfIp[ARCH_INVALID][s_numAbis] = {
@@ -97,7 +107,9 @@ const int PerfRegisterInfo::s_dwarfIp[ARCH_INVALID][s_numAbis] = {
     {0xffff, 0xffff},
     {0xffff, 0xffff},
     {0xffff, 0xffff},
-    {8, 16}
+    {8, 16},
+	{0xffff, 0xffff},
+	{0, 0}
 };
 
 const int PerfRegisterInfo::s_dummyRegisters[ARCH_INVALID][2] = {
@@ -158,5 +170,8 @@ PerfRegisterInfo::Architecture PerfRegisterInfo::archByName(const QByteArray &na
     if (name.startsWith("mips"))
         return ARCH_MIPS;
 
+	if (name.startsWith("risc"))
+		return ARCH_RISCV;
+
     return ARCH_INVALID;
 }

app/perfregisterinfo.h

@@ -25,7 +25,8 @@
 class PerfRegisterInfo
 {
 public:
-    enum Architecture {
+    enum Architecture
+    {
         ARCH_ARM = 0,
         ARCH_AARCH64,
         ARCH_POWERPC,
@@ -34,18 +35,19 @@ class PerfRegisterInfo
         ARCH_SPARC,
         ARCH_X86,
         ARCH_MIPS,
+        ARCH_RISCV,
         ARCH_INVALID
     };
 
     static const int s_numAbis = 2; // maybe more for some archs?
 
-    static Architecture archByName(const QByteArray &name);
+    static Architecture archByName(const QByteArray& name);
     static const int s_numRegisters[ARCH_INVALID][s_numAbis];
     static const int s_wordWidth[ARCH_INVALID][s_numAbis];
 
     // Translation table for converting perf register layout to dwarf register layout
     // This is specific to ABI as the different ABIs may have different numbers of registers.
-    static const int *s_perfToDwarf[ARCH_INVALID][s_numAbis];
+    static const int* s_perfToDwarf[ARCH_INVALID][s_numAbis];
 
     // location of IP register or equivalent in perf register layout for each arch/abi
     // This is not specific to ABI as perf makes sure IP is always in the same spot