GammaCPU/GammaALU.vhdl at main · IntegralPilot/GammaCPU · GitHub

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-- file: GammaALU.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity GammaALU is
    Port (
        clk          : in std_logic;
        left_operand : in std_logic_vector(31 downto 0);  -- Left operand (value to be shifted/operated on)
        right_operand: in std_logic_vector(31 downto 0);  -- Right operand (shift amount or second value)
        op           : in unsigned(15 downto 0);
        result       : out std_logic_vector(31 downto 0);
        reset        : in std_logic;
        enable       : in std_logic
    );
end GammaALU;

architecture Behavioral of GammaALU is
    -- Signal for shift amount (lower 5 bits of right_operand)
    signal shift_amount : integer range 0 to 31;
begin

    shift_amount <= to_integer(unsigned(right_operand(4 downto 0)));

    process(clk, reset)
    begin
        if reset = '1' then
            result <= (others => '0');
        elsif rising_edge(clk) and enable = '1' then
            case to_integer(op) is
                -- Arithmetic
                when 0 =>  -- ADD
                    result <= std_logic_vector(signed(left_operand) + signed(right_operand));
                when 1 =>  -- SUB
                    result <= std_logic_vector(signed(left_operand) - signed(right_operand));
                when 2 =>  -- MUL
                    result <= std_logic_vector(resize(signed(left_operand) * signed(right_operand), 32));
                when 3 =>  -- DIV_S
                    if right_operand /= std_logic_vector(to_signed(0, 32)) then
                        result <= std_logic_vector(signed(left_operand) / signed(right_operand));
                    else
                        result <= (others => '0');
                    end if;

                -- Comparison
                when 4 => -- eq
                    result <= std_logic_vector(to_signed(boolean'pos(left_operand = right_operand), 32));
                when 5 => -- ne
                    result <= std_logic_vector(to_signed(boolean'pos(left_operand /= right_operand), 32));
                when 6 => -- gt_s
                    result <= std_logic_vector(to_signed(boolean'pos(signed(left_operand) > signed(right_operand)), 32));
                when 7 => -- lt_s
                    result <= std_logic_vector(to_signed(boolean'pos(signed(left_operand) < signed(right_operand)), 32));
                when 8 => -- ge_s
                    result <= std_logic_vector(to_signed(boolean'pos(signed(left_operand) >= signed(right_operand)), 32));
                when 9 => -- le_s
                    result <= std_logic_vector(to_signed(boolean'pos(signed(left_operand) <= signed(right_operand)), 32));
                when 11 => -- gt_u
                    result <= std_logic_vector(to_signed(boolean'pos(unsigned(left_operand) > unsigned(right_operand)), 32));
                when 12 => -- lt_u
                    result <= std_logic_vector(to_signed(boolean'pos(unsigned(left_operand) < unsigned(right_operand)), 32));
                when 13 => -- ge_u
                    result <= std_logic_vector(to_signed(boolean'pos(unsigned(left_operand) >= unsigned(right_operand)), 32));
                when 14 => -- le_u
                    result <= std_logic_vector(to_signed(boolean'pos(unsigned(left_operand) <= unsigned(right_operand)), 32));

                when 15 => -- div_u
                    if right_operand /= std_logic_vector(to_unsigned(0, 32)) then
                        result <= std_logic_vector(unsigned(left_operand) / unsigned(right_operand));
                    else
                        result <= (others => '0');
                    end if;
                when 16 => -- rem_u
                    if right_operand /= std_logic_vector(to_unsigned(0, 32)) then
                        result <= std_logic_vector(unsigned(left_operand) rem unsigned(right_operand));
                    else
                        result <= (others => '0');
                    end if;
                when 17 => -- rem_s
                    if right_operand /= std_logic_vector(to_signed(0, 32)) then
                        result <= std_logic_vector(signed(left_operand) rem signed(right_operand));
                    else
                        result <= (others => '0');
                    end if;

                -- i32 binops
                -- Bitwise
                when 18 =>  -- AND
                    result <= left_operand and right_operand;
                when 19 =>  -- OR
                    result <= left_operand or right_operand;
                when 20 =>  -- XOR
                    result <= left_operand xor right_operand;

                -- Shift
                when 21 =>  -- SHL
                    result <= std_logic_vector(shift_left(unsigned(left_operand), shift_amount));
                when 22 =>  -- SHR_S (Arithmetic)
                    result <= std_logic_vector(shift_right(signed(left_operand), shift_amount));
                when 23 =>  -- SHR_U (Logical)
                    result <= std_logic_vector(shift_right(unsigned(left_operand), shift_amount));

                -- Rotate
                when 24 =>  -- ROTL
                    result <= std_logic_vector(rotate_left(unsigned(left_operand), shift_amount));
                when 25 =>  -- ROTR
                    result <= std_logic_vector(rotate_right(unsigned(left_operand), shift_amount));

                when others =>
                    result <= (others => '0');
            end case;
        end if;
    end process;
end Behavioral;