diff --git a/.vscode/launch.json b/.vscode/launch.json
index d2c158491..b9d6ada27 100644
--- a/.vscode/launch.json
+++ b/.vscode/launch.json
@@ -251,6 +251,37 @@
 				]
 			}
 		},
+		{
+			"cwd": "${workspaceFolder}",
+			"executable": "${command:cmake.buildDirectory}/G4SPITESTING.elf",
+			"name": "G4SPITESTING",
+			"request": "launch",
+			"type": "cortex-debug",
+			"servertype": "openocd",
+			"configFiles": [
+				"interface/stlink.cfg",
+				"target/stm32g4x.cfg"
+			],
+			"searchDir": [],
+			"preLaunchTask": "CMake: configure and build G4SPITESTING",
+			"showDevDebugOutput": "raw",
+			"svdPath": "${workspaceFolder}/Lib/Vendor/CMSIS_5/SVD/STM32G474.svd",
+			"swoConfig": {
+				"enabled": true,
+				"cpuFrequency": 170000000,
+				"swoFrequency": 2000000,
+				"source": "probe",
+				"decoders": [
+					{
+						"type": "console",
+						"label": "ITM",
+						"showOnStartup": true,
+						"port": 0,
+						"encoding": "ascii"
+					}
+				]
+			}
+		},
 		{
 			"cwd": "${workspaceFolder}",
 			"executable": "${command:cmake.buildDirectory}/G4ADCTESTING.elf",
diff --git a/.vscode/tasks.json b/.vscode/tasks.json
index da3d7ad1d..05a0e1d97 100644
--- a/.vscode/tasks.json
+++ b/.vscode/tasks.json
@@ -63,6 +63,15 @@
 			],
 			"command": "cmake --build --preset ${command:cmake.activeBuildPresetName} --target G4CANTESTING"
 		},
+		{
+			"label": "CMake: configure and build G4SPITESTING",
+			"type": "shell",
+			"dependsOrder": "sequence",
+			"dependsOn": [
+				"CMake: configure"
+			],
+			"command": "cmake --build --preset ${command:cmake.activeBuildPresetName} --target G4SPITESTING"
+		},
 		{
 			"label": "CMake: configure and build G4BLINKY",
 			"type": "shell",
diff --git a/CMakeLists.txt b/CMakeLists.txt
index ef62927ea..03836d08f 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -41,6 +41,7 @@ include("${lib_path}/GlobalShare/common.cmake")
 include("${lib_path}/Utils/Logomatic/logomatic.cmake")
 include("${lib_path}/Utils/CircularBuffer/circular-buffer-lib.cmake")
 include("${lib_path}/cmake/gr-lib.cmake")
+include("${lib_path}/FancyLayers-RENAME/SPI/spi.cmake")
 include("${lib_path}/Utils/BitManipulations/bit-utils.cmake")
 
 # Peripherals
@@ -68,8 +69,9 @@ add_gr_project(STM32G474xE CCU)
 add_gr_project(STM32G474xE AnalogCalibration)
 
 # Development
-add_gr_project(STM32G474xE G4ADCTESTING)
 add_gr_project(STM32G474xE G4PERTESTING)
+add_gr_project(STM32G474xE G4SPITESTING)
+add_gr_project(STM32G474xE G4ADCTESTING)
 add_gr_project(STM32G474xE G4CANTESTING)
 
 # BLINKY Demos
diff --git a/G4SPITESTING/CMakeLists.txt b/G4SPITESTING/CMakeLists.txt
new file mode 100644
index 000000000..d965f1c66
--- /dev/null
+++ b/G4SPITESTING/CMakeLists.txt
@@ -0,0 +1,39 @@
+cmake_minimum_required(VERSION 3.25)
+
+# Setup compiler settings
+set(CMAKE_C_STANDARD 11)
+set(CMAKE_C_STANDARD_REQUIRED ON)
+set(CMAKE_C_EXTENSIONS ON)
+
+# Define the build type
+if(NOT CMAKE_BUILD_TYPE)
+	set(CMAKE_BUILD_TYPE "Debug")
+endif()
+
+# Enable compile command to ease indexing with e.g. clangd
+set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE)
+
+# Enable CMake support for ASM and C languages
+enable_language(
+	C
+	ASM
+)
+
+# Core project settings
+project(${CMAKE_PROJECT_NAME})
+
+# what, does in fact not get the filename of somthing but rather the name of the project from the path
+get_filename_component(PROJECT_NAME ${CMAKE_CURRENT_SOURCE_DIR} NAME)
+
+add_library(${PROJECT_NAME}_USER_CODE INTERFACE)
+target_sources(
+	${PROJECT_NAME}_USER_CODE
+	INTERFACE
+		Core/Src/main.c
+		Core/Src/stm32g4xx_hal_msp.c
+		Core/Src/stm32g4xx_it.c
+)
+
+target_link_libraries(${PROJECT_NAME}_USER_CODE INTERFACE SPI_Lib)
+
+target_include_directories(${PROJECT_NAME}_USER_CODE INTERFACE Core/Inc)
diff --git a/G4SPITESTING/Core/Inc/main.h b/G4SPITESTING/Core/Inc/main.h
new file mode 100644
index 000000000..9ff00d051
--- /dev/null
+++ b/G4SPITESTING/Core/Inc/main.h
@@ -0,0 +1,116 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file           : main.h
+ * @brief          : Header for main.c file.
+ *                   This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+#include "stm32g4xx_ll_adc.h"
+#include "stm32g4xx_ll_bus.h"
+#include "stm32g4xx_ll_cortex.h"
+#include "stm32g4xx_ll_crs.h"
+#include "stm32g4xx_ll_dma.h"
+#include "stm32g4xx_ll_exti.h"
+#include "stm32g4xx_ll_gpio.h"
+#include "stm32g4xx_ll_i2c.h"
+#include "stm32g4xx_ll_lpuart.h"
+#include "stm32g4xx_ll_pwr.h"
+#include "stm32g4xx_ll_rcc.h"
+#include "stm32g4xx_ll_spi.h"
+#include "stm32g4xx_ll_system.h"
+#include "stm32g4xx_ll_tim.h"
+#include "stm32g4xx_ll_usart.h"
+#include "stm32g4xx_ll_utils.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include <stdio.h>
+#include <stdlib.h>
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define BSPD_SIGNAL_Pin LL_GPIO_PIN_1
+#define BSPD_SIGNAL_GPIO_Port GPIOC
+#define APPS1_SIGNAL_Pin LL_GPIO_PIN_2
+#define APPS1_SIGNAL_GPIO_Port GPIOC
+#define APPS2_SIGNAL_Pin LL_GPIO_PIN_3
+#define APPS2_SIGNAL_GPIO_Port GPIOC
+#define BLINKY_Pin LL_GPIO_PIN_5
+#define BLINKY_GPIO_Port GPIOA
+#define IMD_SENSE_Pin LL_GPIO_PIN_6
+#define IMD_SENSE_GPIO_Port GPIOA
+#define AMS_SENSE_Pin LL_GPIO_PIN_7
+#define AMS_SENSE_GPIO_Port GPIOA
+#define BRAKE_F_SIGNAL_Pin LL_GPIO_PIN_0
+#define BRAKE_F_SIGNAL_GPIO_Port GPIOB
+#define BRAKE_R_SIGNAL_Pin LL_GPIO_PIN_1
+#define BRAKE_R_SIGNAL_GPIO_Port GPIOB
+#define LED_TEST_Pin LL_GPIO_PIN_11
+#define LED_TEST_GPIO_Port GPIOB
+#define AUX_SIGNAL_Pin LL_GPIO_PIN_14
+#define AUX_SIGNAL_GPIO_Port GPIOB
+#define STEERING_ANGLE_Pin LL_GPIO_PIN_15
+#define STEERING_ANGLE_GPIO_Port GPIOB
+#define BRAKE_LIGHT_Pin LL_GPIO_PIN_4
+#define BRAKE_LIGHT_GPIO_Port GPIOB
+#define TSSI_G_CONTROL_Pin LL_GPIO_PIN_5
+#define TSSI_G_CONTROL_GPIO_Port GPIOB
+#define AUX_CONTROL_Pin LL_GPIO_PIN_8
+#define AUX_CONTROL_GPIO_Port GPIOB
+#define SOFTWARE_OK_CONTROL_Pin LL_GPIO_PIN_9
+#define SOFTWARE_OK_CONTROL_GPIO_Port GPIOB
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/G4SPITESTING/Core/Inc/stm32_assert.h b/G4SPITESTING/Core/Inc/stm32_assert.h
new file mode 100644
index 000000000..92460620f
--- /dev/null
+++ b/G4SPITESTING/Core/Inc/stm32_assert.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    stm32_assert.h
+ * @author  MCD Application Team
+ * @brief   STM32 assert file.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32_ASSERT_H
+#define __STM32_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Includes ------------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief  The assert_param macro is used for function's parameters check.
+ * @param  expr: If expr is false, it calls assert_failed function
+ *         which reports the name of the source file and the source
+ *         line number of the call that failed.
+ *         If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32_ASSERT_H */
diff --git a/G4SPITESTING/Core/Inc/stm32g4xx_hal_conf.h b/G4SPITESTING/Core/Inc/stm32g4xx_hal_conf.h
new file mode 100644
index 000000000..3e1fcb018
--- /dev/null
+++ b/G4SPITESTING/Core/Inc/stm32g4xx_hal_conf.h
@@ -0,0 +1,390 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    stm32g4xx_hal_conf.h
+ * @author  MCD Application Team
+ * @brief   HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_CONF_H
+#define STM32G4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+
+#define HAL_MODULE_ENABLED
+
+/*#define HAL_ADC_MODULE_ENABLED   */
+/*#define HAL_COMP_MODULE_ENABLED   */
+/*#define HAL_CORDIC_MODULE_ENABLED   */
+#define HAL_CRC_MODULE_ENABLED
+/*#define HAL_CRYP_MODULE_ENABLED   */
+/*#define HAL_DAC_MODULE_ENABLED   */
+#define HAL_FDCAN_MODULE_ENABLED
+/*#define HAL_FMAC_MODULE_ENABLED   */
+/*#define HAL_HRTIM_MODULE_ENABLED   */
+/*#define HAL_IRDA_MODULE_ENABLED   */
+/*#define HAL_IWDG_MODULE_ENABLED   */
+/*#define HAL_I2C_MODULE_ENABLED   */
+/*#define HAL_I2S_MODULE_ENABLED   */
+/*#define HAL_LPTIM_MODULE_ENABLED   */
+/*#define HAL_NAND_MODULE_ENABLED   */
+/*#define HAL_NOR_MODULE_ENABLED   */
+/*#define HAL_OPAMP_MODULE_ENABLED   */
+/*#define HAL_PCD_MODULE_ENABLED   */
+/*#define HAL_QSPI_MODULE_ENABLED   */
+/*#define HAL_RNG_MODULE_ENABLED   */
+/*#define HAL_RTC_MODULE_ENABLED   */
+/*#define HAL_SAI_MODULE_ENABLED   */
+/*#define HAL_SMARTCARD_MODULE_ENABLED   */
+/*#define HAL_SMBUS_MODULE_ENABLED   */
+/*#define HAL_SPI_MODULE_ENABLED   */
+/*#define HAL_SRAM_MODULE_ENABLED   */
+/*#define HAL_TIM_MODULE_ENABLED   */
+/*#define HAL_UART_MODULE_ENABLED   */
+/*#define HAL_USART_MODULE_ENABLED   */
+/*#define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection
+ * ############################## */
+/**
+ * @brief This is the list of modules where register callback can be used
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U
+#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U
+#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U
+#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0U
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
+
+/* ########################## Oscillator Values adaptation
+ * ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your
+ * application. This value is used by the RCC HAL module to compute the system
+ * frequency (when HSE is used as system clock source, directly or through the
+ * PLL).
+ */
+#if !defined(HSE_VALUE)
+#define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz */
+#endif			       /* HSE_VALUE */
+
+#if !defined(HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
+#endif				    /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ *        This value is used by the RCC HAL module to compute the system
+ * frequency (when HSI is used as system clock source, directly or through the
+ * PLL).
+ */
+#if !defined(HSI_VALUE)
+#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif			       /* HSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
+ *        This internal oscillator is mainly dedicated to provide a high
+ * precision clock to the USB peripheral by means of a special Clock Recovery
+ * System (CRS) circuitry. When the CRS is not used, the HSI48 RC oscillator
+ * runs on it default frequency which is subject to manufacturing process
+ * variations.
+ */
+#if !defined(HSI48_VALUE)
+#define HSI48_VALUE                                                                                                                                                                                    \
+	(48000000UL) /*!< Value of the Internal High Speed oscillator for USB                                                                                                                          \
+			FS/RNG in Hz. The real value my vary depending on                                                                                                                              \
+			manufacturing process variations.*/
+#endif		     /* HSI48_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined(LSI_VALUE)
+/*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations in voltage and
+temperature.*/
+#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
+#endif			    /* LSI_VALUE */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ *        This value is used by the UART, RTC HAL module to compute the system
+ * frequency
+ */
+#if !defined(LSE_VALUE)
+#define LSE_VALUE (32768UL) /*!< Value of the External Low Speed oscillator in Hz */
+#endif			    /* LSE_VALUE */
+
+#if !defined(LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
+#endif				     /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S and SAI peripherals
+ *        This value is used by the I2S and SAI HAL modules to compute the I2S
+ * and SAI clock source frequency, this source is inserted directly through
+ * I2S_CKIN pad.
+ */
+#if !defined(EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE (12288000UL) /*!< Value of the External oscillator in Hz*/
+#endif					  /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+
+#define VDD_VALUE (3300UL)	 /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default)  */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 0U
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ *        HAL drivers code
+ */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC 0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+#include "stm32g4xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g4xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+#include "stm32g4xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32g4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32g4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32g4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+#include "stm32g4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32g4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32g4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief  The assert_param macro is used for function's parameters check.
+ * @param  expr: If expr is false, it calls assert_failed function
+ *         which reports the name of the source file and the source
+ *         line number of the call that failed.
+ *         If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_CONF_H */
diff --git a/G4SPITESTING/Core/Inc/stm32g4xx_it.h b/G4SPITESTING/Core/Inc/stm32g4xx_it.h
new file mode 100644
index 000000000..b6c3b2f72
--- /dev/null
+++ b/G4SPITESTING/Core/Inc/stm32g4xx_it.h
@@ -0,0 +1,67 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    stm32g4xx_it.h
+ * @brief   This file contains the headers of the interrupt handlers.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32G4xx_IT_H
+#define __STM32G4xx_IT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void FDCAN2_IT0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32G4xx_IT_H */
diff --git a/G4SPITESTING/Core/Src/main.c b/G4SPITESTING/Core/Src/main.c
new file mode 100644
index 000000000..dbc073646
--- /dev/null
+++ b/G4SPITESTING/Core/Src/main.c
@@ -0,0 +1,334 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file           : main.c
+ * @brief          : Main program body
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+#include <string.h>
+
+#include "Logomatic.h"
+#include "spi.h"
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+/* USER CODE BEGIN PV */
+LogomaticConfig logomaticConfig = {.clock_source = LOGOMATIC_PCLK1,
+				   .bus = LOGOMATIC_BUS,
+				   .gpio_port = LOGOMATIC_GPIOA,
+				   .gpio_pin_rx_tx_mask = LL_GPIO_PIN_2 | LL_GPIO_PIN_3,
+				   .baud_rate = 115200,
+				   .data_width = LOGOMATIC_DATAWIDTH_8B,
+				   .stop_bits = LOGOMATIC_STOPBITS_1,
+				   .parity = LOGOMATIC_PARITY_NONE,
+				   .transfer_direction = LOGOMATIC_DIRECTION_TX,
+				   .hardware_flow_control = LOGOMATIC_HWCONTROL_NONE,
+				   .prescaler = LOGOMATIC_PRESCALER_DIV1,
+				   .tx_fifo_threshold = LOGOMATIC_FIFOTHRESHOLD_1_8,
+				   .rx_fifo_threshold = LOGOMATIC_FIFOTHRESHOLD_1_8};
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+ * @brief  The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+
+	/* USER CODE BEGIN 1 */
+	static GR_SPI_Handler ex_handler;
+	static LL_SPI_InitTypeDef ex_config;
+	static GR_SPI_Pins ex_pins;
+	/*HAL_OSPI_HandleTypeDef hospi;
+	HAL_StatusTypeDef status;*/
+
+	/* USER CODE END 1 */
+
+	/* MCU
+	 * Configuration--------------------------------------------------------*/
+
+	/* Reset of all peripherals, Initializes the Flash interface and the
+	 * Systick. */
+	HAL_Init();
+
+	/* USER CODE BEGIN Init */
+	Setup_Logomatic(&logomaticConfig);
+	/* USER CODE END Init */
+
+	/* Configure the system clock */
+	SystemClock_Config();
+
+	/* USER CODE BEGIN SysInit */
+	LOGOMATIC("Booted!\n");
+	/* USER CODE END SysInit */
+
+	/* Initialize all configured peripherals */
+	/* USER CODE BEGIN 2 */
+	LL_mDelay(1000); // Wait for peripherals to stabilize
+	LOGOMATIC("Booted!\n");
+
+	ex_config.TransferDirection = LL_SPI_FULL_DUPLEX;
+	ex_config.Mode = LL_SPI_MODE_MASTER;
+	ex_config.DataWidth = LL_SPI_DATAWIDTH_8BIT;
+	ex_config.ClockPolarity = LL_SPI_POLARITY_LOW;
+	ex_config.ClockPhase = LL_SPI_PHASE_1EDGE;
+	ex_config.NSS = LL_SPI_NSS_SOFT;
+	ex_config.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+	ex_config.BitOrder = LL_SPI_LSB_FIRST;
+	ex_config.CRCCalculation = LL_SPI_CRCCALCULATION_ENABLE;
+	ex_config.CRCPoly = 0x1D;
+
+	ex_pins.SPIx = SPI3;
+	ex_pins.GPIOx = (GPIO_TypeDef **)(malloc(4 * sizeof(GPIO_TypeDef *)));
+	// All pins are in the A clock port
+	for (int i = 0; i < 3; i++) {
+		*(ex_pins.GPIOx + i) = GPIOC;
+	}
+	ex_pins.GPIOx[3] = GPIOA;
+	ex_pins.num_pins = 4;
+	ex_pins.pin_nums = (uint32_t *)malloc(4 * sizeof(int));
+	ex_pins.pin_nums[0] = LL_GPIO_PIN_12; // COPI
+	ex_pins.pin_nums[1] = LL_GPIO_PIN_11; // CIPO
+	ex_pins.pin_nums[2] = LL_GPIO_PIN_10; // SCK
+	ex_pins.pin_nums[3] = LL_GPIO_PIN_4;  // NSS
+	ex_pins.alternate_function_number = 6;
+
+	GR_SPI_Initialize(&ex_handler, &ex_config, &ex_pins);
+
+	// LOGOMATIC("-= SPI + GPIO Init Verification (Measured | Expected) =-\n");
+	// /* ---------------- SPI ---------------- */
+	// LOGOMATIC("TransferDirection = %lu | %lu\n", LL_SPI_GetTransferDirection(ex_pins.SPIx), ex_config.TransferDirection);
+	// LOGOMATIC("Mode              = %lu | %lu\n", LL_SPI_GetMode(ex_pins.SPIx), ex_config.Mode);
+	// LOGOMATIC("DataWidth         = %lu | %lu\n", LL_SPI_GetDataWidth(ex_pins.SPIx), ex_config.DataWidth);
+	// LOGOMATIC("ClockPolarity     = %lu | %lu\n", LL_SPI_GetClockPolarity(ex_pins.SPIx), ex_config.ClockPolarity);
+	// LOGOMATIC("ClockPhase        = %lu | %lu\n", LL_SPI_GetClockPhase(ex_pins.SPIx), ex_config.ClockPhase);
+	// LOGOMATIC("NSS               = %lu | %lu\n", LL_SPI_GetNSSMode(ex_pins.SPIx), ex_config.NSS);
+	// LOGOMATIC("BaudRate          = %lu | %lu\n", LL_SPI_GetBaudRatePrescaler(ex_pins.SPIx), ex_config.BaudRate);
+	// LOGOMATIC("BitOrder          = %lu | %lu\n", LL_SPI_GetTransferBitOrder(ex_pins.SPIx), ex_config.BitOrder);
+	// LOGOMATIC("CRC Enable        = %lu | 1\n", LL_SPI_IsEnabledCRC(ex_pins.SPIx));
+	// LOGOMATIC("CRC Polynomial    = 0x%lx | 0x%lx\n", ex_pins.SPIx->CRCPR, ex_config.CRCPoly);
+	// LOGOMATIC("SPI Enable        = %lu | 1\n", LL_SPI_IsEnabled(ex_pins.SPIx));
+
+	// uint32_t spi_clk_en = 0;
+	// if (ex_handler.pins->SPIx == SPI1) {
+	// 	spi_clk_en = LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1);
+	// } else if (ex_handler.pins->SPIx == SPI2) {
+	// 	spi_clk_en = LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2);
+	// } else if (ex_handler.pins->SPIx == SPI3) {
+	// 	spi_clk_en = LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI3);
+	// }
+	// LOGOMATIC("SPI Clock Enable  = %lu | 1\n", spi_clk_en);
+	// /* ---------------- GPIO CLOCKS ---------------- */
+	// for (int i = 0; i < ex_pins.num_pins; i++) {
+	// 	uint32_t clk_en = 0;
+
+	// 	if (ex_pins.GPIOx[i] == GPIOA) {
+	// 		clk_en = LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA);
+	// 	} else if (ex_pins.GPIOx[i] == GPIOB) {
+	// 		clk_en = LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB);
+	// 	} else if (ex_pins.GPIOx[i] == GPIOC) {
+	// 		clk_en = LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC);
+	// 	} else if (ex_pins.GPIOx[i] == GPIOD) {
+	// 		clk_en = LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOD);
+	// 	} else if (ex_pins.GPIOx[i] == GPIOE) {
+	// 		clk_en = LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE);
+	// 	} else if (ex_pins.GPIOx[i] == GPIOF) {
+	// 		clk_en = LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOF);
+	// 	} else if (ex_pins.GPIOx[i] == GPIOG) {
+	// 		clk_en = LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOG);
+	// 	}
+
+	// 	LOGOMATIC("GPIO Clock [%p] = %lu | 1\n", (void *)ex_pins.GPIOx[i], clk_en);
+	// }
+	// /* ---------------- GPIO MODE + AF ---------------- */
+	// for (int i = 0; i < ex_pins.num_pins; i++) {
+	// 	uint32_t pin = ex_pins.pin_nums[i];
+
+	// 	LOGOMATIC("GPIO[%d] Mode     = %lu | %lu\n", pin, LL_GPIO_GetPinMode(ex_pins.GPIOx[i], pin), LL_GPIO_MODE_ALTERNATE);
+
+	// 	LOGOMATIC("GPIO[%d] AF       = %lu | %lu\n", pin, (ex_pins.pin_nums[i] < LL_GPIO_PIN_8) ? LL_GPIO_GetAFPin_0_7(ex_pins.GPIOx[i], pin) : LL_GPIO_GetAFPin_8_15(ex_pins.GPIOx[i], pin),
+	// 		  ex_pins.alternate_function_number);
+	// }
+	// LOGOMATIC("-= End Verification =-\n");
+
+	LOGOMATIC("Starting message transaction...\n");
+	/*
+	uint8_t data = 0x00;
+	LL_GPIO_SetOutputPin(GPIOA, LL_GPIO_PIN_4); // NSS low
+
+	for(uint8_t i = 1; i < 128; i++) {
+		LL_SPI_TransmitData8(SPI3, i);
+		while (LL_SPI_IsActiveFlag_BSY(SPI3));
+		data = LL_SPI_ReceiveData8(SPI3);
+		LOGOMATIC("data: %d\n", data);
+	}
+
+	LL_GPIO_SetOutputPin(GPIOA, LL_GPIO_PIN_4);   // NSS high
+	*/
+	GR_SPI_Message msg;
+	msg.data = (uint8_t *)malloc(32 * sizeof(uint8_t));
+	msg.size = 32;
+
+	for (int i = 0; i < msg.size; i++) {
+		msg.data[i] = 'A' + i;
+	}
+
+	GR_SPI_Send(&ex_handler, &msg);
+
+	LOGOMATIC("Sent message, now receiving...\n");
+
+	for (int i = 0; i < msg.size; i++) {
+		msg.data[i] = '#';
+	}
+
+	while (GR_SPI_IsRxEmpty(&ex_handler)) {}
+
+	GR_SPI_Receive(&ex_handler, &msg);
+
+	char str[33];
+	memcpy(str, msg.data, msg.size);
+	str[32] = '\0';
+
+	LOGOMATIC("Received: %s\n", str);
+
+	free(msg.data);
+	GR_SPI_Close(&ex_handler);
+	/* USER CODE END 2 */
+
+	/* Infinite loop */
+	/* USER CODE BEGIN WHILE */
+	while (1) {
+		/* USER CODE END WHILE */
+
+		// BLINKY
+		HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_SET);
+		HAL_Delay(1000);
+		HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, GPIO_PIN_RESET);
+		HAL_Delay(1000);
+		LOGOMATIC("Blinking!\n");
+
+		/* USER CODE BEGIN 3 */
+	}
+}
+
+/* void test_spi_initialize(GR_SPI_Handler* handle, LL_SPI_InitTypeDef* config,
+GR_SPI_Pins* pin_config){ if(GR_SPI_Initialize(&handle, &config, &pin_config)
+} */
+
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+	LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
+	while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_4) {}
+	LL_PWR_EnableRange1BoostMode();
+	LL_RCC_HSI_Enable();
+	/* Wait till HSI is ready */
+	while (LL_RCC_HSI_IsReady() != 1) {}
+
+	LL_RCC_HSI_SetCalibTrimming(64);
+	LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLLM_DIV_4, 85, LL_RCC_PLLR_DIV_2);
+	LL_RCC_PLL_EnableDomain_SYS();
+	LL_RCC_PLL_Enable();
+	/* Wait till PLL is ready */
+	while (LL_RCC_PLL_IsReady() != 1) {}
+
+	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
+	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
+	/* Wait till System clock is ready */
+	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {}
+
+	/* Insure 1us transition state at intermediate medium speed clock*/
+	for (__IO uint32_t i = (170 >> 1); i != 0; i--)
+		;
+
+	/* Set AHB prescaler*/
+	LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
+	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+	LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+	LL_SetSystemCoreClock(170000000);
+
+	/* Update the time base */
+	if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
+		// status = ERROR;
+		Error_Handler();
+	}
+}
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+ * @brief  This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+	/* USER CODE BEGIN Error_Handler_Debug */
+	/* User can add his own implementation to report the HAL error return
+	 * state */
+	__disable_irq();
+	while (1) {}
+}
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief  Reports the name of the source file and the source line number
+ *         where the assert_param error has occurred.
+ * @param  file: pointer to the source file name
+ * @param  line: assert_param error line source number
+ * @retval None
+ */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+	/* USER CODE BEGIN 6 */
+	/* User can add his own implementation to report the file name and line
+	   number, ex: printf("Wrong parameters value: file %s on line %d\r\n",
+	   file, line) */
+	/* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/G4SPITESTING/Core/Src/stm32g4xx_hal_msp.c b/G4SPITESTING/Core/Src/stm32g4xx_hal_msp.c
new file mode 100644
index 000000000..69189ef4e
--- /dev/null
+++ b/G4SPITESTING/Core/Src/stm32g4xx_hal_msp.c
@@ -0,0 +1,86 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file         stm32g4xx_hal_msp.c
+ * @brief        This file provides code for the MSP Initialization
+ *               and de-Initialization codes.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+
+	/* USER CODE BEGIN MspInit 0 */
+
+	/* USER CODE END MspInit 0 */
+
+	__HAL_RCC_SYSCFG_CLK_ENABLE();
+	__HAL_RCC_PWR_CLK_ENABLE();
+
+	/* System interrupt init*/
+
+	/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
+	 */
+	HAL_PWREx_DisableUCPDDeadBattery();
+
+	/* USER CODE BEGIN MspInit 1 */
+
+	/* USER CODE END MspInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/G4SPITESTING/Core/Src/stm32g4xx_it.c b/G4SPITESTING/Core/Src/stm32g4xx_it.c
new file mode 100644
index 000000000..9549141b0
--- /dev/null
+++ b/G4SPITESTING/Core/Src/stm32g4xx_it.c
@@ -0,0 +1,198 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file    stm32g4xx_it.c
+ * @brief   Interrupt Service Routines.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2024 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_it.h"
+
+#include "main.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+	/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+	/* USER CODE END NonMaskableInt_IRQn 0 */
+	/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+	while (1) {}
+	/* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+	/* USER CODE BEGIN HardFault_IRQn 0 */
+
+	/* USER CODE END HardFault_IRQn 0 */
+	while (1) {
+		/* USER CODE BEGIN W1_HardFault_IRQn 0 */
+		/* USER CODE END W1_HardFault_IRQn 0 */
+	}
+}
+
+/**
+ * @brief This function handles Memory management fault.
+ */
+void MemManage_Handler(void)
+{
+	/* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+	/* USER CODE END MemoryManagement_IRQn 0 */
+	while (1) {
+		/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+		/* USER CODE END W1_MemoryManagement_IRQn 0 */
+	}
+}
+
+/**
+ * @brief This function handles Prefetch fault, memory access fault.
+ */
+void BusFault_Handler(void)
+{
+	/* USER CODE BEGIN BusFault_IRQn 0 */
+
+	/* USER CODE END BusFault_IRQn 0 */
+	while (1) {
+		/* USER CODE BEGIN W1_BusFault_IRQn 0 */
+		/* USER CODE END W1_BusFault_IRQn 0 */
+	}
+}
+
+/**
+ * @brief This function handles Undefined instruction or illegal state.
+ */
+void UsageFault_Handler(void)
+{
+	/* USER CODE BEGIN UsageFault_IRQn 0 */
+
+	/* USER CODE END UsageFault_IRQn 0 */
+	while (1) {
+		/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+		/* USER CODE END W1_UsageFault_IRQn 0 */
+	}
+}
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+	/* USER CODE BEGIN SVCall_IRQn 0 */
+
+	/* USER CODE END SVCall_IRQn 0 */
+	/* USER CODE BEGIN SVCall_IRQn 1 */
+
+	/* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Debug monitor.
+ */
+void DebugMon_Handler(void)
+{
+	/* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+	/* USER CODE END DebugMonitor_IRQn 0 */
+	/* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+	/* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+	/* USER CODE BEGIN PendSV_IRQn 0 */
+
+	/* USER CODE END PendSV_IRQn 0 */
+	/* USER CODE BEGIN PendSV_IRQn 1 */
+
+	/* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+	/* USER CODE BEGIN SysTick_IRQn 0 */
+
+	/* USER CODE END SysTick_IRQn 0 */
+	HAL_IncTick();
+	/* USER CODE BEGIN SysTick_IRQn 1 */
+
+	/* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32G4xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32g4xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/G4SPITESTING/README.md b/G4SPITESTING/README.md
new file mode 100644
index 000000000..c35301534
--- /dev/null
+++ b/G4SPITESTING/README.md
@@ -0,0 +1,10 @@
+# STM32G474 SPI
+Nucleo-G474RE-C04
+
+Compile and flash G4SPITESTING.elf
+
+## Testing
+
+Connect pins C11 and C12 together
+
+Run the program and watch the SWO console
diff --git a/Lib/FancyLayers-RENAME/SPI/Inc/msgBuffer.h b/Lib/FancyLayers-RENAME/SPI/Inc/msgBuffer.h
new file mode 100644
index 000000000..01dfe8497
--- /dev/null
+++ b/Lib/FancyLayers-RENAME/SPI/Inc/msgBuffer.h
@@ -0,0 +1,30 @@
+#ifndef MSG_BUFFER_H
+#define MSG_BUFFER_H
+
+#include <stdint.h>
+
+typedef struct msg_buffer_stc {
+	uint8_t *buffer;
+	uint32_t head;
+	uint32_t tail;
+	uint32_t free_space;
+	uint32_t max_size;
+} GR_MsgBuffer;
+
+void GR_MsgBuffer_Create(GR_MsgBuffer *msg_buffer, uint32_t size);
+
+void GR_MsgBuffer_Free(GR_MsgBuffer *msg_buffer);
+
+// Returns 0 on FAIL and 1 on SUCCESS
+int8_t GR_MsgBuffer_Push(GR_MsgBuffer *msg_buffer, uint8_t *byte_array, uint8_t size);
+
+// Returns 0 on FAIL and size on SUCCESS
+uint32_t GR_MsgBuffer_PeekMsgSize(GR_MsgBuffer *msg_buffer);
+
+// Returns 0 on FAIL and 1 on SUCCESS
+int8_t GR_MsgBuffer_Pop(GR_MsgBuffer *msg_buffer, uint8_t *byte_array);
+
+// Returns 0 on FALSE and 1 on TRUE
+int8_t GR_MsgBuffer_IsEmpty(GR_MsgBuffer *msg_buffer);
+
+#endif // MSG_BUFFER_H
diff --git a/Lib/FancyLayers-RENAME/SPI/Inc/spi.h b/Lib/FancyLayers-RENAME/SPI/Inc/spi.h
new file mode 100644
index 000000000..35ede9d81
--- /dev/null
+++ b/Lib/FancyLayers-RENAME/SPI/Inc/spi.h
@@ -0,0 +1,146 @@
+#ifndef SPI_H
+#define SPI_H
+
+#include <stdint.h>
+
+#include "circularBuffer.h"
+#include "main.h"
+
+#define GR_SPI_UNKNOWN_IRQN -64
+#define GR_SPI_BUFFER_MESSAGE_CAPACITY 16
+
+// Generic type
+typedef struct {
+	uint8_t *data; // byte array
+	uint16_t size; // size of byte array
+} GR_SPI_Message;
+
+typedef struct {
+	SPI_TypeDef *SPIx;    // Pointer to SPI register wrapper (e.g. SPI1, SPI2, SPI3 macro defines)
+	GPIO_TypeDef **GPIOx; // Pointer to GPIO port register wrapper (e.g. GPIOA, GPIOB, GPIOC, etc. macro defines)
+			      // COPI, CIPO, SCLK, CS
+	uint32_t *pin_nums;		    // SPI pin numbers (e.g. LL_GPIO_PIN_0, LL_GPIO_PIN_1, LL_GPIO_PIN_2 macro defines)
+	uint32_t num_pins;		    // Number of SPI pins
+	uint32_t alternate_function_number; // Refer to the datasheet for the correct number (based on SPIx)
+} GR_SPI_Pins;
+
+typedef struct GR_SPI_Handler_struct {
+	// Contains all configuration information
+	LL_SPI_InitTypeDef *spi_config;
+	GR_SPI_Pins *pins;
+	// GR structs
+	CircularBuffer *rx_buffer;
+	CircularBuffer *tx_buffer;
+	// Tx-Rx parameters
+	uint8_t transfer_size;
+	// Tx-Rx current messages
+	GR_SPI_Message *current_msg;
+	volatile uint16_t current_tx_msg_index, current_rx_msg_index;
+	volatile uint8_t msg_status;
+	volatile int8_t error_status;
+} GR_SPI_Handler;
+
+// ============================= handle Functions =============================
+
+/**
+ * @brief Initializes SPI with config values and alternate function number.
+ * Creates circular buffer structs.
+ *
+ * @param handle
+ * @param config
+ * @param pin_config
+ * @return
+ */
+void GR_SPI_Initialize(GR_SPI_Handler *handle, LL_SPI_InitTypeDef *config, GR_SPI_Pins *pin_config);
+
+/**
+ * @brief Tear down the SPI handle and frees all relevant memory
+ * @param handle
+ */
+void GR_SPI_Close(GR_SPI_Handler *handle);
+
+/**
+ * @brief Deallocate the memory in a GR_SPI_Message
+ * @param msg
+ */
+void GR_SPI_Msg_Free(GR_SPI_Message *msg);
+
+/**
+ * @brief Handles SPI interrupts
+ * @param handle
+ */
+void GR_SPI_Interrupt_Handler(GR_SPI_Handler *handle);
+
+// Map SPI1-3 IRQHandlers to custom interrupt handle
+
+/**
+ * @brief Interrupt Request Handler for SPI1; defers to GR_SPI_Interrupt_Handler
+ */
+void SPI1_IRQHandler(void);
+/**
+ * @brief Interrupt Request Handler for SPI2; defers to GR_SPI_Interrupt_Handler
+ */
+void SPI2_IRQHandler(void);
+/**
+ * @brief Interrupt Request Handler for SPI3; defers to GR_SPI_Interrupt_Handler
+ */
+void SPI3_IRQHandler(void);
+
+// ============================= Tx/Rx =============================
+
+/**
+ * @brief The SPI message is sent via SPI and will likely interrupt the program immediately to finish the transaction. Msg is untouched and should be reused in GR_SPI_Receive or freed.
+ * @param handle
+ * @param data
+ */
+void GR_SPI_Send(GR_SPI_Handler *handle, GR_SPI_Message *msg);
+
+/**
+ * @brief The dest_msg will be destroyed and overwritten if there is a message to receive; otherwise, nothing happens.
+ * @param handle
+ * @param dest_msg
+ */
+void GR_SPI_Receive(GR_SPI_Handler *handle, GR_SPI_Message *dest_msg);
+
+/**
+ * @brief Returns whether a message was received and is waiting in the Rx buffer
+ * @param handle
+ * @return 1 if Rx is empty, 0 if Rx is not empty
+ */
+bool GR_SPI_IsRxEmpty(GR_SPI_Handler *handle);
+
+// ============================= Helper Functions =============================
+
+/**
+ * @brief Returns the interrupt request number for a given SPIx peripheral
+ * @param SPIx
+ * @return IRQ Number for SPIx
+ */
+uint32_t GR_SPI_Get_IRQn(SPI_TypeDef *SPIx);
+
+/**
+ * @brief Enables the GPIO port clocks and SPI clock needed for the given pins
+ * @param handle
+ */
+void GR_SPI_Enable_Clocks(GR_SPI_Handler *handle);
+
+/**
+ * @brief Configures GPIO pins for SPI
+ * @param handle
+ * @param pin_config
+ */
+void GR_SPI_Configure_Pins(GR_SPI_Handler *handle, LL_GPIO_InitTypeDef *pin_config);
+
+/**
+ * @brief Continues sending the next byte(s) within an SPI message
+ * @param handle
+ */
+void GR_SPI_Transfer_Tx_Bytes(GR_SPI_Handler *handle);
+
+/**
+ * @brief Pops off the next Tx message and initiates its transaction
+ * @param handle
+ */
+void GR_SPI_Begin_New_Tx(GR_SPI_Handler *handle);
+
+#endif // SPI_H
diff --git a/Lib/FancyLayers-RENAME/SPI/README.md b/Lib/FancyLayers-RENAME/SPI/README.md
new file mode 100644
index 000000000..212b82901
--- /dev/null
+++ b/Lib/FancyLayers-RENAME/SPI/README.md
@@ -0,0 +1,90 @@
+# SPI
+
+This library establishes an easy interface to implement SPI in any GR Project (that utilizes the STM32G4 board). Users simply  have to define SPI configurations and pin configurations in their project and call `GR_SPI_Initialize()` which will return a `handler` which can be used to send and receive data.
+
+To use this library with CMake, one must link the library `SPI_Lib` as an `INTERFACE` to their targets with `target_link_libraries()`.
+
+## How To Use
+
+How to use GR_SPI library(FIX):
+
+1. The SPI config has to have
+2. The SPI_Initialize function creates a circular buffer that either leads to populating the tx or rx buffer. The SPI protocol is configured and the messages
+
+## Limitations
+
+The GR_SPI library currently only supports a single controller and a single peripheral P2P connection. The GR_SPI significantly fragments microcontroller memory over time from dynamic message allocation. The library only supports controller/master behavior and does not support peripheral/slave behavior.
+
+## EXAMPLE CODE
+
+```c
+// Instantiate a GR_SPI_Handler, LL_SPI config struct, and GR_SPI_Pins sttruct
+GR_SPI_Handler ex_handler;
+LL_SPI_InitTypeDef ex_config;
+GR_SPI_Pins ex_pins;
+
+// Configure LL_SPI configuration struct
+ex_config.TransferDirection = LL_SPI_FULL_DUPLEX;
+ex_config.Mode = LL_SPI_MODE_MASTER;
+ex_config.DataWidth = LL_SPI_DATAWIDTH_8BIT;
+ex_config.ClockPolarity = LL_SPI_POLARITY_LOW;
+ex_config.ClockPhase = LL_SPI_PHASE_1EDGE;
+ex_config.NSS = LL_SPI_NSS_SOFT;
+ex_config.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
+ex_config.BitOrder = LL_SPI_LSB_FIRST;
+ex_config.CRCCalculation = LL_SPI_CRCCALCULATION_ENABLE;
+ex_config.CRCPoly = 0x1D;
+
+// Configure GR_SPI_Pins struct
+ex_pins.SPIx = SPI3;
+ex_pins.GPIOx = (GPIO_TypeDef **)(malloc(4 * sizeof(GPIO_TypeDef *)));
+// All pins are in the A clock port
+for (int i = 0; i < 3; i++) {
+    *(ex_pins.GPIOx + i) = GPIOC;
+}
+ex_pins.GPIOx[3] = GPIOA;
+ex_pins.num_pins = 4;
+ex_pins.pin_nums = (uint32_t *)malloc(4 * sizeof(int));
+ex_pins.pin_nums[0] = LL_GPIO_PIN_12; // COPI
+ex_pins.pin_nums[1] = LL_GPIO_PIN_11; // CIPO
+ex_pins.pin_nums[2] = LL_GPIO_PIN_10; // SCK
+ex_pins.pin_nums[3] = LL_GPIO_PIN_4; // NSS
+ex_pins.alternate_function_number = 6;
+
+// Initialize SPI
+GR_SPI_Initialize(&ex_handler, &ex_config, &ex_pins);
+
+// Instantiate the message object
+GR_SPI_Message msg;
+msg.data = (uint8_t *)malloc(32 * sizeof(uint8_t));
+msg.size = 32;
+
+// Initialize msg byte array with values
+for(int i = 0; i < msg.size; i++) {
+    msg.data[i] = 'A' + i;
+}
+
+// Send a message
+GR_SPI_Send(&ex_handler, &msg);
+
+// Wait until receive is no longer empty
+while (GR_SPI_IsRxEmpty(&ex_handler)) {}
+
+// Receive a message
+GR_SPI_Receive(&ex_handler, &msg);
+
+// Now msg contains the received content
+
+// Clean everything up (note: GR_SPI_Msg_Free(msg) should be used if msg object was on the heap)
+free(msg.data);
+GR_SPI_Close(&ex_handler);
+
+```
+
+## Future Plans
+
+1. Add support multiple boards (STM32U5, STM32L4)
+2. Prevent minor race conditions
+3. Replace CircularBuffer with a custom byte array buffer
+4. Support more complex SPI features such as SIMPLEX RX only
+5. Remove all dynamic message heap allocation and stick to byte arrays
diff --git a/Lib/FancyLayers-RENAME/SPI/Src/msgBuffer.c b/Lib/FancyLayers-RENAME/SPI/Src/msgBuffer.c
new file mode 100644
index 000000000..3153a6164
--- /dev/null
+++ b/Lib/FancyLayers-RENAME/SPI/Src/msgBuffer.c
@@ -0,0 +1,72 @@
+#include "msgBuffer.h"
+
+#include <stdbool.h>
+
+#define SUCCESS 1
+#define FAIL 0
+
+void GR_MsgBuffer_Create(GR_MsgBuffer *msg_buffer, uint32_t size)
+{
+	msg_buffer->buffer = (uint8_t *)malloc(size * sizeof(uint8_t));
+	msg_buffer->max_size = size;
+	msg_buffer->free_space = size;
+	msg_buffer->head = 0;
+	msg_buffer->tail = 0;
+}
+
+void GR_MsgBuffer_Free(GR_MsgBuffer *msg_buffer)
+{
+	free(msg_buffer->buffer);
+}
+
+int8_t GR_MsgBuffer_Push(GR_MsgBuffer *msg_buffer, uint8_t *byte_array, uint8_t size)
+{
+	if ((size + 1) > msg_buffer->free_space) {
+		return FAIL;
+	} else {
+		msg_buffer->buffer[msg_buffer->head] = size;
+		msg_buffer->head = (msg_buffer->head + 1) % msg_buffer->max_size;
+
+		for (int i = 0; i < size; i++) {
+			msg_buffer->buffer[msg_buffer->head] = byte_array[i];
+			msg_buffer->head = (msg_buffer->head + 1) % msg_buffer->max_size;
+		}
+	}
+
+	return SUCCESS;
+}
+
+uint32_t GR_MsgBuffer_PeekMsgSize(GR_MsgBuffer *msg_buffer)
+{
+	if (msg_buffer->free_space == msg_buffer->max_size) {
+		return FAIL;
+	} else {
+		return msg_buffer->buffer[msg_buffer->head];
+	}
+}
+
+int8_t GR_MsgBuffer_Pop(GR_MsgBuffer *msg_buffer, uint8_t *byte_array)
+{
+	int msg_size = msg_buffer->buffer[msg_buffer->head];
+	msg_buffer->head = (msg_buffer->head + 1) % msg_buffer->max_size;
+
+	if (msg_buffer->free_space == msg_buffer->max_size) {
+		return FAIL;
+	}
+
+	if (byte_array) {
+		for (int i = 0; i < msg_size; i++) {
+			byte_array[i] = msg_buffer->buffer[msg_buffer->head];
+			msg_buffer->head = (msg_buffer->head + 1) % msg_buffer->max_size;
+		}
+	}
+
+	msg_buffer->free_space += msg_size + 1;
+
+	return SUCCESS;
+}
+
+int8_t GR_MsgBuffer_IsEmpty(GR_MsgBuffer *msg_buffer)
+{
+	return msg_buffer->free_space == msg_buffer->max_size;
+}
diff --git a/Lib/FancyLayers-RENAME/SPI/Src/spi.c b/Lib/FancyLayers-RENAME/SPI/Src/spi.c
new file mode 100644
index 000000000..945272ba4
--- /dev/null
+++ b/Lib/FancyLayers-RENAME/SPI/Src/spi.c
@@ -0,0 +1,425 @@
+// Wonderful SPI Abstraction Layer courtesy of Bailey, Colin, and Aaryan
+#include "spi.h"
+
+#include <stdlib.h>
+
+// Transfer sizes
+#define GR_SPI_TRANSFER_SIZE_8 8
+#define GR_SPI_TRANSFER_SIZE_16 16
+
+// Current message status codes
+#define GR_SPI_MSG_IN_PROGRESS 1
+#define GR_SPI_MSG_IDLE 0
+#define GR_SPI_INVALID_TX_SIZE 65535 // max message size is 2^16 bytes
+
+#define GR_SPI_ERR_NONE 0
+#define GR_SPI_ERR_FRE -1
+#define GR_SPI_ERR_OVR -2
+#define GR_SPI_ERR_MODF -3
+#define GR_SPI_ERR_CRCERR -4
+#define GR_SPI_ERR_RXFULL -5
+#define GR_SPI_ERR_BAD_INIT_NVIC -6
+#define GR_SPI_ERR_BAD_INIT_RXBUF -7
+#define GR_SPI_ERR_BAD_INIT_TXBUF -8
+#define GR_SPI_ERR_BAD_SPIX -9
+#define GR_SPI_ERR_BAD_ADD -10
+#define GR_SPI_ERR_FULL_TRANSMIT -11;
+
+static GR_SPI_Handler *GR_SPI_HANDLER_LUT[3]; // Stores pointer to the handle structs for SPI1
+					      // (0), SPI2 (1), & SPI3 (2)
+
+void GR_SPI_Initialize(GR_SPI_Handler *handle, LL_SPI_InitTypeDef *config, GR_SPI_Pins *pin_config)
+{
+	// Create Circular Buffers
+	CircularBuffer *circular_buffer_ptr;
+	circular_buffer_ptr = GR_CircularBuffer_Create(GR_SPI_BUFFER_MESSAGE_CAPACITY);
+	if (circular_buffer_ptr == NULL) {
+		handle->error_status = GR_SPI_ERR_BAD_INIT_RXBUF;
+		return;
+	} else {
+		handle->rx_buffer = circular_buffer_ptr;
+	}
+	circular_buffer_ptr = GR_CircularBuffer_Create(GR_SPI_BUFFER_MESSAGE_CAPACITY);
+	if (circular_buffer_ptr == NULL) {
+		handle->error_status = GR_SPI_ERR_BAD_INIT_TXBUF;
+		return;
+	} else {
+		handle->tx_buffer = circular_buffer_ptr;
+	}
+
+	// Copy over config values
+	handle->spi_config = (LL_SPI_InitTypeDef *)malloc(sizeof(LL_SPI_InitTypeDef)); // Make memory for LL_SPI_InitTypeDef
+										       // config struct
+	*handle->spi_config = *config;
+
+	// Deep copy of pins struct
+	handle->pins = (GR_SPI_Pins *)malloc(sizeof(GR_SPI_Pins));				    // Make memory for GR_SPI_Pins struct
+	handle->pins->pin_nums = (uint32_t *)malloc(pin_config->num_pins * sizeof(uint32_t));	    // Make memory for pin_nums[num_pins]
+	handle->pins->GPIOx = (GPIO_TypeDef **)malloc(pin_config->num_pins * sizeof(GPIO_TypeDef)); // Make memory for GPIOx[num_pins]
+	for (uint32_t i = 0; i < pin_config->num_pins; i++) {
+		handle->pins->pin_nums[i] = pin_config->pin_nums[i];
+		handle->pins->GPIOx[i] = pin_config->GPIOx[i];
+	}
+	handle->pins->SPIx = pin_config->SPIx;
+	handle->pins->num_pins = pin_config->num_pins;
+	handle->pins->alternate_function_number = pin_config->alternate_function_number;
+
+	// Set current message variables
+	handle->current_msg = NULL;
+	handle->current_rx_msg_index = 0;
+	handle->current_tx_msg_index = 0;
+	handle->msg_status = GR_SPI_MSG_IDLE;
+
+	// Error status variable
+	handle->error_status = GR_SPI_ERR_NONE;
+
+	// Store handle in lookup table for interrupts
+	if (handle->pins->SPIx == SPI1) {
+		GR_SPI_HANDLER_LUT[0] = handle;
+	} else if (handle->pins->SPIx == SPI2) {
+		GR_SPI_HANDLER_LUT[1] = handle;
+	} else if (handle->pins->SPIx == SPI3) {
+		GR_SPI_HANDLER_LUT[2] = handle;
+	} else {
+		handle->error_status = GR_SPI_ERR_BAD_SPIX;
+		return;
+	}
+
+	// Disable SPI
+	LL_SPI_Disable(handle->pins->SPIx);
+
+	// Enable GPIO and SPI clocks
+	GR_SPI_Enable_Clocks(handle);
+
+	// Configure GPIOs
+	LL_GPIO_InitTypeDef gpio_pin_config;
+	GR_SPI_Configure_Pins(handle, &gpio_pin_config);
+
+	// Configure SPI protocol with config values
+	LL_SPI_Init(handle->pins->SPIx, config);
+	// Transaction size is 8-bits
+	if (config->DataWidth <= (SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2)) {
+		handle->transfer_size = GR_SPI_TRANSFER_SIZE_8;
+		// Make the RXNE trigger when >= 8 bits are received
+		handle->pins->SPIx->CR2 |= SPI_CR2_FRXTH;
+	}
+	// Transaction size is 16-bits
+	else {
+		handle->transfer_size = GR_SPI_TRANSFER_SIZE_16;
+		// Make the RXNE trigger when >= 16 bits are received
+		handle->pins->SPIx->CR2 &= ~SPI_CR2_FRXTH;
+	}
+
+	// Enable SPI peripheral after BSY flag clears
+	while (LL_SPI_IsActiveFlag_BSY(handle->pins->SPIx)) {}
+	LL_SPI_Enable(handle->pins->SPIx);
+
+	// Enable interrupts in NVIC
+	int SPI_IRQn = GR_SPI_Get_IRQn(handle->pins->SPIx);
+	if (SPI_IRQn != GR_SPI_UNKNOWN_IRQN) {
+		NVIC_SetPriority(SPI_IRQn, 1);
+		NVIC_EnableIRQ(SPI_IRQn);
+	} else {
+		handle->error_status = GR_SPI_ERR_BAD_INIT_NVIC;
+		return; // Throw an error
+	}
+
+	// Enable interrupts at peripheral level (TXE is enabled in GR_SPI_Begin_New_Tx and disabled in GR_SPI_Transfer_Tx_Bytes)
+	LL_SPI_EnableIT_ERR(handle->pins->SPIx);  // Error interrupt
+	LL_SPI_EnableIT_RXNE(handle->pins->SPIx); // Not empty Rx buffer
+}
+
+void GR_SPI_Send(GR_SPI_Handler *handle, GR_SPI_Message *msg)
+{
+	GR_SPI_Message temp_msg;
+	temp_msg.size = msg->size;
+	temp_msg.data = malloc(temp_msg.size * sizeof(uint8_t));
+	for (int i = 0; i < temp_msg.size; i++) {
+		temp_msg.data[i] = msg->data[i];
+	}
+
+	// Push the new message (copy) onto the Tx circular buffer
+	GR_CircularBuffer_Push(handle->tx_buffer, &temp_msg, sizeof(GR_SPI_Message));
+
+	// Check if there is no message in progress
+	if (handle->msg_status != GR_SPI_MSG_IN_PROGRESS) {
+		GR_SPI_Begin_New_Tx(handle);
+	}
+}
+
+void GR_SPI_Receive(GR_SPI_Handler *handle, GR_SPI_Message *dest_msg)
+{
+	GR_SPI_Message *rx_msg = GR_CircularBuffer_Pop(handle->rx_buffer);
+
+	// Check if there was a message returned by buffer pop
+	if (rx_msg) {
+		// If sizes don't match, re-malloc correct size inside destination message
+		if (dest_msg->size != rx_msg->size) {
+			free(dest_msg->data);
+			dest_msg->size = rx_msg->size;
+			dest_msg->data = malloc(rx_msg->size * sizeof(uint8_t));
+		}
+
+		// Copy over data into the destination message
+		for (int i = 0; i < dest_msg->size; i++) {
+			dest_msg->data[i] = rx_msg->data[i];
+		}
+
+		// Deallocate rx_msg
+		GR_SPI_Msg_Free(rx_msg);
+	}
+}
+
+void SPI1_IRQHandler(void)
+{
+	GR_SPI_Interrupt_Handler(GR_SPI_HANDLER_LUT[0]);
+}
+
+void SPI2_IRQHandler(void)
+{
+	GR_SPI_Interrupt_Handler(GR_SPI_HANDLER_LUT[1]);
+}
+
+void SPI3_IRQHandler(void)
+{
+	GR_SPI_Interrupt_Handler(GR_SPI_HANDLER_LUT[2]);
+}
+
+void GR_SPI_Interrupt_Handler(GR_SPI_Handler *handle)
+{
+	// Check if called by error interrupt
+	// Frame format error
+	if (LL_SPI_IsActiveFlag_FRE(handle->pins->SPIx)) {
+		handle->error_status = GR_SPI_ERR_FRE;
+		return;
+	}
+	// Overrun error
+	else if (LL_SPI_IsActiveFlag_OVR(handle->pins->SPIx)) {
+		handle->error_status = GR_SPI_ERR_OVR;
+		return;
+	}
+	// Fault mode error
+	else if (LL_SPI_IsActiveFlag_MODF(handle->pins->SPIx)) {
+		handle->error_status = GR_SPI_ERR_MODF;
+		return;
+	}
+	// CRC error
+	else if (LL_SPI_IsActiveFlag_CRCERR(handle->pins->SPIx)) {
+		handle->error_status = GR_SPI_ERR_CRCERR;
+		return;
+	}
+
+	// No errors detected...
+
+	// Check if Rx circular buffer is not empty
+	if (LL_SPI_IsActiveFlag_RXNE(handle->pins->SPIx)) {
+		uint16_t rx_index = handle->current_rx_msg_index, msg_size = handle->current_msg->size;
+		// Queue the message into the circular buffer
+		if (handle->transfer_size == GR_SPI_TRANSFER_SIZE_16 && rx_index <= msg_size - 2) {
+			uint16_t data = LL_SPI_ReceiveData16(handle->pins->SPIx);
+			handle->current_msg->data[rx_index + 1] = (uint8_t)(data & 0xFF);
+			handle->current_msg->data[rx_index] = (uint8_t)(data >> 8);
+			handle->current_rx_msg_index += 2;
+		} else if (handle->transfer_size == GR_SPI_TRANSFER_SIZE_8 && rx_index <= msg_size - 1) {
+			uint8_t data = LL_SPI_ReceiveData8(handle->pins->SPIx);
+			handle->current_msg->data[rx_index] = data;
+			handle->current_rx_msg_index += 1;
+		} else {
+			// ERROR: Current message is full
+			handle->error_status = GR_SPI_ERR_RXFULL;
+		}
+
+		// Push current message into Rx circular buffer to mark completion
+		if (handle->current_rx_msg_index == msg_size) {
+			handle->current_rx_msg_index = 0;
+			GR_CircularBuffer_Push(handle->rx_buffer, (void *)handle->current_msg, sizeof(GR_SPI_Message));
+			// Free message struct but not the byte array within the message (pointed to by the message on the rx_buffer)
+			free(handle->current_msg);
+			handle->current_msg = NULL;
+			// Finish transaction
+			LL_GPIO_SetOutputPin(handle->pins->GPIOx[3], handle->pins->pin_nums[3]);
+			// Only go to IDLE when no additional messages are in pipeline
+			if (GR_CircularBuffer_IsEmpty(handle->tx_buffer)) {
+				handle->msg_status = GR_SPI_MSG_IDLE;
+			} else {
+				GR_SPI_Begin_New_Tx(handle);
+			}
+		}
+	}
+	// Check if Tx is empty
+	if (LL_SPI_IsActiveFlag_TXE(handle->pins->SPIx)) {
+		// Continue sending bytes in transaction
+		if (handle->current_tx_msg_index != GR_SPI_INVALID_TX_SIZE) {
+			GR_SPI_Transfer_Tx_Bytes(handle);
+		}
+	}
+}
+
+// SPIx_IRQn is defined in stm32 libraries
+uint32_t GR_SPI_Get_IRQn(SPI_TypeDef *SPIx)
+{
+	if (SPIx == SPI1) {
+		return SPI1_IRQn; // 35
+	} else if (SPIx == SPI2) {
+		return SPI2_IRQn; // 36
+	} else if (SPIx == SPI3) {
+		return SPI3_IRQn; // 51
+	} else {
+		return GR_SPI_UNKNOWN_IRQN;
+	}
+}
+
+void GR_SPI_Enable_Clocks(GR_SPI_Handler *handle)
+{
+	uint32_t GPIOx_Port;
+
+	for (uint32_t i = 0; i < handle->pins->num_pins; i++) {
+		GPIO_TypeDef *gpio = handle->pins->GPIOx[i];
+
+		if (gpio == GPIOA) {
+			GPIOx_Port = LL_AHB2_GRP1_PERIPH_GPIOA;
+		} else if (gpio == GPIOB) {
+			GPIOx_Port = LL_AHB2_GRP1_PERIPH_GPIOB;
+		} else if (gpio == GPIOC) {
+			GPIOx_Port = LL_AHB2_GRP1_PERIPH_GPIOC;
+		} else if (gpio == GPIOD) {
+			GPIOx_Port = LL_AHB2_GRP1_PERIPH_GPIOD;
+		} else if (gpio == GPIOE) {
+			GPIOx_Port = LL_AHB2_GRP1_PERIPH_GPIOE;
+		} else if (gpio == GPIOF) {
+			GPIOx_Port = LL_AHB2_GRP1_PERIPH_GPIOF;
+		} else if (gpio == GPIOG) {
+			GPIOx_Port = LL_AHB2_GRP1_PERIPH_GPIOG;
+		}
+		// Note: GPIOH does not exist on G4 board
+		else {
+			continue; // unknown GPIOx
+		}
+
+		LL_AHB2_GRP1_EnableClock(GPIOx_Port);
+	}
+
+	// Enable SPI clock
+	if (handle->pins->SPIx == SPI1) {
+		LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
+	} else if (handle->pins->SPIx == SPI2) {
+		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
+	} else if (handle->pins->SPIx == SPI3) {
+		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI3);
+	} else {
+		// ERROR: Unexpected SPI address
+		handle->error_status = GR_SPI_ERR_BAD_ADD;
+		return;
+	}
+}
+
+void GR_SPI_Begin_New_Tx(GR_SPI_Handler *handle)
+{
+	// Re-initiate a transaction
+	handle->msg_status = GR_SPI_MSG_IN_PROGRESS;
+	handle->current_tx_msg_index = 0;
+	handle->current_rx_msg_index = 0;
+	handle->current_msg = GR_CircularBuffer_Pop(handle->tx_buffer);
+
+	// Pull chip select to active low
+	LL_GPIO_ResetOutputPin(handle->pins->GPIOx[3], handle->pins->pin_nums[3]);
+
+	// Enable TXE interrupts for loading bytes into TX buffer
+	LL_SPI_EnableIT_TXE(handle->pins->SPIx); // Empty Tx buffer
+}
+
+void GR_SPI_Transfer_Tx_Bytes(GR_SPI_Handler *handle)
+{
+	uint16_t tx_index = handle->current_tx_msg_index, msg_size = handle->current_msg->size;
+	// Send two bytes if transferring 16 bits
+	if (handle->transfer_size == GR_SPI_TRANSFER_SIZE_16 && tx_index <= msg_size - 2) {
+		uint16_t data = (((uint16_t)handle->current_msg->data[tx_index]) << 8) + handle->current_msg->data[tx_index + 1];
+		LL_SPI_TransmitData16(handle->pins->SPIx, data);
+		handle->current_tx_msg_index += 2;
+	}
+	// Send one byte if transferring 8 bits or transferring 16 bits with only 8 bits left
+	else if (handle->transfer_size == GR_SPI_TRANSFER_SIZE_8 && tx_index <= msg_size - 1) {
+		uint8_t data = handle->current_msg->data[tx_index];
+		LL_SPI_TransmitData8(handle->pins->SPIx, data);
+		handle->current_tx_msg_index += 1;
+	} else {
+		// ERROR: Message was already fully transmitted
+		handle->error_status = GR_SPI_ERR_FULL_TRANSMIT;
+		return;
+	}
+
+	// Mark message send complete
+	if (handle->current_tx_msg_index == msg_size) {
+		handle->current_tx_msg_index = 0;
+		// Queue up next message to be sent
+		if (!GR_CircularBuffer_IsEmpty(handle->tx_buffer)) {
+			handle->current_msg = GR_CircularBuffer_Pop(handle->tx_buffer);
+		}
+		// No more messages to load into transfer buffer
+		else {
+			handle->current_tx_msg_index = GR_SPI_INVALID_TX_SIZE;
+			LL_SPI_DisableIT_TXE(handle->pins->SPIx);
+		}
+	}
+}
+
+void GR_SPI_Configure_Pins(GR_SPI_Handler *handle, LL_GPIO_InitTypeDef *pin_config)
+{
+	LL_GPIO_StructInit(pin_config);					 // Default config values
+	pin_config->Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;		 // Very high output speed
+	pin_config->Pull = LL_GPIO_PULL_NO;				 // No pull-up or pull-down
+	pin_config->OutputType = LL_GPIO_OUTPUT_PUSHPULL;		 // Push-pull output (not open-drain)
+	pin_config->Mode = LL_GPIO_MODE_ALTERNATE;			 // Alternate pin function mode
+	pin_config->Alternate = handle->pins->alternate_function_number; // Alternate function number
+	for (uint32_t i = 0; i < handle->pins->num_pins; i++) {
+		pin_config->Pin = handle->pins->pin_nums[i];
+		LL_GPIO_Init(handle->pins->GPIOx[i], pin_config);
+	}
+}
+
+void GR_SPI_Close(GR_SPI_Handler *handle)
+{
+	// Safety Checks
+	LL_GPIO_SetOutputPin(handle->pins->GPIOx[3], handle->pins->pin_nums[3]); // Set CS high
+
+	// Set all the pins analog
+	for (int i = 0; i < 3; i++) {
+		LL_GPIO_SetPinMode(handle->pins->GPIOx[i], handle->pins->pin_nums[i], LL_GPIO_MODE_ANALOG);
+	}
+
+	// Disable and DeInit
+	LL_SPI_Disable(handle->pins->SPIx);
+	LL_SPI_DeInit(handle->pins->SPIx);
+
+	// Deallocate memory
+	if (handle->spi_config) {
+		free(handle->spi_config);
+	}
+	if (handle->pins->GPIOx) {
+		free(handle->pins->GPIOx);
+	}
+	if (handle->pins->pin_nums) {
+		free(handle->pins->pin_nums);
+	}
+	if (handle->pins) {
+		free(handle->pins);
+	}
+	GR_SPI_Msg_Free(handle->current_msg);
+	GR_CircularBuffer_Free(&handle->rx_buffer);
+	GR_CircularBuffer_Free(&handle->tx_buffer);
+}
+
+void GR_SPI_Msg_Free(GR_SPI_Message *msg)
+{
+	if (msg) {
+		if (msg->data) {
+			free(msg->data);
+		}
+		free(msg);
+	}
+}
+
+bool GR_SPI_IsRxEmpty(GR_SPI_Handler *handle)
+{
+	return GR_CircularBuffer_IsEmpty(handle->rx_buffer);
+}
diff --git a/Lib/FancyLayers-RENAME/SPI/spi.cmake b/Lib/FancyLayers-RENAME/SPI/spi.cmake
new file mode 100644
index 000000000..f1c8a00e1
--- /dev/null
+++ b/Lib/FancyLayers-RENAME/SPI/spi.cmake
@@ -0,0 +1,11 @@
+add_library(SPI_Lib INTERFACE)
+
+target_sources(SPI_Lib INTERFACE ${CMAKE_CURRENT_LIST_DIR}/Src/spi.c)
+target_include_directories(SPI_Lib INTERFACE ${CMAKE_CURRENT_LIST_DIR}/Inc)
+
+target_link_libraries(
+	SPI_Lib
+	INTERFACE
+		GLOBALSHARE_LIB
+		CircularBuffer_Lib
+)