Logic-Workbench/test-save.lw.txt at main · Damaged-Engineer-Interactive/Logic-Workbench · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
version_1
Circuit: "ADD"
UUID: 01#23#45#67
color: Color(1,1,1,1)
ports:
	(OUT, 3, 13, <1, 1>, "Q'")
	(OUT, 2, 7, <1, 0>, "Q")
	(IN, 1, 3, <0, 1>, "CLK")
	(IN, 0, 5, <0, 0>, "D")
blockId 13 LIGHT 6 1 ZERO
	(connId:0) (8 1)
blockId 12 NOR 1 1 ZERO
	(connId:0) (5 0)
	(connId:1) (2 0)
blockId 11 NOR 4 1 ZERO
	(connId:0) (3 0) (4 1)
	(connId:1) (8 0)
blockId 10 NOR 5 0 ZERO
	(connId:0) (8 1) (9 1)
	(connId:1) (8 0) (7 0)
blockId 9 NOR 4 0 ZERO
	(connId:0) (3 0) (6 1)
	(connId:1) (10 0)
blockId 8 NOR 5 1 ZERO
	(connId:1) (10 0) (13 0)
	(connId:0) (10 1) (11 1)
blockId 7 LIGHT 6 0 ZERO
	(connId:0) (10 1)
blockId 6 NAND 3 0 ZERO
	(connId:0) (1 1) (4 1)
	(connId:1) (4 0) (9 0)
blockId 5 SWITCH 0 0 ZERO
	(connId:0) (12 0) (1 0)
blockId 4 NAND 3 1 ZERO
	(connId:1) (6 0) (11 0)
	(connId:0) (2 1) (6 1)
blockId 3 SWITCH 0 1 ZERO
	(connId:0) (2 0) (1 0) (11 0) (9 0)
blockId 2 NAND 2 1 ZERO
	(connId:1) (4 0)
	(connId:0) (3 0) (12 1)
blockId 1 NAND 2 0 ZERO
	(connId:1) (6 0)
	(connId:0) (3 0) (5 0)