gpu: reverse several changes not required anymore

Author: Creeeeger

drivers/gpu/arm/bv_r38p1/backend/gpu/mali_kbase_devfreq.c

@@ -74,9 +74,9 @@ static unsigned long get_voltage(struct kbase_device *kbdev, unsigned long freq)
 }
 
 void kbase_devfreq_opp_translate(struct kbase_device *kbdev, unsigned long freq,
-        u64 *core_mask, unsigned long *freqs, unsigned long *volts)
+	u64 *core_mask, unsigned long *freqs, unsigned long *volts)
 {
-        unsigned int i;
+	unsigned int i;
 
 	for (i = 0; i < kbdev->num_opps; i++) {
 		if (kbdev->devfreq_table[i].opp_freq == freq) {
@@ -91,28 +91,8 @@ void kbase_devfreq_opp_translate(struct kbase_device *kbdev, unsigned long freq,
 			}
 
 			break;
-        }
-}
-
-static void kbase_devfreq_log_target(struct kbase_device *kbdev,
-		unsigned long nominal_freq, u64 core_mask,
-		unsigned long *freqs, unsigned long *volts)
-{
-	unsigned int i;
-
-	dev_info(kbdev->dev, "devfreq target freq=%lu core_mask=0x%llx\n",
-		nominal_freq, core_mask);
-
-	for (i = 0; i < kbdev->nr_clocks; i++)
-		dev_info(kbdev->dev, "  clock[%u]=%lu Hz\n", i, freqs[i]);
-
-#if IS_ENABLED(CONFIG_REGULATOR)
-	for (i = 0; i < kbdev->nr_regulators; i++)
-		dev_info(kbdev->dev, "  voltage[%u]=%lu uV\n", i, volts[i]);
-#else
-	(void)volts;
-#endif
-}
+		}
+	}
 
 	/* If failed to find OPP, return all cores enabled
 	 * and nominal frequency and the corresponding voltage.
@@ -169,9 +149,7 @@ kbase_devfreq_target(struct device *dev, unsigned long *target_freq, u32 flags)
 	}
 
 	kbase_devfreq_opp_translate(kbdev, nominal_freq, &core_mask,
-			freqs, volts);
-
-	kbase_devfreq_log_target(kbdev, nominal_freq, core_mask, freqs, volts);
+				    freqs, volts);
 
 #if IS_ENABLED(CONFIG_REGULATOR)
 	/* Regulators and clocks work in pairs: every clock has a regulator,
@@ -516,47 +494,39 @@ static int kbase_devfreq_init_core_mask_table(struct kbase_device *kbdev)
 			}
 		}
 
-        if (!core_mask) {
-                dev_err(kbdev->dev, "OPP has invalid core mask of 0\n");
-                return -ENODEV;
-        }
+		if (!core_mask) {
+			dev_err(kbdev->dev, "OPP has invalid core mask of 0\n");
+			return -ENODEV;
+		}
 
-        kbdev->devfreq_table[i].opp_freq = opp_freq;
-        kbdev->devfreq_table[i].core_mask = core_mask;
-        if (kbdev->nr_clocks > 0) {
-                int j;
+		kbdev->devfreq_table[i].opp_freq = opp_freq;
+		kbdev->devfreq_table[i].core_mask = core_mask;
+		if (kbdev->nr_clocks > 0) {
+			int j;
 
-                for (j = 0; j < kbdev->nr_clocks; j++)
-                        kbdev->devfreq_table[i].real_freqs[j] =
-                                        real_freqs[j];
-        }
+			for (j = 0; j < kbdev->nr_clocks; j++)
+				kbdev->devfreq_table[i].real_freqs[j] =
+					real_freqs[j];
+		}
 #if IS_ENABLED(CONFIG_REGULATOR)
-        if (kbdev->nr_regulators > 0) {
-                int j;
+		if (kbdev->nr_regulators > 0) {
+			int j;
 
-                for (j = 0; j < kbdev->nr_regulators; j++)
-                        kbdev->devfreq_table[i].opp_volts[j] =
-                                        opp_volts[j];
-        }
+			for (j = 0; j < kbdev->nr_regulators; j++)
+				kbdev->devfreq_table[i].opp_volts[j] =
+						opp_volts[j];
+		}
 #endif
 
-        dev_info(kbdev->dev, "OPP %d : opp_freq=%llu core_mask=%llx\n",
-                        i, opp_freq, core_mask);
-        for (j = 0; j < kbdev->nr_clocks; j++)
-                dev_info(kbdev->dev, "\tOPP %d clock[%d]=%llu Hz\n",
-                                i, j, kbdev->devfreq_table[i].real_freqs[j]);
-#if IS_ENABLED(CONFIG_REGULATOR)
-        for (j = 0; j < kbdev->nr_regulators; j++)
-                dev_info(kbdev->dev, "\tOPP %d voltage[%d]=%u uV\n",
-                                i, j, kbdev->devfreq_table[i].opp_volts[j]);
-#endif
+		dev_info(kbdev->dev, "OPP %d : opp_freq=%llu core_mask=%llx\n",
+				i, opp_freq, core_mask);
 
-        i++;
-}
+		i++;
+	}
 
-        kbdev->num_opps = i;
+	kbdev->num_opps = i;
 
-        return 0;
+	return 0;
 #endif /* CONFIG_OF */
 }
 

drivers/gpu/arm/bv_r38p1/mali_kbase_core_linux.c

@@ -3155,7 +3155,7 @@ static char gpuinfo_override[64];
  * Return: The number of bytes output to @buf.
  */
 static ssize_t gpuinfo_show(struct device *dev,
-		struct device_attribute *attr, char *buf)
+				  struct device_attribute *attr, char *buf)
 {
 	static const struct gpu_product_id_name {
 		unsigned int id;
@@ -3295,10 +3295,7 @@ static ssize_t gpuinfo_store(struct device *dev, struct device_attribute *attr,
 
 	return count;
 }
-
-static DEVICE_ATTR_RW(gpuinfo);
-
-
+static DEVICE_ATTR_RO(gpuinfo);
 
 /**
  * dvfs_period_store - Store callback for the dvfs_period sysfs file.

drivers/gpu/arm/bv_r38p1/mali_kbase_dummy_job_wa.c

@@ -254,39 +254,7 @@ static ssize_t dummy_job_wa_info_show(struct device * const dev,
 	return err;
 }
 
-static ssize_t dummy_job_wa_info_store(struct device *const dev,
-		struct device_attribute *const attr, const char *const buf,
-		size_t const count)
-{
-	struct kbase_device *const kbdev = dev_get_drvdata(dev);
-	unsigned int slot;
-	u64 flags;
-	int parsed;
-
-	if (!kbdev || !kbdev->dummy_job_wa.ctx)
-		return -ENODEV;
-
-	parsed = sscanf(buf, "%u %llx", &slot, &flags);
-	if (parsed < 1)
-		return -EINVAL;
-
-	if (parsed < 2)
-		flags = kbdev->dummy_job_wa.flags;
-
-	if (flags & ~KBASE_DUMMY_JOB_WA_FLAGS)
-		return -EINVAL;
-
-	kbdev->dummy_job_wa.slot = slot;
-	kbdev->dummy_job_wa.flags = flags;
-
-	dev_info(kbdev->dev,
-		"dummy_job_wa_info updated: slot %u flags %llx\n",
-		slot, flags);
-
-	return count;
-}
-
-static DEVICE_ATTR_RW(dummy_job_wa_info);
+static DEVICE_ATTR_RO(dummy_job_wa_info);
 
 static bool wa_blob_load_needed(struct kbase_device *kbdev)
 {

drivers/gpu/arm/exynos/backend/gpexbe_devicetree.c

@@ -263,10 +263,10 @@ static void read_from_dt(void)
 	gpexbe_devicetree_read_u32("gpu_debug_level", &dt_info.gpu_debug_level);
 
 	/* HCM */
-        gpexbe_devicetree_read_u32("gpu_heavy_compute_cpu0_min_clock",
-                                   &dt_info.gpu_heavy_compute_cpu0_min_clock);
-        gpexbe_devicetree_read_u32("gpu_heavy_compute_vk_cpu0_min_clock",
-                                   &dt_info.gpu_heavy_compute_vk_cpu0_min_clock);
+	gpexbe_devicetree_read_u32("gpu_heavy_compute_cpu0_min_clock;",
+				   &dt_info.gpu_heavy_compute_cpu0_min_clock);
+	gpexbe_devicetree_read_u32("gpu_heavy_compute_vk_cpu0_min_clock;",
+				   &dt_info.gpu_heavy_compute_vk_cpu0_min_clock);
 
 	/* TSG */
 	gpexbe_devicetree_read_u32("gpu_weight_table_idx_0", &dt_info.gpu_weight_table_idx_0);