Skip to content

Commit af0c523

Browse files
maxgerhardtmaxgerhardt
committed
Add autogenerated F30x variants except F303CC
1 parent f4b8a7d commit af0c523

120 files changed

Lines changed: 18970 additions & 0 deletions

File tree

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎variants/GD32F303CB_GENERIC/PeripheralNames.h‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
/*
2+
Copyright (c) 2021, CommunityGD32Cores
3+
4+
Redistribution and use in source and binary forms, with or without modification,
5+
are permitted provided that the following conditions are met:
6+
7+
1. Redistributions of source code must retain the above copyright notice, this
8+
list of conditions and the following disclaimer.
9+
2. Redistributions in binary form must reproduce the above copyright notice,
10+
this list of conditions and the following disclaimer in the documentation
11+
and/or other materials provided with the distribution.
12+
3. Neither the name of the copyright holder nor the names of its contributors
13+
may be used to endorse or promote products derived from this software without
14+
specific prior written permission.
15+
16+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18+
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19+
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
20+
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21+
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
22+
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23+
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24+
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
25+
OF SUCH DAMAGE.
26+
*/
27+
28+
#ifndef PERIPHERALNAMES_H
29+
#define PERIPHERALNAMES_H
30+
31+
#include "gd32xxyy.h"
32+
33+
#ifdef __cplusplus
34+
extern "C" {
35+
#endif
36+
37+
typedef enum {
38+
ADC_0 = (int)ADC0,
39+
ADC_1 = (int)ADC1,
40+
ADC_2 = (int)ADC2
41+
} ADCName;
42+
43+
typedef enum {
44+
DAC_0 = (int)DAC
45+
} DACName;
46+
47+
typedef enum {
48+
UART_0 = (int)USART0,
49+
UART_1 = (int)USART1,
50+
UART_2 = (int)USART2
51+
} UARTName;
52+
53+
typedef enum {
54+
SPI_0 = (int)SPI0,
55+
SPI_1 = (int)SPI1,
56+
SPI_2 = (int)SPI2
57+
} SPIName;
58+
59+
typedef enum {
60+
I2C_0 = (int)I2C0,
61+
I2C_1 = (int)I2C1
62+
} I2CName;
63+
64+
typedef enum {
65+
PWM_0 = (int)TIMER0,
66+
PWM_1 = (int)TIMER1,
67+
PWM_2 = (int)TIMER2,
68+
PWM_3 = (int)TIMER3,
69+
PWM_4 = (int)TIMER4
70+
} PWMName;
71+
72+
73+
#ifdef __cplusplus
74+
}
75+
#endif
76+
77+
#endif

‎variants/GD32F303CB_GENERIC/PeripheralPins.c‎

Lines changed: 264 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,264 @@
1+
/*
2+
Copyright (c) 2020, GigaDevice Semiconductor Inc.
3+
4+
Redistribution and use in source and binary forms, with or without modification,
5+
are permitted provided that the following conditions are met:
6+
7+
1. Redistributions of source code must retain the above copyright notice, this
8+
list of conditions and the following disclaimer.
9+
2. Redistributions in binary form must reproduce the above copyright notice,
10+
this list of conditions and the following disclaimer in the documentation
11+
and/or other materials provided with the distribution.
12+
3. Neither the name of the copyright holder nor the names of its contributors
13+
may be used to endorse or promote products derived from this software without
14+
specific prior written permission.
15+
16+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18+
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19+
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
20+
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21+
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
22+
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23+
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24+
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
25+
OF SUCH DAMAGE.
26+
*/
27+
28+
#include "gd32xxyy.h"
29+
#include "PeripheralPins.h"
30+
31+
/* void pin_function(PinName pin, int function);
32+
configure the speed, mode,and remap function of pins
33+
the parameter function contains the configuration information,show as below
34+
bit 0:2 gpio mode
35+
bit 3:8 remap
36+
bit 9:10 gpio speed
37+
bit 11:15 adc /timer channel
38+
*/
39+
40+
/* pin descriptions only reference the index in the array, so
41+
* to get e.g. AF11 one must give it index = 9. provide
42+
* convenience macros here.
43+
* for all other arrays, the value is also equivalent to the index,
44+
* so there doesn't need to be anything done more.
45+
*/
46+
47+
/* Generated remapping names */
48+
49+
const int GD_GPIO_REMAP[] = {
50+
0x00000000,
51+
#if __has_include("gd32f30x_remap.h")
52+
#define __REMAP_NAME__(remap) GPIO_ ## remap,
53+
#include "gd32f30x_remap.h"
54+
#undef __REMAP_NAME__
55+
#endif
56+
};
57+
58+
enum GD_GPIO_REMAP_NAME {
59+
REMAP_NONE = 0U,
60+
#if __has_include("gd32f10x_remap.h")
61+
#define __REMAP_NAME__(remap) remap,
62+
#include "gd32f30x_remap.h"
63+
#undef __REMAP_NAME__
64+
#define __REMAP_NAME__(remap) DISABLE_ ## remap = GPIO_ ## remap | (1U << 6),
65+
#include "gd32f30x_remap.h"
66+
#undef __REMAP_NAME__
67+
#endif
68+
};
69+
70+
/* GPIO MODE */
71+
const int GD_GPIO_MODE[] = {
72+
GPIO_MODE_AIN, /* 0 INPUT_ANALOG */
73+
GPIO_MODE_IN_FLOATING, /* 1 INPUT */
74+
GPIO_MODE_IPD, /* 2 INPUT_PULLDOWN */
75+
GPIO_MODE_IPU, /* 3 INPUT_PULLUP */
76+
GPIO_MODE_OUT_OD, /* 4 OUTPUT_OPEN_DRAIN */
77+
GPIO_MODE_OUT_PP, /* 5 OUTPUT */
78+
GPIO_MODE_AF_OD, /* 6 ALT FUNC OPEN DRAIN */
79+
GPIO_MODE_AF_PP, /* 7 ALT FUNC PUSH PULL */
80+
};
81+
82+
/* GPIO SPEED */
83+
const int GD_GPIO_SPEED[] = {
84+
GPIO_OSPEED_2MHZ, /* 0 */
85+
GPIO_OSPEED_10MHZ, /* 1 */
86+
0, /* 2 (unused) */
87+
GPIO_OSPEED_50MHZ, /* 3 */
88+
};
89+
90+
/* ADC PinMap */
91+
const PinMap PinMap_ADC[] = {
92+
{PORTA_0, ADC0, GD_PIN_FUNC_ANALOG_CH(0)}, /* ADC0_IN0 */
93+
{PORTA_0_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(0)}, /* ADC1_IN0 */
94+
{PORTA_0_ALT2, ADC2, GD_PIN_FUNC_ANALOG_CH(0)}, /* ADC2_IN0 */
95+
{PORTA_1, ADC0, GD_PIN_FUNC_ANALOG_CH(1)}, /* ADC0_IN1 */
96+
{PORTA_1_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(1)}, /* ADC1_IN1 */
97+
{PORTA_1_ALT2, ADC2, GD_PIN_FUNC_ANALOG_CH(1)}, /* ADC2_IN1 */
98+
{PORTA_2, ADC0, GD_PIN_FUNC_ANALOG_CH(2)}, /* ADC0_IN2 */
99+
{PORTA_2_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(2)}, /* ADC1_IN2 */
100+
{PORTA_2_ALT2, ADC2, GD_PIN_FUNC_ANALOG_CH(2)}, /* ADC2_IN2 */
101+
{PORTA_3, ADC0, GD_PIN_FUNC_ANALOG_CH(3)}, /* ADC0_IN3 */
102+
{PORTA_3_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(3)}, /* ADC1_IN3 */
103+
{PORTA_3_ALT2, ADC2, GD_PIN_FUNC_ANALOG_CH(3)}, /* ADC2_IN3 */
104+
{PORTA_4, ADC0, GD_PIN_FUNC_ANALOG_CH(4)}, /* ADC0_IN4 */
105+
{PORTA_4_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(4)}, /* ADC1_IN4 */
106+
{PORTA_5, ADC0, GD_PIN_FUNC_ANALOG_CH(5)}, /* ADC0_IN5 */
107+
{PORTA_5_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(5)}, /* ADC1_IN5 */
108+
{PORTA_6, ADC0, GD_PIN_FUNC_ANALOG_CH(6)}, /* ADC0_IN6 */
109+
{PORTA_6_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(6)}, /* ADC1_IN6 */
110+
{PORTA_7, ADC0, GD_PIN_FUNC_ANALOG_CH(7)}, /* ADC0_IN7 */
111+
{PORTA_7_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(7)}, /* ADC1_IN7 */
112+
{PORTB_0, ADC0, GD_PIN_FUNC_ANALOG_CH(8)}, /* ADC0_IN8 */
113+
{PORTB_0_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(8)}, /* ADC1_IN8 */
114+
{PORTB_1, ADC0, GD_PIN_FUNC_ANALOG_CH(9)}, /* ADC0_IN9 */
115+
{PORTB_1_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(9)}, /* ADC1_IN9 */
116+
{ADC_TEMP, ADC0, GD_PIN_FUNC_ANALOG_CH(16)}, /* ADC0_IN16 */
117+
{ADC_VREF, ADC0, GD_PIN_FUNC_ANALOG_CH(17)}, /* ADC0_IN17 */
118+
{NC, NC, 0}
119+
};
120+
121+
/* DAC PinMap */
122+
const PinMap PinMap_DAC[] = {
123+
{PORTA_4, DAC, GD_PIN_FUNC_ANALOG_CH(0)}, /* DAC_OUT0 */
124+
{PORTA_5, DAC, GD_PIN_FUNC_ANALOG_CH(1)}, /* DAC_OUT1 */
125+
{NC, NC, 0}
126+
};
127+
128+
/* I2C_SDA PinMap */
129+
const PinMap PinMap_I2C_SDA[] = {
130+
{PORTB_7, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SDA */
131+
{PORTB_9, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SDA */
132+
{PORTB_11, I2C1, GPIO_MODE_AF_OD}, /* I2C1_SDA */
133+
{NC, NC, 0}
134+
};
135+
136+
/* I2C_SCL PinMap */
137+
const PinMap PinMap_I2C_SCL[] = {
138+
{PORTB_6, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SCL */
139+
{PORTB_8, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SCL */
140+
{PORTB_10, I2C1, GPIO_MODE_AF_OD}, /* I2C1_SCL */
141+
{NC, NC, 0}
142+
};
143+
144+
/* PWM PinMap */
145+
const PinMap PinMap_PWM[] = {
146+
{PORTA_0, TIMER1, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER1_CH0 */
147+
{PORTA_0_ALT1, TIMER4, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER4_CH0 */
148+
{PORTA_1, TIMER1, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER1_CH1 */
149+
{PORTA_1_ALT1, TIMER4, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER4_CH1 */
150+
{PORTA_2, TIMER1, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER1_CH2 */
151+
{PORTA_2_ALT1, TIMER4, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER4_CH2 */
152+
{PORTA_3, TIMER1, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER1_CH3 */
153+
{PORTA_3_ALT1, TIMER4, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER4_CH3 */
154+
{PORTA_6, TIMER2, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER2_CH0 */
155+
{PORTA_7, TIMER0, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER0_CH0_ON */
156+
{PORTA_7_ALT1, TIMER2, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER2_CH1 */
157+
{PORTA_8, TIMER0, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER0_CH0 */
158+
{PORTA_9, TIMER0, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER0_CH1 */
159+
{PORTA_10, TIMER0, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER0_CH2 */
160+
{PORTA_11, TIMER0, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER0_CH3 */
161+
{PORTA_15, TIMER1, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER1_CH0 */
162+
{PORTB_0, TIMER0, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER0_CH1_ON */
163+
{PORTB_0_ALT1, TIMER2, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER2_CH2 */
164+
{PORTB_1, TIMER0, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER0_CH2_ON */
165+
{PORTB_1_ALT1, TIMER2, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER2_CH3 */
166+
{PORTB_3, TIMER1, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER1_CH1 */
167+
{PORTB_4, TIMER2, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER2_CH0 */
168+
{PORTB_5, TIMER2, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER2_CH1 */
169+
{PORTB_6, TIMER3, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER3_CH0 */
170+
{PORTB_7, TIMER3, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER3_CH1 */
171+
{PORTB_8, TIMER3, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER3_CH2 */
172+
{PORTB_9, TIMER3, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER3_CH3 */
173+
{PORTB_10, TIMER1, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER1_CH2 */
174+
{PORTB_11, TIMER1, GD_PIN_FUNC_PWM(3, 0)}, /* TIMER1_CH3 */
175+
{PORTB_13, TIMER0, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER0_CH0_ON */
176+
{PORTB_14, TIMER0, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER0_CH1_ON */
177+
{PORTB_15, TIMER0, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER0_CH2_ON */
178+
{NC, NC, 0}
179+
};
180+
181+
/* UART_TX PinMap */
182+
const PinMap PinMap_UART_TX[] = {
183+
{PORTA_2, USART1, PIN_MODE_AF_PP}, /* USART1_TX */
184+
{PORTA_9, USART0, PIN_MODE_AF_PP}, /* USART0_TX */
185+
{PORTB_6, USART0, PIN_MODE_AF_PP}, /* USART0_TX */
186+
{PORTB_10, USART2, PIN_MODE_AF_PP}, /* USART2_TX */
187+
{NC, NC, 0}
188+
};
189+
190+
/* UART_RX PinMap */
191+
const PinMap PinMap_UART_RX[] = {
192+
{PORTA_3, USART1, GPIO_MODE_IN_FLOATING}, /* USART1_RX */
193+
{PORTA_10, USART0, GPIO_MODE_IN_FLOATING}, /* USART0_RX */
194+
{PORTB_7, USART0, GPIO_MODE_IN_FLOATING}, /* USART0_RX */
195+
{PORTB_11, USART2, GPIO_MODE_IN_FLOATING}, /* USART2_RX */
196+
{NC, NC, 0}
197+
};
198+
199+
/* UART_RTS PinMap */
200+
const PinMap PinMap_UART_RTS[] = {
201+
{PORTA_1, USART1, GPIO_MODE_AF_PP}, /* USART1_RTS */
202+
{PORTA_12, USART0, GPIO_MODE_AF_PP}, /* USART0_RTS */
203+
{PORTB_14, USART2, GPIO_MODE_AF_PP}, /* USART2_RTS */
204+
{NC, NC, 0}
205+
};
206+
207+
/* UART_CTS PinMap */
208+
const PinMap PinMap_UART_CTS[] = {
209+
{PORTA_0, USART1, GPIO_MODE_AF_PP}, /* USART1_CTS */
210+
{PORTA_11, USART0, GPIO_MODE_AF_PP}, /* USART0_CTS */
211+
{PORTB_13, USART2, GPIO_MODE_AF_PP}, /* USART2_CTS */
212+
{NC, NC, 0}
213+
};
214+
215+
/* SPI_MOSI PinMap */
216+
const PinMap PinMap_SPI_MOSI[] = {
217+
{PORTA_7, SPI0, GPIO_MODE_AF_PP}, /* SPI0_MOSI */
218+
{PORTB_5, SPI0, GPIO_MODE_AF_PP}, /* SPI0_MOSI */
219+
{PORTB_5_ALT1, SPI2, GPIO_MODE_AF_PP}, /* SPI2_MOSI */
220+
{PORTB_15, SPI1, GPIO_MODE_AF_PP}, /* SPI1_MOSI */
221+
{NC, NC, 0}
222+
};
223+
224+
/* SPI_MISO PinMap */
225+
const PinMap PinMap_SPI_MISO[] = {
226+
{PORTA_6, SPI0, GPIO_MODE_AF_PP}, /* SPI0_MISO */
227+
{PORTB_4, SPI0, GPIO_MODE_AF_PP}, /* SPI0_MISO */
228+
{PORTB_4_ALT1, SPI2, GPIO_MODE_AF_PP}, /* SPI2_MISO */
229+
{PORTB_14, SPI1, GPIO_MODE_AF_PP}, /* SPI1_MISO */
230+
{NC, NC, 0}
231+
};
232+
233+
/* SPI_SCLK PinMap */
234+
const PinMap PinMap_SPI_SCLK[] = {
235+
{PORTA_5, SPI0, GPIO_MODE_AF_PP}, /* SPI0_SCK */
236+
{PORTB_3, SPI0, GPIO_MODE_AF_PP}, /* SPI0_SCK */
237+
{PORTB_13, SPI1, GPIO_MODE_AF_PP}, /* SPI1_SCK */
238+
{NC, NC, 0}
239+
};
240+
241+
/* SPI_SSEL PinMap */
242+
const PinMap PinMap_SPI_SSEL[] = {
243+
{PORTA_4, SPI0, GPIO_MODE_AF_PP}, /* SPI0_NSS */
244+
{PORTA_4_ALT1, SPI2, GPIO_MODE_AF_PP}, /* SPI2_NSS */
245+
{PORTA_15, SPI0, GPIO_MODE_AF_PP}, /* SPI0_NSS */
246+
{PORTA_15_ALT1, SPI2, GPIO_MODE_AF_PP}, /* SPI2_NSS */
247+
{PORTB_12, SPI1, GPIO_MODE_AF_PP}, /* SPI1_NSS */
248+
{NC, NC, 0}
249+
};
250+
251+
/* CAN_RD PinMap */
252+
const PinMap PinMap_CAN_RD[] = {
253+
{PORTA_11, CAN0, GPIO_MODE_AF_PP}, /* CAN0_RX */
254+
{PORTB_8, CAN0, GPIO_MODE_AF_PP}, /* CAN0_RX */
255+
{NC, NC, 0}
256+
};
257+
258+
/* CAN_TD PinMap */
259+
const PinMap PinMap_CAN_TD[] = {
260+
{PORTA_12, CAN0, GPIO_MODE_AF_PP}, /* CAN0_TX */
261+
{PORTB_9, CAN0, GPIO_MODE_AF_PP}, /* CAN0_TX */
262+
{NC, NC, 0}
263+
};
264+

‎variants/GD32F303CB_GENERIC/PinNamesVar.h‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
PORTA_0_ALT1,
2+
PORTA_0_ALT2,
3+
PORTA_1_ALT1,
4+
PORTA_1_ALT2,
5+
PORTA_2_ALT1,
6+
PORTA_2_ALT2,
7+
PORTA_3_ALT1,
8+
PORTA_3_ALT2,
9+
PORTA_4_ALT1,
10+
PORTA_5_ALT1,
11+
PORTA_6_ALT1,
12+
PORTA_7_ALT1,
13+
PORTA_15_ALT1,
14+
PORTB_0_ALT1,
15+
PORTB_1_ALT1,
16+
PORTB_4_ALT1,
17+
PORTB_5_ALT1,

0 commit comments

Comments
 (0)