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maxgerhardtmaxgerhardt
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Downgrade SPL again so that CAN, DAC and ADC are properly referenced again
1 parent 2f8ba8b commit 4a394f5

53 files changed

Lines changed: 7495 additions & 2601 deletions

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‎system/GD32F1x0_firmware/CMSIS/GD/GD32F1x0/Include/gd32f1x0.h‎

Lines changed: 27 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,16 @@
11
/*!
2-
\file gd32f1x0.h
3-
\brief general definitions for gd32f1x0
2+
\file gd32f1x0.h
3+
\brief general definitions for gd32f1x0
44
55
\version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
66
\version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
77
\version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
88
\version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
99
\version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
10-
\version 2020-09-21, V3.3.0, firmware update for GD32F1x0(x=3,5,7,9)
11-
\version 2022-08-15, V3.4.0, firmware update for GD32F1x0(x=3,5)
1210
*/
1311

1412
/*
15-
Copyright (c) 2022, GigaDevice Semiconductor Inc.
13+
Copyright (c) 2019, GigaDevice Semiconductor Inc.
1614
1715
Redistribution and use in source and binary forms, with or without modification,
1816
are permitted provided that the following conditions are met:
@@ -53,6 +51,14 @@ OF SUCH DAMAGE.
5351
#error "Please select the target GD32F1x0 device used in your application (in gd32f1x0.h file)"
5452
#endif /* undefine GD32F1x0 tip */
5553

54+
/* define GD32F1x0 device category */
55+
#if (!defined (GD32F170_190))&&(!defined (GD32F130_150))
56+
#error "Please select GD32F1x0 device category( GD32F130_150 or GD32F170_190 )"
57+
#endif /* undefine GD32F170_190 or GD32F130_150 tip */
58+
#if (defined (GD32F170_190))&&(defined (GD32F130_150))
59+
#error "Please select one GD32F1x0 device category( GD32F130_150 or GD32F170_190 )"
60+
#endif /* define GD32F170_190 and GD32F130_150 tip */
61+
5662
/* define value of high speed crystal oscillator (HXTAL) in Hz */
5763
#if !defined (HXTAL_VALUE)
5864
#define HXTAL_VALUE ((uint32_t)8000000)
@@ -74,9 +80,15 @@ OF SUCH DAMAGE.
7480
#endif /* internal 8MHz RC oscillator startup timeout */
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7682
/* define value of internal RC oscillator for ADC in Hz */
83+
#ifdef GD32F170_190
84+
#if !defined (IRC28M_VALUE)
85+
#define IRC28M_VALUE ((uint32_t)28000000)
86+
#endif /* IRC28M for GD32F170_190 */
87+
#else
7788
#if !defined (IRC14M_VALUE)
7889
#define IRC14M_VALUE ((uint32_t)14000000)
7990
#endif /* IRC14M for GD32F130_150 */
91+
#endif /* GD32F170_190 */
8092

8193
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
8294
#if !defined (IRC40K_VALUE)
@@ -152,19 +164,24 @@ typedef enum IRQn
152164
USBD_LP_IRQn = 37, /*!< USBD_LP interrupt */
153165
USBD_HP_IRQn = 38, /*!< USBD_HP interrupt */
154166
USBDWakeUp_IRQChannel = 42, /*!< USBD_WKUP interrupt */
167+
CAN0_TX_IRQn = 43, /*!< CAN0 TX interrupt */
168+
CAN0_RX0_IRQn = 44, /*!< CAN0 RX0 interrupt */
169+
CAN0_RX1_IRQn = 45, /*!< CAN0 RX1 interrupt */
170+
CAN0_SCE_IRQn = 46, /*!< CAN0 SCE interrupt */
171+
SLCD_IRQn = 47, /*!< SLCD interrupt */
155172
DMA_Channel5_6_IRQn = 48, /*!< DMA1 channel 5 and channel 6 interrupts */
156173
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
174+
CAN1_TX_IRQn = 70, /*!< CAN1 TX interrupt */
175+
CAN1_RX0_IRQn = 71, /*!< CAN1 RX0 interrupt */
176+
CAN1_RX1_IRQn = 72, /*!< CAN1 RX1 interrupt */
177+
CAN1_SCE_IRQn = 73, /*!< CAN1 SCE interrupt */
157178
} IRQn_Type;
158179

159180
/* includes */
160181
#include "core_cm3.h"
161182
#include "system_gd32f1x0.h"
162183
#include <stdint.h>
163184

164-
/* HACKS for Arduino until we do proper peripheral pins generation */
165-
#define GPIO_AF_11 11
166-
#define GPIO_AF_9 9
167-
168185
/* enum definitions */
169186
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
170187
#include <stdbool.h>
@@ -237,4 +254,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
237254
#ifdef __cplusplus
238255
}
239256
#endif
240-
#endif
257+
#endif

‎system/GD32F1x0_firmware/GD32F1x0_standard_peripheral/Include/gd32f1x0_adc.h‎

Lines changed: 61 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,16 @@
11
/*!
2-
\file gd32f1x0_adc.h
3-
\brief definitions for the ADC
2+
\file gd32f1x0_adc.h
3+
\brief definitions for the ADC
44
55
\version 2014-12-26, V1.0.0, platform GD32F1x0(x=3,5)
66
\version 2016-01-15, V2.0.0, platform GD32F1x0(x=3,5,7,9)
77
\version 2016-04-30, V3.0.0, firmware update for GD32F1x0(x=3,5,7,9)
88
\version 2017-06-19, V3.1.0, firmware update for GD32F1x0(x=3,5,7,9)
99
\version 2019-11-20, V3.2.0, firmware update for GD32F1x0(x=3,5,7,9)
10-
\version 2020-09-21, V3.3.0, firmware update for GD32F1x0(x=3,5,7,9)
11-
\version 2022-08-15, V3.4.0, firmware update for GD32F1x0(x=3,5)
1210
*/
1311

1412
/*
15-
Copyright (c) 2022, GigaDevice Semiconductor Inc.
13+
Copyright (c) 2019, GigaDevice Semiconductor Inc.
1614
1715
Redistribution and use in source and binary forms, with or without modification,
1816
are permitted provided that the following conditions are met:
@@ -68,6 +66,10 @@ OF SUCH DAMAGE.
6866
#define ADC_IDATA3 REG32(ADC + 0x00000048U) /*!< ADC inserted data register 3 */
6967
#define ADC_RDATA REG32(ADC + 0x0000004CU) /*!< ADC regular data register */
7068

69+
#ifdef GD32F170_190
70+
#define ADC_OVSAMPCTL REG32(ADC + 0x00000080U) /*!< ADC oversampling control register */
71+
#endif /* GD32F170_190 */
72+
7173
/* bits definitions */
7274
/* ADC_STAT */
7375
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
@@ -90,6 +92,10 @@ OF SUCH DAMAGE.
9092
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
9193
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
9294

95+
#ifdef GD32F170_190
96+
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
97+
#endif /* GD32F170_190 */
98+
9399
/* ADC_CTL1 */
94100
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
95101
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
@@ -126,12 +132,20 @@ OF SUCH DAMAGE.
126132
#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */
127133
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
128134

129-
/* ADC_IDATAx x=0..3 */
135+
/* ADC_IDATAx x=0..3*/
130136
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */
131137

132-
/* ADC_RDATA */
138+
/* ADC_RDT */
133139
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */
134140

141+
#ifdef GD32F170_190
142+
/* ADC_OVCTL */
143+
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
144+
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
145+
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
146+
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
147+
#endif /* GD32F170_190 */
148+
135149
/* constants definitions */
136150
/* ADC flag definitions */
137151
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
@@ -207,6 +221,35 @@ OF SUCH DAMAGE.
207221
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
208222
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
209223

224+
#ifdef GD32F170_190
225+
/* ADC oversampling shift */
226+
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
227+
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
228+
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
229+
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
230+
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
231+
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
232+
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
233+
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
234+
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
235+
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
236+
237+
/* ADC oversampling ratio */
238+
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
239+
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
240+
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
241+
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
242+
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
243+
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
244+
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
245+
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
246+
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
247+
248+
/* ADC triggered oversampling */
249+
#define ADC_OVERSAMPLING_ALL_CONVERT (0U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
250+
#define ADC_OVERSAMPLING_ONE_CONVERT (1U) /*!< each oversampled conversion for a channel needs a trigger */
251+
#endif /* GD32F170_190 */
252+
210253
/* ADC channel group definitions */
211254
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */
212255
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */
@@ -322,4 +365,15 @@ void adc_watchdog_disable(void);
322365
/* configure ADC analog watchdog threshold */
323366
void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
324367

368+
#ifdef GD32F170_190
369+
/* configure ADC resolution */
370+
void adc_resolution_config(uint32_t resolution);
371+
/* configure ADC oversample mode */
372+
void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
373+
/* enable ADC oversample mode */
374+
void adc_oversample_mode_enable(void);
375+
/* disable ADC oversample mode */
376+
void adc_oversample_mode_disable(void);
377+
#endif /* GD32F170_190 */
378+
325379
#endif /* GD32F1X0_ADC_H */

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