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maxgerhardtmaxgerhardt
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Regnerate F103 variants, fix timers for GD32F10X_MD
1 parent c21b369 commit 407a303

188 files changed

Lines changed: 21861 additions & 2980 deletions

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‎cores/arduino/gd32/timer.c‎

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,13 @@ OF SUCH DAMAGE.
9191
#define NO_TIMER_13
9292
#endif
9393
#elif defined(GD32F10x)
94+
#if defined(GD32F10X_MD)
95+
#define NO_TIMER_4
96+
#define NO_TIMER_5
97+
#define NO_TIMER_6
98+
#define NO_TIMER_7
99+
#endif
100+
94101
#if !defined(GD32F10X_XD)
95102
#define TIMER7_IRQ_NAME TIMER7_UP_IRQn
96103
#define TIMER7_UP_IRQ_NAME TIMER7_UP_IRQn
@@ -1084,7 +1091,7 @@ IRQn_Type getTimerUpIrq(uint32_t tim)
10841091
IRQn = TIMER3_IRQn;
10851092
break;
10861093
#endif
1087-
#if defined(TIMER4)
1094+
#if defined(TIMER4) && !defined(NO_TIMER_4)
10881095
case (uint32_t)TIMER4:
10891096
IRQn = TIMER4_IRQn;
10901097
break;
@@ -1094,12 +1101,12 @@ IRQn_Type getTimerUpIrq(uint32_t tim)
10941101
IRQn = TIMER5_IRQ_Name;
10951102
break;
10961103
#endif
1097-
#if defined(TIMER6)
1104+
#if defined(TIMER6) && !defined(NO_TIMER_6)
10981105
case (uint32_t)TIMER6:
10991106
IRQn = TIMER6_IRQn;
11001107
break;
11011108
#endif
1102-
#if defined(TIMER7)
1109+
#if defined(TIMER7) && !defined(NO_TIMER_7)
11031110
case (uint32_t)TIMER7:
11041111
IRQn = TIMER7_UP_IRQ_NAME;
11051112
break;
@@ -1196,7 +1203,7 @@ IRQn_Type getTimerCCIrq(uint32_t tim)
11961203
IRQn = TIMER3_IRQn;
11971204
break;
11981205
#endif
1199-
#if defined(TIMER4)
1206+
#if defined(TIMER4) && !defined(NO_TIMER_4)
12001207
case (uint32_t)TIMER4:
12011208
IRQn = TIMER4_IRQn;
12021209
break;
@@ -1206,12 +1213,12 @@ IRQn_Type getTimerCCIrq(uint32_t tim)
12061213
IRQn = TIMER5_IRQ_Name;
12071214
break;
12081215
#endif
1209-
#if defined(TIMER6)
1216+
#if defined(TIMER6) && !defined(NO_TIMER_6)
12101217
case (uint32_t)TIMER6:
12111218
IRQn = TIMER6_IRQn;
12121219
break;
12131220
#endif
1214-
#if defined(TIMER7)
1221+
#if defined(TIMER7) && !defined(NO_TIMER_7)
12151222
case (uint32_t)TIMER7:
12161223
IRQn = TIMER7_IRQ_NAME;
12171224
break;

‎system/GD32F10x_firmware/CMSIS/GD/GD32F10x/Source/system_gd32f10x.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,9 @@ OF SUCH DAMAGE.
4242
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
4343
#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
4444

45-
//#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
45+
#ifndef VECT_TAB_OFFSET
46+
#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
47+
#endif
4648

4749
/* select a system clock by uncommenting the following line */
4850
/* use IRC8M */

‎variants/GD32F103C4_GENERIC/PeripheralNames.h‎

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
1+
/*
2+
Copyright (c) 2021, CommunityGD32Cores
3+
4+
Redistribution and use in source and binary forms, with or without modification,
5+
are permitted provided that the following conditions are met:
6+
7+
1. Redistributions of source code must retain the above copyright notice, this
8+
list of conditions and the following disclaimer.
9+
2. Redistributions in binary form must reproduce the above copyright notice,
10+
this list of conditions and the following disclaimer in the documentation
11+
and/or other materials provided with the distribution.
12+
3. Neither the name of the copyright holder nor the names of its contributors
13+
may be used to endorse or promote products derived from this software without
14+
specific prior written permission.
15+
16+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18+
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19+
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
20+
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21+
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
22+
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23+
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24+
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
25+
OF SUCH DAMAGE.
26+
*/
27+
28+
#ifndef PERIPHERALNAMES_H
29+
#define PERIPHERALNAMES_H
30+
31+
#include "gd32xxyy.h"
32+
33+
#ifdef __cplusplus
34+
extern "C" {
35+
#endif
36+
37+
typedef enum {
38+
ADC_0 = (int)ADC0,
39+
ADC_1 = (int)ADC1,
40+
ADC_2 = (int)ADC2
41+
} ADCName;
42+
43+
/* no DAC pins */
44+
45+
typedef enum {
46+
UART_0 = (int)USART0,
47+
UART_1 = (int)USART1
48+
} UARTName;
49+
50+
typedef enum {
51+
SPI_0 = (int)SPI0
52+
} SPIName;
53+
54+
typedef enum {
55+
I2C_0 = (int)I2C0
56+
} I2CName;
57+
58+
typedef enum {
59+
PWM_0 = (int)TIMER0,
60+
PWM_1 = (int)TIMER1,
61+
PWM_2 = (int)TIMER2,
62+
PWM_4 = (int)TIMER4
63+
} PWMName;
64+
65+
66+
#ifdef __cplusplus
67+
}
68+
#endif
69+
70+
#endif

‎variants/GD32F103C4_GENERIC/PeripheralPins.c‎

Lines changed: 252 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,252 @@
1+
/*
2+
Copyright (c) 2020, GigaDevice Semiconductor Inc.
3+
4+
Redistribution and use in source and binary forms, with or without modification,
5+
are permitted provided that the following conditions are met:
6+
7+
1. Redistributions of source code must retain the above copyright notice, this
8+
list of conditions and the following disclaimer.
9+
2. Redistributions in binary form must reproduce the above copyright notice,
10+
this list of conditions and the following disclaimer in the documentation
11+
and/or other materials provided with the distribution.
12+
3. Neither the name of the copyright holder nor the names of its contributors
13+
may be used to endorse or promote products derived from this software without
14+
specific prior written permission.
15+
16+
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17+
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18+
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19+
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
20+
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21+
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
22+
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23+
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24+
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
25+
OF SUCH DAMAGE.
26+
*/
27+
28+
#include "gd32xxyy.h"
29+
#include "PeripheralPins.h"
30+
31+
/* void pin_function(PinName pin, int function);
32+
configure the speed, mode,and remap function of pins
33+
the parameter function contains the configuration information,show as below
34+
bit 0:2 gpio mode
35+
bit 3:8 remap
36+
bit 9:10 gpio speed
37+
bit 11:15 adc /timer channel
38+
*/
39+
40+
/* pin descriptions only reference the index in the array, so
41+
* to get e.g. AF11 one must give it index = 9. provide
42+
* convenience macros here.
43+
* for all other arrays, the value is also equivalent to the index,
44+
* so there doesn't need to be anything done more.
45+
*/
46+
47+
/* Generated remapping names */
48+
49+
const int GD_GPIO_REMAP[] = {
50+
0x00000000,
51+
#if __has_include("gd32f10x_remap.h")
52+
#define __REMAP_NAME__(remap) GPIO_ ## remap,
53+
#include "gd32f10x_remap.h"
54+
#undef __REMAP_NAME__
55+
#endif
56+
};
57+
58+
enum GD_GPIO_REMAP_NAME {
59+
REMAP_NONE = 0U,
60+
#if __has_include("gd32f10x_remap.h")
61+
#define __REMAP_NAME__(remap) remap,
62+
#include "gd32f10x_remap.h"
63+
#undef __REMAP_NAME__
64+
#define __REMAP_NAME__(remap) DISABLE_ ## remap = GPIO_ ## remap | (1U << 6),
65+
#include "gd32f10x_remap.h"
66+
#undef __REMAP_NAME__
67+
#endif
68+
};
69+
70+
/* GPIO MODE */
71+
const int GD_GPIO_MODE[] = {
72+
GPIO_MODE_AIN, /* 0 INPUT_ANALOG */
73+
GPIO_MODE_IN_FLOATING, /* 1 INPUT */
74+
GPIO_MODE_IPD, /* 2 INPUT_PULLDOWN */
75+
GPIO_MODE_IPU, /* 3 INPUT_PULLUP */
76+
GPIO_MODE_OUT_OD, /* 4 OUTPUT_OPEN_DRAIN */
77+
GPIO_MODE_OUT_PP, /* 5 OUTPUT */
78+
GPIO_MODE_AF_OD, /* 6 ALT FUNC OPEN DRAIN */
79+
GPIO_MODE_AF_PP, /* 7 ALT FUNC PUSH PULL */
80+
};
81+
82+
/* GPIO SPEED */
83+
const int GD_GPIO_SPEED[] = {
84+
GPIO_OSPEED_2MHZ, /* 0 */
85+
GPIO_OSPEED_10MHZ, /* 1 */
86+
0, /* 2 (unused) */
87+
GPIO_OSPEED_50MHZ, /* 3 */
88+
};
89+
90+
/* ADC PinMap */
91+
const PinMap PinMap_ADC[] = {
92+
{PORTA_0, ADC0, GD_PIN_FUNC_ANALOG_CH(0)}, /* ADC0_IN0 */
93+
{PORTA_0_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(0)}, /* ADC1_IN0 */
94+
{PORTA_0_ALT2, ADC2, GD_PIN_FUNC_ANALOG_CH(0)}, /* ADC2_IN0 */
95+
{PORTA_1, ADC0, GD_PIN_FUNC_ANALOG_CH(1)}, /* ADC0_IN1 */
96+
{PORTA_1_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(1)}, /* ADC1_IN1 */
97+
{PORTA_1_ALT2, ADC2, GD_PIN_FUNC_ANALOG_CH(1)}, /* ADC2_IN1 */
98+
{PORTA_2, ADC0, GD_PIN_FUNC_ANALOG_CH(2)}, /* ADC0_IN2 */
99+
{PORTA_2_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(2)}, /* ADC1_IN2 */
100+
{PORTA_2_ALT2, ADC2, GD_PIN_FUNC_ANALOG_CH(2)}, /* ADC2_IN2 */
101+
{PORTA_3, ADC0, GD_PIN_FUNC_ANALOG_CH(3)}, /* ADC0_IN3 */
102+
{PORTA_3_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(3)}, /* ADC1_IN3 */
103+
{PORTA_3_ALT2, ADC2, GD_PIN_FUNC_ANALOG_CH(3)}, /* ADC2_IN3 */
104+
{PORTA_4, ADC0, GD_PIN_FUNC_ANALOG_CH(4)}, /* ADC0_IN4 */
105+
{PORTA_4_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(4)}, /* ADC1_IN4 */
106+
{PORTA_5, ADC0, GD_PIN_FUNC_ANALOG_CH(5)}, /* ADC0_IN5 */
107+
{PORTA_5_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(5)}, /* ADC1_IN5 */
108+
{PORTA_6, ADC0, GD_PIN_FUNC_ANALOG_CH(6)}, /* ADC0_IN6 */
109+
{PORTA_6_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(6)}, /* ADC1_IN6 */
110+
{PORTA_7, ADC0, GD_PIN_FUNC_ANALOG_CH(7)}, /* ADC0_IN7 */
111+
{PORTA_7_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(7)}, /* ADC1_IN7 */
112+
{PORTB_0, ADC0, GD_PIN_FUNC_ANALOG_CH(8)}, /* ADC0_IN8 */
113+
{PORTB_0_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(8)}, /* ADC1_IN8 */
114+
{PORTB_1, ADC0, GD_PIN_FUNC_ANALOG_CH(9)}, /* ADC0_IN9 */
115+
{PORTB_1_ALT1, ADC1, GD_PIN_FUNC_ANALOG_CH(9)}, /* ADC1_IN9 */
116+
{ADC_TEMP, ADC0, GD_PIN_FUNC_ANALOG_CH(16)}, /* ADC0_IN16 */
117+
{ADC_VREF, ADC0, GD_PIN_FUNC_ANALOG_CH(17)}, /* ADC0_IN17 */
118+
{NC, NC, 0}
119+
};
120+
121+
/* DAC PinMap */
122+
const PinMap PinMap_DAC[] = {
123+
{NC, NC, 0}
124+
};
125+
126+
/* I2C_SDA PinMap */
127+
const PinMap PinMap_I2C_SDA[] = {
128+
{PORTB_7, I2C0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_I2C0_REMAP)}, /* I2C0_SDA */
129+
{PORTB_9, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SDA */
130+
{NC, NC, 0}
131+
};
132+
133+
/* I2C_SCL PinMap */
134+
const PinMap PinMap_I2C_SCL[] = {
135+
{PORTB_6, I2C0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_I2C0_REMAP)}, /* I2C0_SCL */
136+
{PORTB_8, I2C0, GPIO_MODE_AF_OD}, /* I2C0_SCL */
137+
{NC, NC, 0}
138+
};
139+
140+
/* PWM PinMap */
141+
const PinMap PinMap_PWM[] = {
142+
{PORTA_0, TIMER1, GD_PIN_FUNC_PWM(0, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH0 */
143+
{PORTA_0_ALT1, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH0 */
144+
{PORTA_0_ALT2, TIMER4, GD_PIN_FUNC_PWM(0, 0)}, /* TIMER4_CH0 */
145+
{PORTA_1, TIMER1, GD_PIN_FUNC_PWM(1, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH1 */
146+
{PORTA_1_ALT1, TIMER1, GD_PIN_FUNC_PWM(1, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH1 */
147+
{PORTA_2, TIMER1, GD_PIN_FUNC_PWM(2, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH2 */
148+
{PORTA_2_ALT1, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH2 */
149+
{PORTA_3, TIMER1, GD_PIN_FUNC_PWM(3, DISABLE_TIMER1_FULL_REMAP)}, /* TIMER1_CH3 */
150+
{PORTA_3_ALT1, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH3 */
151+
{PORTA_6, TIMER2, GD_PIN_FUNC_PWM(0, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH0 */
152+
{PORTA_7, TIMER0, GD_PIN_FUNC_PWM(0, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH0_ON */
153+
{PORTA_7_ALT1, TIMER2, GD_PIN_FUNC_PWM(1, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH1 */
154+
{PORTA_8, TIMER0, GD_PIN_FUNC_PWM(0, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH0 */
155+
{PORTA_8_ALT1, TIMER0, GD_PIN_FUNC_PWM(0, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH0 */
156+
{PORTA_9, TIMER0, GD_PIN_FUNC_PWM(1, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH1 */
157+
{PORTA_9_ALT1, TIMER0, GD_PIN_FUNC_PWM(1, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH1 */
158+
{PORTA_10, TIMER0, GD_PIN_FUNC_PWM(2, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH2 */
159+
{PORTA_10_ALT1, TIMER0, GD_PIN_FUNC_PWM(2, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH2 */
160+
{PORTA_11, TIMER0, GD_PIN_FUNC_PWM(3, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH3 */
161+
{PORTA_11_ALT1, TIMER0, GD_PIN_FUNC_PWM(3, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH3 */
162+
{PORTA_15, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_PARTIAL_REMAP0)}, /* TIMER1_CH0 */
163+
{PORTA_15_ALT1, TIMER1, GD_PIN_FUNC_PWM(0, TIMER1_FULL_REMAP)}, /* TIMER1_CH0 */
164+
{PORTB_0, TIMER0, GD_PIN_FUNC_PWM(1, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH1_ON */
165+
{PORTB_0_ALT1, TIMER2, GD_PIN_FUNC_PWM(2, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH2 */
166+
{PORTB_0_ALT2, TIMER2, GD_PIN_FUNC_PWM(2, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH2 */
167+
{PORTB_1, TIMER0, GD_PIN_FUNC_PWM(2, TIMER0_PARTIAL_REMAP)}, /* TIMER0_CH2_ON */
168+
{PORTB_1_ALT1, TIMER2, GD_PIN_FUNC_PWM(3, DISABLE_TIMER2_FULL_REMAP)}, /* TIMER2_CH3 */
169+
{PORTB_1_ALT2, TIMER2, GD_PIN_FUNC_PWM(3, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH3 */
170+
{PORTB_4, TIMER2, GD_PIN_FUNC_PWM(0, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH0 */
171+
{PORTB_5, TIMER2, GD_PIN_FUNC_PWM(1, TIMER2_PARTIAL_REMAP)}, /* TIMER2_CH1 */
172+
{PORTB_10, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH2 */
173+
{PORTB_10_ALT1, TIMER1, GD_PIN_FUNC_PWM(2, TIMER1_FULL_REMAP)}, /* TIMER1_CH2 */
174+
{PORTB_11, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_PARTIAL_REMAP1)}, /* TIMER1_CH3 */
175+
{PORTB_11_ALT1, TIMER1, GD_PIN_FUNC_PWM(3, TIMER1_FULL_REMAP)}, /* TIMER1_CH3 */
176+
{PORTB_13, TIMER0, GD_PIN_FUNC_PWM(0, DISABLE_TIMER0_FULL_REMAP)}, /* TIMER0_CH0_ON */
177+
{PORTB_14, TIMER0, GD_PIN_FUNC_PWM(1, 0)}, /* TIMER0_CH1_ON */
178+
{PORTB_15, TIMER0, GD_PIN_FUNC_PWM(2, 0)}, /* TIMER0_CH2_ON */
179+
{NC, NC, 0}
180+
};
181+
182+
/* UART_TX PinMap */
183+
const PinMap PinMap_UART_TX[] = {
184+
{PORTA_2, USART1, PIN_MODE_AF_PP}, /* USART1_TX */
185+
{PORTA_9, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_USART0_REMAP)}, /* USART0_TX */
186+
{PORTB_6, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, USART0_REMAP)}, /* USART0_TX */
187+
{NC, NC, 0}
188+
};
189+
190+
/* UART_RX PinMap */
191+
const PinMap PinMap_UART_RX[] = {
192+
{PORTA_3, USART1, GPIO_MODE_IN_FLOATING}, /* USART1_RX */
193+
{PORTA_10, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_USART0_REMAP)}, /* USART0_RX */
194+
{PORTB_7, USART0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, USART0_REMAP)}, /* USART0_RX */
195+
{NC, NC, 0}
196+
};
197+
198+
/* UART_RTS PinMap */
199+
const PinMap PinMap_UART_RTS[] = {
200+
{PORTA_1, USART1, GPIO_MODE_AF_PP}, /* USART1_RTS */
201+
{PORTA_12, USART0, GPIO_MODE_AF_PP}, /* USART0_RTS */
202+
{NC, NC, 0}
203+
};
204+
205+
/* UART_CTS PinMap */
206+
const PinMap PinMap_UART_CTS[] = {
207+
{PORTA_0, USART1, GPIO_MODE_AF_PP}, /* USART1_CTS */
208+
{PORTA_11, USART0, GPIO_MODE_AF_PP}, /* USART0_CTS */
209+
{NC, NC, 0}
210+
};
211+
212+
/* SPI_MOSI PinMap */
213+
const PinMap PinMap_SPI_MOSI[] = {
214+
{PORTA_7, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_MOSI */
215+
{PORTB_5, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_MOSI */
216+
{NC, NC, 0}
217+
};
218+
219+
/* SPI_MISO PinMap */
220+
const PinMap PinMap_SPI_MISO[] = {
221+
{PORTA_6, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_MISO */
222+
{PORTB_4, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_MISO */
223+
{NC, NC, 0}
224+
};
225+
226+
/* SPI_SCLK PinMap */
227+
const PinMap PinMap_SPI_SCLK[] = {
228+
{PORTA_5, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_SCK */
229+
{NC, NC, 0}
230+
};
231+
232+
/* SPI_SSEL PinMap */
233+
const PinMap PinMap_SPI_SSEL[] = {
234+
{PORTA_4, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, DISABLE_SPI0_REMAP)}, /* SPI0_NSS */
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{PORTA_15, SPI0, GD_PIN_FUNCTION5(PIN_MODE_AF, PIN_OTYPE_PP, PIN_PUPD_PULLUP, SPI0_REMAP)}, /* SPI0_NSS */
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{NC, NC, 0}
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};
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/* CAN_RD PinMap */
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const PinMap PinMap_CAN_RD[] = {
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{PORTA_11, CAN0, GPIO_MODE_AF_PP}, /* CAN0_RX */
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{PORTB_8, CAN0, GPIO_MODE_AF_PP}, /* CAN0_RX */
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{NC, NC, 0}
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};
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/* CAN_TD PinMap */
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const PinMap PinMap_CAN_TD[] = {
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{PORTA_12, CAN0, GPIO_MODE_AF_PP}, /* CAN0_TX */
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{PORTB_9, CAN0, GPIO_MODE_AF_PP}, /* CAN0_TX */
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{NC, NC, 0}
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};
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