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 Marco Caccamo's Home Page Marco Caccamo Professor Department of Computer Science University of Illinois Office: 4118 SC Siebel Center for Computer Science 201 N. Goodwin Avenue Urbana, IL 61801 Phone: 217-244-0528 Fax: 217-244-6500 mcaccamo "at" illinois.edu Marco Caccamo graduated (summa cum laude) in Computer Engineering at University of Pisa on July 1997. He received a Ph.D. in Computer Engineering from Scuola Superiore Sant'Anna ( SSSUP ) in January 2002. He is a professor in the Department of Computer Science, with courtesy appointments in the Department of Electrical and Computer Engineering and Department of Aerospace Engineering at the University of Illinois at Urbana-Champaign (UIUC). He is the Principal Investigator at the "Real Time and Embedded System Laboratory" at UIUC. In broad terms, his research interests are centered on the area of embedded systems. He has worked in close collaboration with avionics, farming, and automotive industries developing innovative software architectures and toolkits for the design automation of embedded digital controllers, and low-level resource management solutions for real-time operating systems running on multicore architectures. More recently, he has begun to investigate real-time, security, and robustness problems in the software architecture of unmanned aerial vehicles (UAVs). See recent article about this work and take a look at one of our UAV testbed ). Current Students: Fardin Abdi (Ph.D) Ayoosh Bansal (Ph.D) Or Dantsker (Ph.D) Mirco Theile (Ph.D) Rohan Tabish (Ph.D) Jayati Singh (visiting student) Honors & Awards: IEEE Fellow, "For contributions to the theory and applications of hard real-time multicore computing", 2018 Alexander von Humboldt Professorship , 2018 ( TUM ) Paper of the month and Editor's pick of the year 2016, IEEE Transactions on Computers Engineering Council Outstanding Advising Award (Spring 2015) Best Student Paper Award (RTAS 2013) Ranked as excellent teacher by students of CS598MC (Fall 2007, Spring 2012, Fall 2014) IEEE Tech. Committee on RT Systems Service Award (for serving as General Chair of CPSWeek 2011) Best Paper Award (RTCSA 2008) Best Student Paper Award (RTSS 2004) NSF CAREER Award (2003) Professional Activities: Member of 2018 IEEE Computer Society Fellows Committee, Chair of WiP session at RTEST'18 conference, Associate Editor of IEEE Transactions on Computers (TC), 2017-18, Co-chair of Second TCRTS Workshop on Certifiable Multicore Avionics and Automotive Systems (CMAAS'17) General Chair of IEEE Real-Time Systems Symposium (RTSS'16), Program Chair of IEEE Real-Time Systems Symposium (RTSS'15), General Chair of Cyber Physical Systems Week (CPSWeek) 2011, General Chair of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'11), Program Chair of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'10), Chair of WiP session at ECRTS'08 conference. Publications Teaching: CS424 (Real-Time Systems) CS598mc (Special topics: Cyber-Physical Systems) CS431 (Embedded Systems Architecture and Software) CS241 (Systems Programming) Research Projects sponsored by NSF: Hybrid hardware-software architecture for reconfigurable real-time systems : m odern SoC devices enable the development of hybrid embedded systems where sofware tasks, running on a traditional CPU, can coexist with hardware tasks running on reconfigurable hardware (FPGA). The main goal of this research is to develop a SoC real-time computing architecture that integrates hardware and software execution in a transparent manner, and can support QoS adaptation by means of partial reconfiguration of modern FPGA devices. CSR: Memory-Centric Real-Time Scheduling for Multicore Embedded Systems . M. Caccamo (PI), Co-PI: L. Sha , National Science Foundation, CNS-1219064 In modern automotive and avionics applications, the use of multiple sensors and especially real-time imaging sensors creates unprecedented workloads. From a computational perspective, multicore architectures have become mainstream; however, as a multicore chip is expected to process increasing volumes of data in real-time, the memory hierarchy becomes the bottleneck resource. In the worst case, task execution times can grow linearly with the number of cores in the system. This research aims at laying foundations for a modern memory-centric real-time scheduling theory that can effectively co-schedule the use of the memory hierarchy, the cores, and the on-chip network, including the I/O channels. According to the vision of Memory-Centric Scheduling, when the memory hierarchy is the system bottleneck, memory accesses should be scheduled to achieve high memory utilization. Performance of a real-time multicore system should be measured in terms of schedulable memory utilization rather than just core utilization. Ideally, the real-time constraints should be met as long as total memory utilization of all real-time applications (across all the cores contending for shared memory) is below 100%. See the presentation titled " The Migration of Safety-Critical RT Software to Multicore " ( pptx ) for learning about major findings of this research. CSR: Multicore Real Time Virtual Partitions . L. Sha (PI), Co-PIs: M. Caccamo, T. Abdelzaher, National Science Foundation, CNS-1302563 Embedded industry has a large body of certified real time safety and mission critical software developed for single core chips, using certification procedures developed for single core systems. Now, those chips are becoming obsolete, and newer chips are being designed with slower clock rates but multiple cores. Multicore computer platforms pose new challenges for hard real-time systems, because of the complex temporal coupling between processing cores' shared last level cache, shared memory and I/O bandwidth. This research aims at tackling this industry-wide challenge by introducing the notion of real time virtual partitions (RTVPs), each of which can be treated as a stand-alone single-core chip from the point of view of real-time schedulability analysis and certification process. Without a technology like RTVP, the change of workload in one core could adversely impact the schedulability of tasks in other cores, triggering the recertification of applications running on other cores. The time and costs of such recertification is economically unsustainable. This problem is especially critical for the avionic industry. Single Core Equivalence (SCE): a cost-effective solution for the transition of safety-critical RT software from single-core to multi-core commodity platforms. CPS: Breakthrough: Solar-powered, Long-endurance UAV for Real-time Onboard Data Processing . M. Caccamo (PI), National Science Foundation, CNS-1646383 Given the wide range of possibilities, unmanned aerial vehicles (UAVs) represent a growing market in CPS and they are perceived as an "enabling technology" to re-consider the human involvement in many military and civil applications on a global scale. One of the major challenges in enabling this growth is UAV endurance. This is directly related to the amount of energy available to the UAV to perform its mission. This proposal looks to increase UAV endurance by trading off UAV performance with energy efficient computing. This requires mapping of mission and goals into energy needs and computational requirements. The goal of the project is to show that this trade can enable long-duration flight especially when solar energy is utilized as a primary energy source. The ambitious plan is to develop a light weight and efficient aircraft capable of maneuver-aware power adaptation and real-time video/sensor acquisition and processing for up to 12 hours of continuous flight (this limit being set by daylight hours). This project aims to expanding the theoretical and practical foundations for the design and integration of UAVs capable of real-time sensing and processing from an array of visual, acoustic and other sensors. For more details, please check the project web-site . Former Research Projects sponsored by NSF Former Students: Renato Mancuso (Ph.D'17, Assistant Professor at Boston Univ.) Suraj Venkat (MS'17) Andrew Louis (MS'17, Embedded Software Engineer at Bell) Stanley Bak (Ph.D'13, Research Scientist, Air Force Research Lab (AFRL), Rome, NY) Roman Dudko (MS'12, Google) Bach Duy Bui (Ph.D'11, SW Engineer at Yahoo!, UIUC Research Center) Rodolfo Pellizzoni (Ph.D'10, Associate Professor Univ. of Waterloo) Olugbemiga Adekunle (MS'10, Instructor at Blue Ridge Community College, VA) Deepti K. Chivukula (MS'10, Associate, Firm Risk Management @ Morgan Stanley) Chin F. Cheah (MS'07, Citadel Investment Group) Sathish Gopalakrishnan ( Ph.D'05, Associate Professor UBC) Spencer Hoke (MS'05, Garmin) Deepu C. Thomas (MS'04, Microsoft) Simone Giannecchini (MS'03, Geosolutions, Italy) accesses since June 2005