makefile.cocotb

# Makefile

# defaults
SIM ?= questa
TOPLEVEL_LANG ?= verilog
GUI ?= 1

LIBRARIES = work altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver fourteennm_ver fourteennm_ct1_ver dsp_prime_10 tensor_core_accu tensor_core_entry_bf12 tensor_core_bf12 tensor_core_start_bf12
SIM_ARGS += $(addprefix -L ,$(LIBRARIES))
SCRIPT_FILE += $(PWD)/mentor/msim_setup.tcl

ifeq ($(GUI),1)
	PRE_CMD += $(PWD)/tensor_core_wrapper_tb_add_wave.do
endif

# use VHDL_SOURCES for VHDL files
# intel ip and util design
VERILOG_SOURCES += $(PWD)/tb/fourteennm_atoms.sv
VERILOG_SOURCES += $(PWD)/../src/main/sverilog/blk_delay_core.sv
VERILOG_SOURCES += $(PWD)/../src/main/sverilog/out_asym_fifo.sv
# specify spmm core src path here
VERILOG_SOURCES += $(PWD)/../src/generated_spmm_core_6x12x8/*.v


# specify top design and test module
TOPLEVEL = tensor_core_array_wrapper
MODULE = tensor_core_wrapper_tb_coco

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim

clean::
	\rm -rf libraries
	\rm -rf transcript
	\rm -rf *.wlf