- Synchronous
- Serial
- Full duplex
- Master-slave architecture
- Single master multiple slave
- For interfacing microcontrollers with sensors or other modules (SD cards, EEPROMs, etc)
- One clock pin
SCLK: Sent by master to slaves- Data is sample on the rising edge of clock
- 2 data pins
MOSI: Master Out Slave InMISO: Master In Slave Out
- Select pins for each slave
SS: Slave select (ActiveLOW)
- Any number of bits can be sent or received - no concept of packets
Often, peripheral devices call MOSI as SDI (Serial Data In) and MISO as SDO (Serial Data Out), and Slave select as CS (Chip Select)
Note : Most of the time, chip select is not a part of the SPI hardware interface and is controlled using other GPIO pins.
The SPI protocol is implemented using shift registers.
So, the SPI protocol acts like a ring buffer in this case. The slave buffer is read by the controller when CS pin goes high.
Using multiple slaves with seperate slave select pins
If we are short on pins, and since we know that the slaves use shift register, we can use "daisy chaining" with a single pin. The shift register values are only read when CS pin goes high. So, in the case below, we can maintain CS pin low for transferring 3 words which are shifted over one-by-one. We need to send the word to the last slave in the chain first.
