From d9d0fa8a76740f5ac5c00c0345b73c58d93b19a0 Mon Sep 17 00:00:00 2001 From: Pat Rogers Date: Thu, 7 May 2026 12:22:27 -0500 Subject: [PATCH] Correct GPIO config for SDRAM GPIO pins at higher SDCLK speeds With a SYSCLK at 216MHz, the SDCLK is 108MHz. A GPIO output speed of Speed_50MHz is insufficient for a 108MHz signal. At 108MHz a GPIO output speed of 50MHZ is borderline, and can (does) cause signal integrity issues, especially on a board with marginal silicon. It should be Speed_100MHz or Speed_Very_High (the STM32F7 HAL uses GPIO_SPEED_FREQ_VERY_HIGH for FMC pins). --- boards/stm32_common/sdram/stm32-sdram.adb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/boards/stm32_common/sdram/stm32-sdram.adb b/boards/stm32_common/sdram/stm32-sdram.adb index 9b7250a24..aca65c046 100644 --- a/boards/stm32_common/sdram/stm32-sdram.adb +++ b/boards/stm32_common/sdram/stm32-sdram.adb @@ -58,7 +58,7 @@ package body STM32.SDRAM is Configure_IO (SDRAM_PINS, (Mode => Mode_AF, AF => GPIO_AF_FMC_12, - AF_Speed => Speed_50MHz, + AF_Speed => Speed_Very_High, AF_Output_Type => Push_Pull, Resistors => Pull_Up)); @@ -243,5 +243,4 @@ package body STM32.SDRAM is return Ret; end Reserve; - end STM32.SDRAM;