From 875ea067bf1b921b41e49741dd0fbff0d56b979f Mon Sep 17 00:00:00 2001 From: Pat Rogers Date: Sat, 28 Mar 2026 11:55:51 -0500 Subject: [PATCH 1/3] new general MPU config facility; also fixes LTDC slew --- arch/ARM/cortex_m/src/cortex_m-mpu.adb | 127 ++++++++++++++++++++++++ arch/ARM/cortex_m/src/cortex_m-mpu.ads | 129 +++++++++++++++++++++++++ 2 files changed, 256 insertions(+) create mode 100644 arch/ARM/cortex_m/src/cortex_m-mpu.adb create mode 100644 arch/ARM/cortex_m/src/cortex_m-mpu.ads diff --git a/arch/ARM/cortex_m/src/cortex_m-mpu.adb b/arch/ARM/cortex_m/src/cortex_m-mpu.adb new file mode 100644 index 000000000..332b34363 --- /dev/null +++ b/arch/ARM/cortex_m/src/cortex_m-mpu.adb @@ -0,0 +1,127 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2026, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +with System.Machine_Code; use System.Machine_Code; +with Ada.Unchecked_Conversion; + +with Cortex_M_SVD.MPU; use Cortex_M_SVD.MPU; + +package body Cortex_M.MPU is + + procedure DSB with Inline_Always; + procedure ISB with Inline_Always; + + procedure DSB is + begin + Asm ("dsb", Volatile => True); + end DSB; + + procedure ISB is + begin + Asm ("isb", Volatile => True); + end ISB; + + ------------ + -- Enable -- + ------------ + + procedure Enable (Control : MPU_Control) is + begin + MPU_Periph.CTRL := (ENABLE => True, + HFNMIENA => Control.Hard_Fault_NMI_Enable, + PRIVDEFENA => Control.Privileged_Default, + others => <>); + DSB; + ISB; + end Enable; + + ------------- + -- Disable -- + ------------- + + procedure Disable is + begin + DSB; + MPU_Periph.CTRL := (ENABLE => False, + HFNMIENA => False, + PRIVDEFENA => False, + others => <>); + ISB; + end Disable; + + ---------------------- + -- Configure_Region -- + ---------------------- + + procedure Configure_Region (Config : Region_Configuration) is + + function To_UInt32 is new Ada.Unchecked_Conversion + (System.Address, HAL.UInt32); + + use HAL; + + Addr : constant UInt32 := To_UInt32 (Config.Base_Address); + + Size_Val : constant UInt5 := Region_Size'Enum_Rep (Config.Size); + AP_Val : constant UInt3 := Access_Permission'Enum_Rep (Config.Access_Permission); + begin + -- Select the region + MPU_Periph.RNR := (REGION => HAL.UInt8 (Config.Number), others => <>); + + -- Set base address + MPU_Periph.RBAR := (ADDR => UInt27 (Addr / 2**5), VALID => False, REGION => 0); + + -- Set attributes and enable + MPU_Periph.RASR := (ENABLE => True, + SIZE => Size_Val, + SRD => (As_Array => False, Val => Config.Subregion_Disable), + B => Config.Bufferable, + C => Config.Cacheable, + S => Config.Shareable, + TEX => Config.TEX, + AP => Cortex_M_SVD.MPU.RASR_AP_Field'Val (AP_Val), + XN => (if Config.Execute_Never + then Cortex_M_SVD.MPU.I_Disabled + else Cortex_M_SVD.MPU.I_Enabled), + others => <>); + end Configure_Region; + + -------------------- + -- Disable_Region -- + -------------------- + + procedure Disable_Region (Number : Region_Number) is + begin + MPU_Periph.RNR := (REGION => HAL.UInt8 (Number), others => <>); + MPU_Periph.RASR := (ENABLE => False, others => <>); + end Disable_Region; + +end Cortex_M.MPU; diff --git a/arch/ARM/cortex_m/src/cortex_m-mpu.ads b/arch/ARM/cortex_m/src/cortex_m-mpu.ads new file mode 100644 index 000000000..dd5df2ca6 --- /dev/null +++ b/arch/ARM/cortex_m/src/cortex_m-mpu.ads @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------ +-- -- +-- Copyright (C) 2026, AdaCore -- +-- -- +-- Redistribution and use in source and binary forms, with or without -- +-- modification, are permitted provided that the following conditions are -- +-- met: -- +-- 1. Redistributions of source code must retain the above copyright -- +-- notice, this list of conditions and the following disclaimer. -- +-- 2. Redistributions in binary form must reproduce the above copyright -- +-- notice, this list of conditions and the following disclaimer in -- +-- the documentation and/or other materials provided with the -- +-- distribution. -- +-- 3. Neither the name of the copyright holder nor the names of its -- +-- contributors may be used to endorse or promote products derived -- +-- from this software without specific prior written permission. -- +-- -- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- +-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -- +-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -- +-- HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -- +-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- +-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -- +-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- +-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -- +-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -- +-- -- +------------------------------------------------------------------------------ + +-- This package provides subprograms to configure the Memory Protection +-- Unit (MPU) on the Cortex-M7 family of CPU. +-- +-- On Cortex-M7, the MPU is required when the D-cache is enabled in order +-- to prevent speculative reads from causing bus contention on external +-- memory interfaces (e.g., FMC/SDRAM). Without MPU configuration, the +-- default memory map treats all external memory as Normal, allowing the +-- CPU to issue speculative reads that can starve bus masters such as the +-- LTDC display controller. + +with HAL; +with System; + +package Cortex_M.MPU is + + type Region_Number is range 0 .. 7; + + type Region_Size is + (Size_32B, Size_64B, Size_128B, Size_256B, + Size_512B, Size_1KB, Size_2KB, Size_4KB, + Size_8KB, Size_16KB, Size_32KB, Size_64KB, + Size_128KB, Size_256KB, Size_512KB, Size_1MB, + Size_2MB, Size_4MB, Size_8MB, Size_16MB, + Size_32MB, Size_64MB, Size_128MB, Size_256MB, + Size_512MB, Size_1GB, Size_2GB, Size_4GB); + + for Region_Size use + (Size_32B => 16#04#, Size_64B => 16#05#, + Size_128B => 16#06#, Size_256B => 16#07#, + Size_512B => 16#08#, Size_1KB => 16#09#, + Size_2KB => 16#0A#, Size_4KB => 16#0B#, + Size_8KB => 16#0C#, Size_16KB => 16#0D#, + Size_32KB => 16#0E#, Size_64KB => 16#0F#, + Size_128KB => 16#10#, Size_256KB => 16#11#, + Size_512KB => 16#12#, Size_1MB => 16#13#, + Size_2MB => 16#14#, Size_4MB => 16#15#, + Size_8MB => 16#16#, Size_16MB => 16#17#, + Size_32MB => 16#18#, Size_64MB => 16#19#, + Size_128MB => 16#1A#, Size_256MB => 16#1B#, + Size_512MB => 16#1C#, Size_1GB => 16#1D#, + Size_2GB => 16#1E#, Size_4GB => 16#1F#); + + type Access_Permission is + (No_Access, + Privileged_RW, + Privileged_RW_Unprivileged_RO, + Full_Access, + Privileged_RO, + Privileged_RO_Unprivileged_RO); + + for Access_Permission use + (No_Access => 0, + Privileged_RW => 1, + Privileged_RW_Unprivileged_RO => 2, + Full_Access => 3, + Privileged_RO => 5, + Privileged_RO_Unprivileged_RO => 6); + + subtype TEX_Level is HAL.UInt3; + + subtype Subregion_Disable is HAL.UInt8; + + type Region_Configuration is record + Number : Region_Number; + Base_Address : System.Address; + Size : Region_Size; + Subregion_Disable : MPU.Subregion_Disable := 16#00#; + TEX : TEX_Level := 0; + Access_Permission : MPU.Access_Permission := Full_Access; + Execute_Never : Boolean := False; + Shareable : Boolean := False; + Cacheable : Boolean := False; + Bufferable : Boolean := False; + end record; + + -- Enable/disable control bits for HAL_MPU_Enable + type MPU_Control is record + Hard_Fault_NMI_Enable : Boolean; + -- When True, the MPU is enabled during hard fault, NMI, and FAULTMASK + Privileged_Default : Boolean; + -- When True, enables the default memory map as a background region + -- for privileged access + end record; + + procedure Enable (Control : MPU_Control); + -- Enable the MPU with the specified control options. + -- DSB and ISB are issued after enabling. + + procedure Disable; + -- Disable the MPU. DSB and ISB are issued after disabling. + + procedure Configure_Region (Config : Region_Configuration); + -- Configure a single MPU region. The region is enabled upon return. + + procedure Disable_Region (Number : Region_Number); + -- Disable a single MPU region. + +end Cortex_M.MPU; From daecb0a82845f8972181fe3e960a785e098c8764 Mon Sep 17 00:00:00 2001 From: Pat Rogers Date: Fri, 8 May 2026 11:14:08 -0500 Subject: [PATCH 2/3] Move new MPU source files to dedicated directory specific to supported Cortex-M families. Created new directory arch/ARM/cortex_m/src/mpu_cm4_cm7/ and moved the two source files defining the MPU facility into that directory. Updated the scripts/config/archs.py file to include that new source directory for the supported MCU families (all the M4 and M7 boards, excluding the M0). Manually updated all the relevant gpr files to reference that new directory. --- .../cortex_m/src/{ => mpu_cm4_cm7}/cortex_m-mpu.adb | 0 .../cortex_m/src/{ => mpu_cm4_cm7}/cortex_m-mpu.ads | 12 +++--------- boards/feather_stm32f405/feather_stm32f405_full.gpr | 1 + boards/feather_stm32f405/feather_stm32f405_sfp.gpr | 1 + boards/stm32_f4ve/stm32_f4ve_full.gpr | 1 + boards/stm32_f4ve/stm32_f4ve_sfp.gpr | 1 + .../stm32f407_discovery/stm32f407_discovery_full.gpr | 1 + .../stm32f407_discovery/stm32f407_discovery_sfp.gpr | 1 + .../stm32f429_discovery/stm32f429_discovery_full.gpr | 1 + .../stm32f429_discovery/stm32f429_discovery_sfp.gpr | 1 + .../stm32f469_discovery/stm32f469_discovery_full.gpr | 1 + .../stm32f469_discovery/stm32f469_discovery_sfp.gpr | 1 + boards/stm32f4xx_m/stm32f4xx_m_full.gpr | 1 + boards/stm32f4xx_m/stm32f4xx_m_sfp.gpr | 1 + .../stm32f746_discovery/stm32f746_discovery_full.gpr | 1 + .../stm32f746_discovery/stm32f746_discovery_sfp.gpr | 1 + .../stm32f769_discovery/stm32f769_discovery_full.gpr | 1 + .../stm32f769_discovery/stm32f769_discovery_sfp.gpr | 1 + scripts/config/archs.py | 2 ++ 19 files changed, 21 insertions(+), 9 deletions(-) rename arch/ARM/cortex_m/src/{ => mpu_cm4_cm7}/cortex_m-mpu.adb (100%) rename arch/ARM/cortex_m/src/{ => mpu_cm4_cm7}/cortex_m-mpu.ads (91%) diff --git a/arch/ARM/cortex_m/src/cortex_m-mpu.adb b/arch/ARM/cortex_m/src/mpu_cm4_cm7/cortex_m-mpu.adb similarity index 100% rename from arch/ARM/cortex_m/src/cortex_m-mpu.adb rename to arch/ARM/cortex_m/src/mpu_cm4_cm7/cortex_m-mpu.adb diff --git a/arch/ARM/cortex_m/src/cortex_m-mpu.ads b/arch/ARM/cortex_m/src/mpu_cm4_cm7/cortex_m-mpu.ads similarity index 91% rename from arch/ARM/cortex_m/src/cortex_m-mpu.ads rename to arch/ARM/cortex_m/src/mpu_cm4_cm7/cortex_m-mpu.ads index dd5df2ca6..9d8ceb52e 100644 --- a/arch/ARM/cortex_m/src/cortex_m-mpu.ads +++ b/arch/ARM/cortex_m/src/mpu_cm4_cm7/cortex_m-mpu.ads @@ -29,15 +29,9 @@ -- -- ------------------------------------------------------------------------------ --- This package provides subprograms to configure the Memory Protection --- Unit (MPU) on the Cortex-M7 family of CPU. --- --- On Cortex-M7, the MPU is required when the D-cache is enabled in order --- to prevent speculative reads from causing bus contention on external --- memory interfaces (e.g., FMC/SDRAM). Without MPU configuration, the --- default memory map treats all external memory as Normal, allowing the --- CPU to issue speculative reads that can starve bus masters such as the --- LTDC display controller. +-- This package provides support for configuring the Memory Protection +-- Unit (MPU) on Cortex-M3, -M4, and -M7 MCUs. It does not support the M0+ +-- family, nor the M33. with HAL; with System; diff --git a/boards/feather_stm32f405/feather_stm32f405_full.gpr b/boards/feather_stm32f405/feather_stm32f405_full.gpr index 2507b10ef..bd53b55da 100644 --- a/boards/feather_stm32f405/feather_stm32f405_full.gpr +++ b/boards/feather_stm32f405/feather_stm32f405_full.gpr @@ -98,6 +98,7 @@ library project Feather_STM32F405_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/feather_stm32f405/feather_stm32f405_sfp.gpr b/boards/feather_stm32f405/feather_stm32f405_sfp.gpr index dae9e57b0..4609622f7 100644 --- a/boards/feather_stm32f405/feather_stm32f405_sfp.gpr +++ b/boards/feather_stm32f405/feather_stm32f405_sfp.gpr @@ -98,6 +98,7 @@ library project Feather_STM32F405_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32_f4ve/stm32_f4ve_full.gpr b/boards/stm32_f4ve/stm32_f4ve_full.gpr index c712fb880..49eb0f889 100644 --- a/boards/stm32_f4ve/stm32_f4ve_full.gpr +++ b/boards/stm32_f4ve/stm32_f4ve_full.gpr @@ -100,6 +100,7 @@ library project STM32_F4VE_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32_f4ve/stm32_f4ve_sfp.gpr b/boards/stm32_f4ve/stm32_f4ve_sfp.gpr index 892d2d50f..d946e1138 100644 --- a/boards/stm32_f4ve/stm32_f4ve_sfp.gpr +++ b/boards/stm32_f4ve/stm32_f4ve_sfp.gpr @@ -100,6 +100,7 @@ library project STM32_F4VE_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f407_discovery/stm32f407_discovery_full.gpr b/boards/stm32f407_discovery/stm32f407_discovery_full.gpr index 478d348f8..be627e374 100644 --- a/boards/stm32f407_discovery/stm32f407_discovery_full.gpr +++ b/boards/stm32f407_discovery/stm32f407_discovery_full.gpr @@ -99,6 +99,7 @@ library project STM32F407_Discovery_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f407_discovery/stm32f407_discovery_sfp.gpr b/boards/stm32f407_discovery/stm32f407_discovery_sfp.gpr index df574867d..9af95a752 100644 --- a/boards/stm32f407_discovery/stm32f407_discovery_sfp.gpr +++ b/boards/stm32f407_discovery/stm32f407_discovery_sfp.gpr @@ -99,6 +99,7 @@ library project STM32F407_Discovery_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f429_discovery/stm32f429_discovery_full.gpr b/boards/stm32f429_discovery/stm32f429_discovery_full.gpr index a6c44080f..cb9bbab77 100644 --- a/boards/stm32f429_discovery/stm32f429_discovery_full.gpr +++ b/boards/stm32f429_discovery/stm32f429_discovery_full.gpr @@ -102,6 +102,7 @@ library project STM32F429_Discovery_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f42x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f429x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f429_discovery/stm32f429_discovery_sfp.gpr b/boards/stm32f429_discovery/stm32f429_discovery_sfp.gpr index 072112f9e..3d4d16dc9 100644 --- a/boards/stm32f429_discovery/stm32f429_discovery_sfp.gpr +++ b/boards/stm32f429_discovery/stm32f429_discovery_sfp.gpr @@ -102,6 +102,7 @@ library project STM32F429_Discovery_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f42x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f429x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f469_discovery/stm32f469_discovery_full.gpr b/boards/stm32f469_discovery/stm32f469_discovery_full.gpr index e978f924f..b7c185135 100644 --- a/boards/stm32f469_discovery/stm32f469_discovery_full.gpr +++ b/boards/stm32f469_discovery/stm32f469_discovery_full.gpr @@ -103,6 +103,7 @@ library project STM32F469_Discovery_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f46_79x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f46_79x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f469_discovery/stm32f469_discovery_sfp.gpr b/boards/stm32f469_discovery/stm32f469_discovery_sfp.gpr index 61efafd04..95e2aa1cf 100644 --- a/boards/stm32f469_discovery/stm32f469_discovery_sfp.gpr +++ b/boards/stm32f469_discovery/stm32f469_discovery_sfp.gpr @@ -103,6 +103,7 @@ library project STM32F469_Discovery_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f46_79x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f46_79x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f4xx_m/stm32f4xx_m_full.gpr b/boards/stm32f4xx_m/stm32f4xx_m_full.gpr index 7f9f39546..f4a6b1fc0 100644 --- a/boards/stm32f4xx_m/stm32f4xx_m_full.gpr +++ b/boards/stm32f4xx_m/stm32f4xx_m_full.gpr @@ -100,6 +100,7 @@ library project STM32F4XX_M_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f4xx_m/stm32f4xx_m_sfp.gpr b/boards/stm32f4xx_m/stm32f4xx_m_sfp.gpr index 561a4ec89..29bb76ec9 100644 --- a/boards/stm32f4xx_m/stm32f4xx_m_sfp.gpr +++ b/boards/stm32f4xx_m/stm32f4xx_m_sfp.gpr @@ -100,6 +100,7 @@ library project STM32F4XX_M_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f746_discovery/stm32f746_discovery_full.gpr b/boards/stm32f746_discovery/stm32f746_discovery_full.gpr index 6bea0adf2..dedd769fe 100644 --- a/boards/stm32f746_discovery/stm32f746_discovery_full.gpr +++ b/boards/stm32f746_discovery/stm32f746_discovery_full.gpr @@ -103,6 +103,7 @@ library project STM32F746_Discovery_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/cache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f7x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f7x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f746_discovery/stm32f746_discovery_sfp.gpr b/boards/stm32f746_discovery/stm32f746_discovery_sfp.gpr index 1c6b2921b..3d5793dca 100644 --- a/boards/stm32f746_discovery/stm32f746_discovery_sfp.gpr +++ b/boards/stm32f746_discovery/stm32f746_discovery_sfp.gpr @@ -103,6 +103,7 @@ library project STM32F746_Discovery_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/cache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f7x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f7x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f769_discovery/stm32f769_discovery_full.gpr b/boards/stm32f769_discovery/stm32f769_discovery_full.gpr index 8c8b24199..3b74b5261 100644 --- a/boards/stm32f769_discovery/stm32f769_discovery_full.gpr +++ b/boards/stm32f769_discovery/stm32f769_discovery_full.gpr @@ -103,6 +103,7 @@ library project STM32F769_Discovery_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/cache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f7x9/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f7x9/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/stm32f769_discovery/stm32f769_discovery_sfp.gpr b/boards/stm32f769_discovery/stm32f769_discovery_sfp.gpr index 6be34b8d0..84c9666a5 100644 --- a/boards/stm32f769_discovery/stm32f769_discovery_sfp.gpr +++ b/boards/stm32f769_discovery/stm32f769_discovery_sfp.gpr @@ -103,6 +103,7 @@ library project STM32F769_Discovery_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/cache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f7x9/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f7x9/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/scripts/config/archs.py b/scripts/config/archs.py index cc0eada28..dfc5d3e4b 100644 --- a/scripts/config/archs.py +++ b/scripts/config/archs.py @@ -21,6 +21,7 @@ def load_cpu_config(config): config.add_source_dir('arch/ARM/cortex_m/src/fpu', origin) config.add_source_dir('arch/ARM/cortex_m/src/nocache', origin) config.add_source_dir('arch/ARM/cortex_m/src/nvic_cm4_cm7', origin) + config.add_source_dir('arch/ARM/cortex_m/src/mpu_cm4_cm7', origin) elif cpu == "ARM Cortex-M7F": config.add_source_dir('arch/ARM/cortex_m/src', origin) @@ -28,6 +29,7 @@ def load_cpu_config(config): config.add_source_dir('arch/ARM/cortex_m/src/fpu', origin) config.add_source_dir('arch/ARM/cortex_m/src/cache', origin) config.add_source_dir('arch/ARM/cortex_m/src/nvic_cm4_cm7', origin) + config.add_source_dir('arch/ARM/cortex_m/src/mpu_cm4_cm7', origin) elif cpu == "RISC-V32": config.add_source_dir('arch/RISC-V/src/', origin) From 50869abde17540a19095d8bbdf79530489db28e1 Mon Sep 17 00:00:00 2001 From: Pat Rogers Date: Fri, 8 May 2026 11:14:08 -0500 Subject: [PATCH 3/3] Move new MPU source files to dedicated directory specific to supported Cortex-M families. Created new directory arch/ARM/cortex_m/src/mpu_cm4_cm7/ and moved the two source files defining the MPU facility into that directory. Updated the scripts/config/archs.py file to include that new source directory for the supported MCU families (all the M4 and M7 boards, excluding the M0). Manually updated all the relevant gpr files to reference that new directory. --- boards/nucleo_f446ze/nucleo_f446ze_full.gpr | 1 + boards/nucleo_f446ze/nucleo_f446ze_sfp.gpr | 1 + 2 files changed, 2 insertions(+) diff --git a/boards/nucleo_f446ze/nucleo_f446ze_full.gpr b/boards/nucleo_f446ze/nucleo_f446ze_full.gpr index 2afa572b6..4fd72d615 100644 --- a/boards/nucleo_f446ze/nucleo_f446ze_full.gpr +++ b/boards/nucleo_f446ze/nucleo_f446ze_full.gpr @@ -99,6 +99,7 @@ library project NUCLEO_F446ZE_Full is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition diff --git a/boards/nucleo_f446ze/nucleo_f446ze_sfp.gpr b/boards/nucleo_f446ze/nucleo_f446ze_sfp.gpr index 2bf9f654c..ca790a4ab 100644 --- a/boards/nucleo_f446ze/nucleo_f446ze_sfp.gpr +++ b/boards/nucleo_f446ze/nucleo_f446ze_sfp.gpr @@ -99,6 +99,7 @@ library project NUCLEO_F446ZE_SFP is Src_Dirs_Root & "/arch/ARM/cortex_m/src/fpu", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nocache", -- From arch definition Src_Dirs_Root & "/arch/ARM/cortex_m/src/nvic_cm4_cm7", -- From arch definition + Src_Dirs_Root & "/arch/ARM/cortex_m/src/mpu_cm4_cm7", -- From arch definition Src_Dirs_Root & "/arch/ARM/STM32/devices/stm32f40x/", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/svd/stm32f40x", -- From MCU definition Src_Dirs_Root & "/arch/ARM/STM32/drivers/", -- From MCU definition